Intel 6300ESB ICH User manual

Order Number: 300641-004US
Notice: The Intel®6300ESB I/O Controller Hub may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Intel® 6300ESB I/O Controller Hub
Datasheet
November 2007

Intel®6300ESB I/O Controller Hub
DS November 2007
2Order Number: 300641-004US
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OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel®6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published
specifications.which may cause the product to deviate from published specifications. which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
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Copyright © 2007, Intel Corporation. All rights reserved.

Intel®6300ESB I/O Controller Hub
November 2007 DS
Order Number: 300641-004US 3
—Intel®6300ESB ICH
Intel®6300ESB I/O Controller Hub
Product Features
•8-Bit Hub Interface
— 266 Mbyte/s maximum throughput
— Parallel Termination scheme for longer
trace lengths
— Supports Lower Voltages as per Hub
Interface 1.5 spec
•PCI-X Bus I/F
— Supports PCI-X Rev 1.0 Specification at
66 MHz
— Supports PCI Rev 2.2 Specification at 33
MHz
— Support external master devices on PCI
— 4 @ PCI 33 MHz
— 2 @ PCI 64/66 MHz
— 4 @ PCI-X 64/66 MHz (two slots and
two soldered down devices)
— Support for 64-bit addressing on PCI-X
using DAC protocol
•PCI Bus I/F
— Supports PCI 32b/33 MHz
— 120 Mbyte/s throughput
— Supports PCI Rev 2.2 Specification at 33
MHz
— Supports 4 external master devices @
33 MHz
— Support for 44-bit addressing on PCI
using DAC protocol.
— 4 slots supported
•Integrated IDE Controller
— Supports “Native Mode” Register and
Interrupts
— Supports faster PIO timings for non-
data cycles
— Independent timing of up to four drives,
with separate Primary and Secondary
IDE cable connections
— Supports Ultra 100 DMA Mode Transfers
up to 100 Mbytes/s for reads from disk;
88.88 Mbytes/s for writes to disk, as
well as Ultra66 and Ultra33 DMA modes.
— PIO Mode four transfers up to 14
Mbytes/s
•Integrated Serial ATA Host Controllers
— Independent DMA operation on two
ports
— Data transfer rates up to 150 Mbyte/s
— Alternate Device ID and RAID Class
Code option for support of Soft RAID
—
•Power Management Logic
— ACPI 1.0 compliant
— ACPI-defined power states S1 (Stop
Grant), S3 (STR), S4 (STD), S5 (SOFF)
— ACPI Power Management Timer
—SMI#Generation
—PCIPME#
— Supports THRMTRIP# input,
SYS_RESER# input and SLP_S4#
output
— Support for APM-based legacy power
management for non-ACPI
implementations
•External Glue Integration
— Integrated Pull-up, Pull-down and Series
Termination resistors on IDE, CPU I/F
— Integrated Pull-down and Series
resistors on USB
•Enhanced Hub I/F buffers improve routing
flexibility (Not available with all Memory
Controller Hubs)
•Firmware Hub (FWH) I/F supports BIOS
Memory size up to 8 Mbytes
•Low Pin Count (LPC) I/F
— New: No ISA/X-Bus support
— Allows connections of devices such as
Super I/O, microcontrollers, customers
ASICs
— Supports two Master/DMA devices
— Memory size up to 8 Mbytes
•Enhanced DMA Controller
— Two cascaded 8237 DMA controllers
—SupportsLPCDMA
— Supports DMA Collection Buffer to
provide
Type-F DMA performance for all DMA
channels
•Real-Time Clock
— 256-byte battery-backed CMOS RAM
•System TCO Reduction Circuits
— Timers to generate SMI# and Reset
upon detection of system hang
— Interrupt capability to OS-specific
manageability extension and OS
capability to call TCO BIOS Timers to
detect improper CPU reset
— Alert On Lan (AOL) to enable heartbeats
and system event reporting via LAN
controller
—SupportsCPUBIST
— Supports ability to disable external
devices

Intel®6300ESB ICH—
Intel®6300ESB I/O Controller Hub
DS November 2007
4Order Number: 300641-004US
•USB
— Includes one EHCI USB2 host
controllers, a total of four ports (shared
with the UHCI ports)
— Two UHCI Host Controllers for a total of
four ports (shared with EHCI ports)
— New: supports a USB 2.0 High-speed
Debug Port
— Supports wake-up from sleeping states
S1-S4
— Supports legacy Keyboard/Mouse
software with USB-based keyboard and
mouse
•SMBus
— Flexible SMBus/SMLink architecture to
optimize for ASF and eliminate board
requirements of SMBus 2.0 compliance
— Supports SMBus 2.0 Specification
— Host interface allows CPU to
communicate via SMBus
— Slave interface allows an external
Microcontroller to access system
resources
— Compatible with most 2-wire
components that are also I2C
compatible
•AC'97 Link for Audio and Telephony
CODECs
— New: Third AC_SDATA_IN Line for three
codec support
— AC’97 2.2 compliant
— New: Independent bus master logic for
8 channels (PCM In/Out, Mic 1 Input,
Mic 2 Input, Modem In/Out, S/PDIF
Out)
— Separate independent PCI functions for
Audio and Modem
— Support for up four to six channels of
PCM audio output (full AC3 decode)
— Support for 20-bit sample
— Support for ACPI device states - D0 and
D3
•Interrupt Controller
— Supports up to 12 PCI interrupt pins;
four are not shared
— Two cascaded 82C59 with 15 interrupts
— Supports PCI scheme for delivering
interrupts as write cycles (MSI)
— Integrated I/O APIC capability with 24
interrupts
— Supports Serial Interrupt Protocol
— Supports Front-Side Message Interrupt
Delivery
•New: Multimedia Timers based on 82C54
— Includes three timer comparators
— System timer, Refresh request, Speaker
tone output
— One-shot and periodic interrupts
supported
•New: Watchdog Timer
— Two-Stage Watchdog with independent
count values for each stage
— First stage generates an INT or SMI
— Second stage drives external pin active
until cleared by a system reset or power
cycle
— Configuration option for write-once
enabling (count values can still change)
— Configurable granularity from 1µs to 10
min
•New: Integrated 16550 compatible UARTs
— Enable/disable per UARTs
— Serial interrupts
— Can disable when external SIO used
•New: Port 60/64 Emulation
— Programmable interrupt generation on
writes
— Positive decode to Port 60/64 emulation
registers
•GPIO
— Four GPOs capable of directly driving
LEDs
— Two GPOs maintain state during and
after reset
•1.5 V operation with 3.3 V I/O. 5 V
tolerance on many buffers, including IDE.
•Package 37.5 x 37.5 mm 689 BGA
•Process P859.6

Intel®6300ESB I/O Controller Hub
November 2007 DS
Order Number: 300641-004US 5
—Intel®6300ESB ICH
System Block Diagrams
Figure 1. Workstation/PC Model
B2475-02
CPU
Graphics
SM Bus
Memory
1GB to 4 GB
Hublink 1.5
AGP
HL 1.5
PCI
Intel
®
875P MCH
Intel
®
6300ESB
I/O
Controller
Hub
GBE
PCI-X
GBE / SCSI
LPC
FWH / SIO IDE Hard Disk
SATA Hard Disk
SATA Hard Disk
IDE Hard Disk /
CD-DVD
USB 2.0
Legacy Peripherals
AC'97
GPIO

Intel®6300ESB ICH—
Intel®6300ESB I/O Controller Hub
DS November 2007
6Order Number: 300641-004US
Figure 2. Low to Mid-Range Communication Appliance Model (Diskless)
B2476-02
CPU
Memory
256 MB
to 1GB
Hublink
Processor System Bus
HL 1.5
GBE
PCI-X
GBE /
2D Graphics
Hard Disk
SIO
GPIO's
SM Bus
Intel
®
875P MCH
Intel
®
6300ESB
I/O
Controller
Hub

Intel®6300ESB I/O Controller Hub
November 2007 DS
Order Number: 300641-004US 7
—Intel®6300ESB ICH
Figure 3. Value Server, Ultra-Dense Server and Low-End Server Blade
B2477-03
CPU
SM Bus
Memory
1GB to 2 GB
Processor System Bus
Hublink 1.5
HL 1.5
GBE
PCI
2D Graphics
PCI-X
GBE
LPC
BMC
IDE Hard Disk
Hard Disk
SATA Hard Disk
SATA Hard Disk
IDE
USB 2.0
GPIO
Intel
®
E7210 MCH
Intel
®
6300ESB
I/O
Controller
Hub

Intel®6300ESB ICH—Contents
Intel®6300ESB I/O Controller Hub
DS November 2007
8Order Number: 300641-004US
Contents
1Introduction............................................................................................................49
1.1 About This Document.........................................................................................49
2 Intel
®6300ESB ICH and System Clock Domains .....................................................53
3 Signal Description....................................................................................................55
3.1 Hub Interface to Host Controller ..........................................................................55
3.2 Firmware Hub Interface......................................................................................56
3.3 PCI Interface.....................................................................................................57
3.4 PCI-X Interface .................................................................................................60
3.5 SATA Interface..................................................................................................64
3.6 IDE Interface ....................................................................................................64
3.7 LPC I/F.............................................................................................................66
3.8 Interrupt Interface.............................................................................................66
3.9 USB Interface....................................................................................................67
3.10 Power Management Interface..............................................................................68
3.11 CPU Interface....................................................................................................69
3.12 SMBus Interface................................................................................................71
3.13 System Management Interface............................................................................71
3.14 Real Time Clock Interface ...................................................................................71
3.15 Other Clocks .....................................................................................................72
3.16 Miscellaneous Signals.........................................................................................72
3.17 AC’97 Link........................................................................................................73
3.18 Universal Asynchronous Receive and Transmit (UART0,1) .......................................73
3.19 General Purpose I/O...........................................................................................74
3.20 Power and Ground .............................................................................................76
3.21 Pin Straps.........................................................................................................77
3.21.1 Functional Straps....................................................................................77
3.22 Revision and Device ID Table ..............................................................................78
4Intel
®6300ESB ICH Power Planes and Pin States....................................................79
4.1 Power Planes.....................................................................................................79
4.2 Integrated Pull-Ups and Pull-Downs......................................................................80
4.3 IDE Integrated Series Termination Resistors..........................................................81
4.4 Output and I/O Signals Planes and States .............................................................81
4.5 Power Planes for Input Signals ............................................................................83
5 Functional Description .............................................................................................91
5.1 Hub Interface to PCI Bridge (D30:F0)...................................................................91
5.1.1 PCI Bus Interface....................................................................................91
5.1.2 PCI-to-PCI Bridge Model ..........................................................................92
5.1.3 IDSEL to Device Number Mapping.............................................................92
5.1.4 SERR# Functionality................................................................................92
5.1.5 Parity Error Detection..............................................................................95
5.1.6 Standard PCI Bus Configuration Mechanism................................................96
5.1.6.1 Type 0 to Type 0 Forwarding ......................................................96
5.1.6.2 Type 1 to Type 0 Conversion.......................................................96
5.1.7 PCI Dual Address Cycle (DAC) Support ......................................................97
5.2 LPC Bridge (with System and Management Functions) (D31:F0)...............................97
5.2.1 LPC Cycle Types .....................................................................................98
5.2.1.1 Start Field Definition..................................................................98
5.2.1.2 Cycle Type/Direction (CYCTYPE + DIR).........................................99
5.2.1.3 SIZE........................................................................................99
5.2.1.4 SYNC.......................................................................................99

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Contents—Intel®6300ESB ICH
5.2.1.5 SYNC Time-Out ...................................................................... 100
5.2.1.6 SYNC Error Indication.............................................................. 100
5.2.1.7 LFRAME# Usage ..................................................................... 101
5.2.1.8 I/O Cycles.............................................................................. 102
5.2.1.9 Bus Master Cycles................................................................... 102
5.2.1.10 LPC Power Management........................................................... 102
5.2.1.11 Configuration and Intel®6300ESB ICH Implications .................... 102
5.3 DMA Operation (D31:F0).................................................................................. 103
5.3.1 DMA Overview ..................................................................................... 103
5.3.2 Channel Priority ................................................................................... 104
5.3.2.1 Fixed Priority.......................................................................... 104
5.3.2.2 Rotating Priority ..................................................................... 104
5.3.3 Address Compatibility Mode................................................................... 104
5.3.4 Summary of DMA Transfer Sizes ............................................................ 105
5.3.4.1 Address Shifting When Programmed for 16-Bit I/O Count by Words105
5.3.5 Autoinitialize........................................................................................ 105
5.3.6 Software Commands............................................................................. 106
5.3.6.1 Clear Byte Pointer Flip-Flop ...................................................... 106
5.3.6.2 DMA Master Clear ................................................................... 106
5.3.6.3 Clear Mask Register ................................................................ 106
5.4 LPC DMA........................................................................................................ 106
5.4.1 Asserting DMA Requests........................................................................ 106
5.4.2 Abandoning DMA Requests .................................................................... 107
5.4.3 General Flow of DMA Transfers............................................................... 108
5.4.4 Terminal Count (TC)............................................................................. 108
5.4.5 Verify Mode......................................................................................... 108
5.4.6 DMA Request Deassertion...................................................................... 108
5.4.7 SYNC Field/LDRQ# Rules....................................................................... 109
5.5 8254 Timers (D31:F0) ..................................................................................... 110
5.5.1 Counter 0, System Timer ...................................................................... 110
5.5.2 Counter 1, Refresh Request Signal.......................................................... 110
5.5.3 Counter 2, Speaker Tone....................................................................... 110
5.5.4 Timer Programming.............................................................................. 110
5.5.5 Reading from the Interval Timer............................................................. 111
5.5.5.1 Simple Read........................................................................... 112
5.5.5.2 Counter Latch Command.......................................................... 112
5.5.5.3 Read Back Command .............................................................. 113
5.6 8259 Interrupt Controllers (PIC) (D31:F0).......................................................... 113
5.6.1 Interrupt Handling................................................................................ 114
5.6.1.1 Generating Interrupts.............................................................. 114
5.6.1.2 Acknowledging Interrupts ........................................................ 115
5.6.1.3 Hardware/Software Interrupt Sequence ..................................... 115
5.6.2 Initialization Command Words (ICWx)..................................................... 115
5.6.2.1 ICW1 .................................................................................... 116
5.6.2.2 ICW2 .................................................................................... 116
5.6.2.3 ICW3 .................................................................................... 116
5.6.2.4 ICW4 .................................................................................... 116
5.6.3 Operation Command Words (OCW)......................................................... 116
5.6.4 Modes of Operation .............................................................................. 117
5.6.4.1 Fully Nested Mode................................................................... 117
5.6.4.2 Special Fully-Nested Mode........................................................ 117
5.6.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 117
5.6.4.4 Specific Rotation Mode (Specific Priority).................................... 117
5.6.4.5 Poll Mode............................................................................... 118
5.6.4.6 Cascade Mode ........................................................................ 118
5.6.4.7 Edge and Level Triggered Mode ................................................ 118
5.6.4.8 End of Interrupt Operations...................................................... 118

Intel®6300ESB ICH—Contents
Intel®6300ESB I/O Controller Hub
DS November 2007
10 Order Number: 300641-004US
5.6.4.9 Normal End of Interrupt ...........................................................119
5.6.4.10 Automatic End of Interrupt Mode...............................................119
5.6.5 Masking Interrupts................................................................................119
5.6.5.1 Masking on an Individual Interrupt Request ................................119
5.6.5.2 Special Mask Mode ..................................................................119
5.6.6 Steering PCI Interrupts..........................................................................119
5.6.7 Special Handling of IRQ1 and IRQ12........................................................120
5.7 Advanced Interrupt Controller (APIC) (D29:F5)....................................................121
5.7.1 Interrupt Handling ................................................................................121
5.7.2 SMI/NMI/INIT/ExtINT Delivery Modes......................................................121
5.7.3 Boot Interrupt......................................................................................122
5.7.4 Interrupt Mapping.................................................................................123
5.7.5 APIC Bus Functional Description..............................................................124
5.7.5.1 APIC Bus Arbitration ................................................................125
5.7.5.2 Bus Message Formats ..............................................................126
5.7.6 PCI Message-Based Interrupts................................................................132
5.7.6.1 Theory of Operation.................................................................132
5.7.6.2 Registers and Bits Associated with PCI Interrupt Delivery .............133
5.7.7 Processor System Bus Interrupt Delivery .................................................133
5.7.7.1 Theory of Operation.................................................................133
5.7.7.2 Edge-Triggered Operation.........................................................134
5.7.7.3 Level-Triggered Operation ........................................................134
5.7.7.4 Registers Associated with Processor System Bus Interrupt Delivery 134
5.7.7.5 Interrupt Message Format ........................................................134
5.8 Serial Interrupt (D31:F0)..................................................................................135
5.8.1 Start Frame .........................................................................................136
5.8.2 Data Frames ........................................................................................136
5.8.3 Stop Frame..........................................................................................137
5.8.4 Specific Interrupts Not Supported via SERIRQ...........................................137
5.8.5 Data Frame Format...............................................................................137
5.9 Real Time Clock (D31:F0).................................................................................138
5.9.1 RTC Overview ......................................................................................138
5.9.1.1 Update Cycles.........................................................................139
5.9.1.2 Interrupts ..............................................................................139
5.9.1.3 Lockable RAM Ranges ..............................................................139
5.9.1.4 Century Rollover .....................................................................139
5.9.1.5 Clearing Battery-Backed RTC RAM .............................................140
5.10 Processor Interface (D31:F0) ............................................................................141
5.10.1 Processor Interface Signals ....................................................................141
5.10.1.1 A20M# ..................................................................................141
5.10.1.2 INIT#....................................................................................141
5.10.1.3 FERR#/IGNNE# (Coprocessor Error) ..........................................142
5.10.1.4 NMI.......................................................................................143
5.10.1.5 STPCLK# and CPUSLP# Signals.................................................143
5.10.2 Dual Processor Issues ...........................................................................143
5.10.2.1 Signal Differences ...................................................................143
5.10.2.2 Dual Processor Power Management............................................143
5.11 Power Management (D31:F0)............................................................................145
5.11.1 Features..............................................................................................145
5.11.2 Intel®6300ESB ICH Power States and Transition Rules .............................146
5.11.3 System Power Planes ............................................................................148
5.11.4 Intel®6300ESB ICH Power Planes ..........................................................148
5.11.5 SMI#/SCI Generation............................................................................149
5.11.6 Dynamic Processor Clock Control ............................................................152
5.11.6.1 Throttling Using STPCLK#.........................................................153
5.11.6.2 Transition Rules among S0/Cx and Throttling States ....................153

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Contents—Intel®6300ESB ICH
5.11.6.3 STPCLK# Implementation Notes ............................................... 154
5.11.7 Sleep States........................................................................................ 155
5.11.7.1 Sleep State Overview .............................................................. 155
5.11.7.2 Initiating Sleep State............................................................... 155
5.11.7.3 Exiting Sleep States ................................................................ 156
5.11.7.4 Sx-G3-Sx, Handling Power Failures ........................................... 157
5.11.8 Thermal Management ........................................................................... 158
5.11.8.1 THRM# Signal ........................................................................ 158
5.11.8.2 THRM# Initiated Passive Cooling............................................... 158
5.11.8.3 THRM# Override Software Bit................................................... 159
5.11.8.4 Processor Initiated Passive Cooling (Via Programmed
Duty Cycle on STPCLK#).......................................................... 159
5.11.8.5 Active Cooling ........................................................................ 159
5.11.9 Event Input Signal Usage ...................................................................... 159
5.11.9.1 PWRBTN# - Power Button........................................................ 159
5.11.9.2 RI# - Ring Indicate ................................................................. 160
5.11.9.3 PME# - PCI Power Management Event ....................................... 161
5.11.9.4 SYS_RESET# Signal................................................................ 161
5.11.9.5 THRMTRIP# Signal.................................................................. 161
5.11.10ALT Access Mode.................................................................................. 162
5.11.10.1Write Only Registers with Read Paths in ALT Access Mode ............ 163
5.11.10.2Programmable Interrupt Controller (PIC) Reserved Bits................ 164
5.11.10.3Read-Only Registers with Write Paths in ALT Access Mode............ 165
5.11.11System Power Supplies, Planes, and Signals ............................................ 165
5.11.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 165
5.11.11.2PWROK Signal........................................................................ 165
5.11.11.3VRMPWRGD Signal.................................................................. 166
5.11.11.4Controlling Leakage and Power Consumption during Low-Power States
167
5.11.12Clock Generators.................................................................................. 167
5.11.13Legacy Power Management Theory of Operation....................................... 168
5.11.13.1Overview............................................................................... 168
5.11.13.2APM Feature Notes.................................................................. 168
5.12 System Management (D31:F0).......................................................................... 168
5.12.1 Overview of System Management Functions............................................. 168
5.12.2 TCO Signal Usage................................................................................. 169
5.12.2.1 Intruder# Signal..................................................................... 169
5.12.2.2 Pin Straps.............................................................................. 169
5.12.2.3 SMLINK Signals ...................................................................... 169
5.12.3 TCO Theory of Operation....................................................................... 170
5.12.3.1 Overview............................................................................... 170
5.12.3.2 Detecting a System Lockup...................................................... 170
5.12.3.3 Handling an OS Lockup............................................................ 170
5.12.3.4 Handling an Intruder............................................................... 171
5.12.3.5 Detecting Improper FWH Programming...................................... 171
5.12.3.6 Handling an ECC Error or Other Memory Error ............................ 171
5.12.4 Heartbeat and Event Reporting through SMLink/SMbus ............................. 172
5.12.4.1 Overview............................................................................... 172
5.13 General Purpose I/O ........................................................................................ 176
5.13.1 GPIO Mapping...................................................................................... 176
5.13.2 Power Wells......................................................................................... 178
5.13.3 SMI# and SCI Routing .......................................................................... 178
5.13.4 Triggering ........................................................................................... 178
5.14 IDE Controller (D31:F1) ................................................................................... 178
5.14.1 Overview ............................................................................................ 178
5.14.2 PIO Transfers ...................................................................................... 179
5.14.2.1 Overview............................................................................... 179

Intel®6300ESB ICH—Contents
Intel®6300ESB I/O Controller Hub
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5.14.2.2 IDE Port Decode......................................................................179
5.14.2.3 IDE Legacy Mode and Native Mode ............................................179
5.14.2.4 PIO IDE Timing Modes .............................................................180
5.14.2.5 IORDY Masking.......................................................................181
5.14.2.6 PIO 32-Bit IDE Data Port Accesses.............................................181
5.14.2.7 PIO IDE Data Port Prefetching and Posting..................................181
5.14.3 Bus Master Function..............................................................................182
5.14.3.1 Physical Region Descriptor Format.............................................182
5.14.3.2 Line Buffer .............................................................................183
5.14.3.3 Bus Master IDE Timings ...........................................................183
5.14.3.4 Interrupts ..............................................................................183
5.14.3.5 Bus Master IDE Operation ........................................................184
5.14.3.6 Error Conditions......................................................................185
5.14.3.7 8237-Like Protocol ..................................................................185
5.14.4 Ultra ATA/33 Protocol............................................................................186
5.14.4.1 Signal Descriptions..................................................................186
5.14.4.2 Operation...............................................................................187
5.14.4.3 CRC Calculation ......................................................................187
5.14.5 Ultra ATA/66 Protocol............................................................................188
5.14.6 Ultra ATA/100 Protocol..........................................................................188
5.14.7 Ultra ATA/33/66/100 Timing ..................................................................188
5.15 SATA Host Controller (D31:F2)..........................................................................189
5.15.1 Overview.............................................................................................189
5.15.2 Theory of Operation..............................................................................189
5.15.2.1 Standard ATA Emulation...........................................................189
5.15.2.2 48-bit LBA Operation (Logical Block Addressing)..........................189
5.15.3 Hot Plug Operation................................................................................189
5.15.4 Power Management Operation................................................................189
5.15.4.1 Power State Mappings..............................................................190
5.15.4.2 Power State Transitions............................................................191
5.15.4.3 SMI Trapping (APM).................................................................191
5.15.5 SATA Interrupts....................................................................................192
5.15.6 SATALED#...........................................................................................192
5.16 Multimedia Event Timers...................................................................................192
5.16.1 Overview.............................................................................................192
5.16.2 Timer Accuracy ....................................................................................193
5.16.3 Interrupt Mapping.................................................................................193
5.16.4 Periodic vs. Non-Periodic Modes..............................................................193
5.16.5 Enabling the Timers ..............................................................................195
5.16.6 Interrupt Levels....................................................................................195
5.16.7 Handling Interrupts...............................................................................195
5.16.8 Issues Related to 64-bit Timers with 32-bit Processors...............................195
5.17 USB UHCI Controllers (D29:F0 and F1)...............................................................196
5.17.1 Overview.............................................................................................196
5.17.2 Data Structures in Main Memory.............................................................196
5.17.2.1 Frame List Pointer ...................................................................196
5.17.2.2 Transfer Descriptors (TD).........................................................197
5.17.2.3 Queue Head (QH)....................................................................201
5.17.3 Data Transfers to/from Main Memory ......................................................202
5.17.3.1 Executing the Schedule............................................................202
5.17.3.2 Processing Transfer Descriptors.................................................203
5.17.3.3 Command Register, Status Register, and TD Status Bit Interaction 204
5.17.3.4 Transfer Queuing ....................................................................204
5.17.4 Data Encoding and Bit Stuffing ...............................................................208
5.17.5 Bus Protocol.........................................................................................208
5.17.5.1 Bit Ordering............................................................................208
5.17.5.2 SYNC Field .............................................................................208

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Contents—Intel®6300ESB ICH
5.17.5.3 Packet Field Formats ............................................................... 208
5.17.5.4 Address Fields........................................................................ 210
5.17.5.5 Frame Number Field................................................................ 211
5.17.5.6 Data Field.............................................................................. 211
5.17.5.7 Cyclic Redundancy Check (CRC)................................................ 211
5.17.6 Packet Formats.................................................................................... 211
5.17.6.1 Token Packets........................................................................ 211
5.17.6.2 Start of Frame Packets ............................................................ 212
5.17.6.3 Data Packets.......................................................................... 212
5.17.6.4 Handshake Packets ................................................................. 213
5.17.6.5 Handshake Responses ............................................................. 213
5.17.7 USB Interrupts..................................................................................... 214
5.17.7.1 Overview............................................................................... 214
5.17.7.2 Transaction Based Interrupts.................................................... 214
5.17.7.3 Non-Transaction Based Interrupts............................................. 216
5.17.8 USB Power Management ....................................................................... 216
5.17.9 USB Legacy Keyboard Operation ............................................................ 217
5.18 USB EHCI Controller (D29:F7)........................................................................... 221
5.18.1 Overview ............................................................................................ 221
5.18.2 EHC Initialization.................................................................................. 221
5.18.2.1 Power On............................................................................... 222
5.18.2.2 BIOS Initialization................................................................... 222
5.18.2.3 Driver Initialization ................................................................. 222
5.18.2.4 EHC Resets............................................................................ 222
5.18.3 Data Structures in Main Memory............................................................. 223
5.18.4 USB 2.0 Enhanced Host Controller DMA................................................... 224
5.18.4.1 Periodic List Execution............................................................. 224
5.18.4.2 Asynchronous List Execution .................................................... 226
5.18.5 Data Encoding and Bit Stuffing............................................................... 227
5.18.6 Packet Formats.................................................................................... 227
5.18.7 USB EHCI Interrupts and Error Conditions ............................................... 227
5.18.7.1 Aborts on USB EHCI-Initiated Memory Reads.............................. 228
5.18.8 USB EHCI Power Management................................................................ 228
5.18.8.1 Pause Feature ........................................................................ 228
5.18.8.2 Suspend Feature..................................................................... 229
5.18.8.3 ACPI Device States ................................................................. 229
5.18.8.4 ACPI System States ................................................................ 229
5.18.8.5 Low-power system Considerations............................................. 229
5.18.9 Interaction with Classic Host Controllers.................................................. 230
5.18.9.1 Port-Routing Logic .................................................................. 230
5.18.9.2 Device Connects..................................................................... 231
5.18.9.3 Device Disconnects ................................................................. 231
5.18.9.4 Effect of Resets on Port-Routing Logic........................................ 232
5.18.10USB 2.0 Legacy Keyboard Operation....................................................... 232
5.18.11USB 2.0 EHCI Based Debug Port............................................................. 232
5.18.11.1Overview............................................................................... 233
5.18.11.2Theory of Operation ................................................................ 233
5.19 SMBus Controller Functional Description (D31:F3) ............................................... 237
5.19.1 Overview ............................................................................................ 237
5.19.2 Host Controller..................................................................................... 238
5.19.2.1 Command Protocols ................................................................ 239
5.19.2.2 I2C Behavior .......................................................................... 249
5.19.2.3 Heartbeat for Use with the External LAN Controller...................... 249
5.19.3 Bus Arbitration..................................................................................... 249
5.19.4 Bus Timing.......................................................................................... 249
5.19.4.1 Clock Stretching ..................................................................... 249
5.19.4.2 Bus Time Out (Intel®6300ESB ICH as SMBus Master)................. 250

Intel®6300ESB ICH—Contents
Intel®6300ESB I/O Controller Hub
DS November 2007
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5.19.5 Interrupts/SMI#...................................................................................250
5.19.6 SMBALERT#.........................................................................................251
5.19.7 SMBus CRC Generation and Checking......................................................251
5.19.8 SMBus Slave Interface...........................................................................251
5.19.8.1 Format of Slave Write Cycle......................................................252
5.19.8.2 Format of Read Command ........................................................254
5.19.8.3 Format of Host Notify Command................................................256
5.20 AC’97 Controller Functional Description (Audio D31:F5, Modem D31:F6).................257
5.20.1 Overview.............................................................................................257
5.20.1.1 PCI Power Management ...........................................................260
5.20.2 AC-Link Overview .................................................................................260
5.20.2.1 AC-link Output Frame (SDOUT).................................................263
5.20.2.2 Output Slot 0: Tag Phase .........................................................263
5.20.2.3 Output Slot 1: Command Address Port.......................................264
5.20.2.4 Output Slot 2: Command Data Port ...........................................264
5.20.2.5 Output Slot 3: PCM Playback Left Channel ..................................264
5.20.2.6 Output Slot 4: PCM Playback Right Channel ................................264
5.20.2.7 Output Slot 5: Modem Codec ....................................................264
5.20.2.8 Output Slot 6: PCM Playback Center Front Channel......................265
5.20.2.9 Output Slots 7-8: PCM Playback Left and Right Rear Channels.......265
5.20.2.10Output Slot 9: Playback Sub Woofer Channel ..............................265
5.20.2.11Output Slots 10-11: Reserved...................................................265
5.20.2.12Output Slot 12: I/O Control ......................................................265
5.20.2.13AC-Link Input Frame (SDIN).....................................................265
5.20.2.14Input Slot 0: Tag Phase ...........................................................267
5.20.2.15Input Slot 1: Status Address Port/Slot Request Bits .....................267
5.20.2.16Input Slot 2: Status Data Port...................................................268
5.20.2.17Input Slot 3: PCM Record Left Channel.......................................268
5.20.2.18Input Slot 4: PCM Record Right Channel.....................................268
5.20.2.19Input Slot 5: Modem Line.........................................................268
5.20.2.20Input Slot 6: Optional Dedicated Microphone Record Data.............268
5.20.2.21Input Slots 7-11: Reserved.......................................................268
5.20.2.22Input Slot 12: I/O Status .........................................................268
5.20.2.23Register Access.......................................................................269
5.20.3 AC-Link Low Power Mode.......................................................................270
5.20.3.1 External Wake Event................................................................270
5.20.4 AC‘97 Cold Reset..................................................................................271
5.20.5 AC‘97 Warm Reset................................................................................271
5.20.6 System Reset.......................................................................................273
5.20.7 Hardware Assist to Determine AC_SDIN Used Per Codec............................273
5.20.8 Software Mapping of AC_SDIN to DMA Engine ..........................................274
6 Register and Memory Mapping...............................................................................275
6.1 PCI Devices and Functions ................................................................................275
6.2 PCI Configuration Map......................................................................................277
6.3 I/O Map..........................................................................................................278
6.3.1 Fixed I/O Address Ranges......................................................................278
6.3.2 Variable I/O Decode Ranges...................................................................281
6.4 Memory Map...................................................................................................283
6.4.1 Boot-Block Update Scheme....................................................................285
7 Hub Interface to PCI Bridge Registers (D30:F0).....................................................287
7.1 PCI Configuration Registers (D30:F0).................................................................287
7.1.1 Offset 00 - 01h: VID—Vendor ID Register (HUB-PCI—D30:F0)....................288
7.1.2 Offset 02 - 03h: DID—Device ID Register (HUB-PCI—D30:F0)....................288
7.1.3 Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0)...................289
7.1.4 Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—D30:F0) ..
290

Intel®6300ESB I/O Controller Hub
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Contents—Intel®6300ESB ICH
7.1.5 Offset 08h: RID—Revision Identification Register
(HUB-PCI—D30:F0).............................................................................. 291
7.1.6 Offset 0Ah: SCC—Sub-Class Code Register (HUB-PCI—D30:F0).................. 291
7.1.7 Offset 0Bh: BCC—Base-Class Code Register
(HUB-PCI—D30:F0).............................................................................. 291
7.1.8 Offset 0Dh: PMLT—Primary Master Latency Timer Register (HUB-PCI—D30:F0) ..
292
7.1.9 Offset 0Eh: HEADTYP—Header Type Register
(HUB-PCI—D30:F0).............................................................................. 292
7.1.10 Offset 18h: PBUS_NUM—Primary Bus Number Register (HUB-PCI—D30:F0). 292
7.1.11 Offset 19h: SBUS_NUM—Secondary Bus Number Register (HUB-PCI—D30:F0)...
293
7.1.12 Offset 1A: SUB_BUS_NUM—Subordinate Bus Number Register (HUB-PCI—
D30:F0)293
7.1.13 Offset 1Bh: SMLT—Secondary Master Latency Timer Register (HUB-PCI—D30:F0)
293
7.1.14 Offset 1Ch: IOBASE—I/O Base Register (HUB-PCI—D30:F0) ...................... 294
7.1.15 Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—D30:F0) ........................ 295
7.1.16 Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI—D30:F0) ... 295
7.1.17 Offset 20 - 21h: MEMBASE—Memory Base Register
(HUB-PCI—D30:F0).............................................................................. 296
7.1.18 Offset 22 - 23h: MEMLIM—Memory Limit Register
(HUB-PCI—D30:F0).............................................................................. 297
7.1.19 Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory
Base Register (HUB-PCI—D30:F0) .......................................................... 298
7.1.20 Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory
Limit Register (HUB-PCI—D30:F0).......................................................... 299
7.1.21 Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-PCI—
D30:F0)299
7.1.22 Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16 Bits Register
(HUB-PCI—D30:F0).............................................................................. 300
7.1.23 Offset 3Ch: INT_LINE—Interrupt Line Register
(HUB-PCI—D30:F0).............................................................................. 300
7.1.24 Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0). 301
7.1.25 Offset 40 - 43h: HI_CMD—Hub Interface Command Control
Register (HUB-PCI—D30:F0).................................................................. 304
7.1.26 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device
Hiding Register (HUB-PCI—D30:F0)........................................................ 305
7.1.27 Offset 50 - 51h: CNF—Intel®6300ESB ICH Configuration Register (HUB-PCI—
D30:F0)306
7.1.28 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-PCI—D30:F0)
307
7.1.29 Offset 70h: MTT—Multi-Transaction Timer Register
(HUB-PCI—D30:F0).............................................................................. 308
7.1.30 Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—D30:F0)309
7.1.31 Offset 90h: ERR_CMD—Error Command Register
(HUB-PCI—D30:F0).............................................................................. 309
7.1.32 Offset 92h: ERR_STS—Error Status Register
(HUB-PCI—D30:F0).............................................................................. 310
7.1.33 Offset F8h - FBh: MANID— Manufacturer’s ID .......................................... 310
8 LPC I/F Bridge Registers (D31:F0) ........................................................................ 311
8.1 PCI Configuration Registers (D31:F0)................................................................. 311
8.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F0) ..................... 312
8.1.2 Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F0)...................... 313
8.1.3 Offset 04 - 05h: PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0)................................................................................ 313

Intel®6300ESB ICH—Contents
Intel®6300ESB I/O Controller Hub
DS November 2007
16 Order Number: 300641-004US
8.1.4 Offset 06 - 07h: PCISTA—PCI Device Status
(LPC I/F—D31:F0) ................................................................................314
8.1.5 Offset 08h: RID—Revision ID Register (LPC I/F—D31:F0)...........................315
8.1.6 Offset 09h: PI—Programming Interface (LPC I/F—D31:F0).........................315
8.1.7 Offset 0Ah: SCC—Sub-Class Code Register
(LPC I/F—D31:F0) ................................................................................315
8.1.8 Offset 0Bh: BCC—Base-Class Code Register
(LPC I/F—D31:F0) ................................................................................316
8.1.9 Offset 0Eh: HEADTYP—Header Type Register
(LPC I/F—D31:F0) ................................................................................316
8.1.10 Offset 40 - 43h: PMBASE—ACPI Base Address
(LPC I/F—D31:F0) ................................................................................317
8.1.11 Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)...........................317
8.1.12 Offset 4E - 4Fh: BIOS_CNTL (LPC I/F—D31:F0)........................................319
8.1.13 Offset 54h: TCO_CNTL—TCO Control (LPC I/F—D31:F0) ............................320
8.1.14 Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address
(LPC I/F—D31:F0) ................................................................................321
8.1.15 Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)..........................321
8.1.16 Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D]
Routing Control (LPC I/F—D31:F0)..........................................................322
8.1.17 Offset 64h: SERIRQ_CNTL—Serial IRQ Control
(LPC I/F—D31:F0) ................................................................................323
8.1.18 Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing
Control (LPC I/F—D31:F0) .....................................................................324
8.1.19 Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—D31:F0).
325
8.1.20 Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F—D31:F0).
325
8.1.21 Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0)326
8.1.22 Offset D0h - D3h: GEN_CNTL—General Control Register
(LPC I/F—D31:F0) ................................................................................327
8.1.23 Offset D4h: GEN_STA—General Status (LPC I/F—D31:F0)..........................329
8.1.24 Offset D5h: BACK_CNTL—Backed Up Control
(LPC I/F—D31:F0) ................................................................................330
8.1.25 Offset D8h: RTC_CONF—RTC Configuration Register
(LPC I/F—D31:F0) ................................................................................331
8.1.26 Offset E0h: COM_DEC—LPC I/F Communication Port
Decode Ranges (LPC I/F—D31:F0)..........................................................332
8.1.27 Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT Decode Ranges (LPC I/F—
D31:F0)333
8.1.28 Offset E2h: SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—D31:F0) ....334
8.1.29 Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—D31:F0).
335
8.1.30 Offset E4h - E5h: GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/F—D31:F0)
336
8.1.31 Offset E6h - E7h: LPC_EN—LPC I/F Enables
(LPC I/F—D31:F0) ................................................................................337
8.1.32 Offset E8h: FWH_SEL1—FWH Select 1 Register
(LPC I/F—D31:F0) ................................................................................339
8.1.33 Offset ECh - EDh: GEN2_DEC—LPC I/F Generic Decode
Range 2 (LPC I/F—D31:F0)....................................................................340
8.1.34 Offset EEh - EFh: FWH_SEL2—FWH Select 2 Register
(LPC I/F—D31:F0) ................................................................................341
8.1.35 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0) .
342
8.1.36 Offset F2h: FUNC_DIS—Function Disable Register
(LPC I/F—D31:F0) ................................................................................343

Intel®6300ESB I/O Controller Hub
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Contents—Intel®6300ESB ICH
8.1.37 Offset F4: ETR1—PCI-X Extended Features Register
(LPC I/F—D31:F0)................................................................................ 345
8.1.38 Offset F8h: Manufacturer’s ID ................................................................ 345
8.2 DMA I/O Registers........................................................................................... 346
8.2.1 DMABASE_CA—DMA Base and Current Address Registers .......................... 348
8.2.2 DMABASE_CC—DMA Base and Current Count Registers............................. 349
8.2.3 DMAMEM_LP—DMA Memory Low Page Registers....................................... 350
8.2.4 DMACMD—DMA Command Register ........................................................ 350
8.2.5 DMASTA—DMA Status Register .............................................................. 351
8.2.6 DMA_WRSMSK—DMA Write Single Mask Register...................................... 352
8.2.7 DMACH_MODE—DMA Channel Mode Register ........................................... 352
8.2.8 DMA Clear Byte Pointer Register............................................................. 353
8.2.9 DMA Master Clear Register .................................................................... 354
8.2.10 DMA_CLMSK—DMA Clear Mask Register .................................................. 354
8.2.11 DMA_WRMSK—DMA Write All Mask Register ............................................ 355
8.3 Timer I/O Registers ......................................................................................... 355
8.3.1 TCW —Timer Control Word Register........................................................ 356
8.3.1.1 RDBK_CMD—Read Back Command............................................ 357
8.3.1.2 LTCH_CMD—Counter Latch Command ....................................... 357
8.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register........................... 358
8.3.3 Counter Access Ports Register................................................................ 360
8.4 8259 Interrupt Controller (PIC) Registers ........................................................... 360
8.4.1 Interrupt Controller I/O MAP.................................................................. 360
8.4.2 ICW1—Initialization Command Word 1 Register........................................ 361
8.4.3 ICW2—Initialization Command Word 2 Register........................................ 362
8.4.4 ICW3—Master Controller Initialization Command Word 3 Register............... 363
8.4.5 ICW3—Slave Controller Initialization Command Word 3 Register................. 363
8.4.6 ICW4—Initialization Command Word 4 Register........................................ 364
8.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register.................... 364
8.4.8 OCW2—Operational Control Word 2 Register............................................ 365
8.4.9 OCW3—Operational Control Word 3 Register............................................ 366
8.4.10 ELCR1—Master Controller Edge/Level Triggered Register ........................... 367
8.4.11 ELCR2—Slave Controller Edge/Level Triggered Register............................. 367
8.5 Advanced Interrupt Controller (APIC0) ............................................................... 368
8.5.1 APIC Register Map................................................................................ 368
8.5.2 IND—Index Register ............................................................................. 369
8.5.3 DAT—Data Register.............................................................................. 369
8.5.4 Offset FEC0_0020h: IRQPA—IRQ Pin Assertion Register............................. 370
8.5.5 Offset FEC0 - EOIR: EOI Register ........................................................... 370
8.5.6 Offset 00h: ID—Identification Register .................................................... 371
8.5.7 Offset 01h: VER—Version Register.......................................................... 372
8.5.8 Offset 02h: ARBID—Arbitration ID Register.............................................. 372
8.5.9 Offset 03h: BOOT_CONFIG—Boot Configuration Register........................... 373
8.5.10 Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection Table 373
8.6 Real Time Clock Registers................................................................................. 375
8.6.1 I/O Register Address Map...................................................................... 375
8.6.2 Indexed Registers ................................................................................ 376
8.6.2.1 RTC_REGA—Register A............................................................ 377
8.6.2.2 RTC_REGB—Register B (General Configuration) .......................... 378
8.6.2.3 RTC_REGC—Register C (Flag Register) ...................................... 380
8.6.3 RTC_REGD—Register D (Flag Register).................................................... 380
8.7 CPU Interface Registers.................................................................................... 381
8.7.1 NMI_SC—NMI Status and Control Register............................................... 381
8.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) ................................... 382
8.7.3 PORT92—Fast A20 and Init Register ....................................................... 382

Intel®6300ESB ICH—Contents
Intel®6300ESB I/O Controller Hub
DS November 2007
18 Order Number: 300641-004US
8.7.4 COPROC_ERR—Coprocessor Error Register...............................................383
8.7.5 RST_CNT—Reset Control Register...........................................................383
8.8 Power Management Registers (D31:F0) ..............................................................384
8.8.1 Power Management PCI Configuration Registers (D31:F0)..........................384
8.8.1.1 Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0).........................................................................385
8.8.1.2 Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0).........................................................................386
8.8.1.3 Offset A4h: GEN_PMCON_3—General PM Configuration 3
Register (PM—D31:F0).............................................................387
8.8.1.4 Offset ACh: RST_CNT2—Reset Control 2 Register (PM—D31:F0)....388
8.8.1.5 Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register
(PM—D31:F0).........................................................................389
8.8.1.6 Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register
(PM—D31:F0).........................................................................390
8.8.1.7 Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7]
Trap Range Register for Devices 4-7 (PM—D31:F0)......................390
8.8.1.8 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register
for Devices 4-7 (PM—D31:F0)...................................................391
8.8.2 APM I/O Decode ...................................................................................392
8.8.2.1 APM_CNT—Advanced Power Management Control Port Register.....392
8.8.2.2 APM_STS—Advanced Power Management Status Port Register ......392
8.8.3 Power Management I/O Registers ...........................................................393
8.8.3.1 PM1_STS—Power Management 1 Status Register.........................394
8.8.3.2 PM1_EN—Power Management 1 Enable Register..........................396
8.8.3.3 PM1_CNT—Power Management 1 Control....................................397
8.8.3.4 PM1_TMR—Power Management 1 Timer Register.........................398
8.8.3.5 PROC_CNT—Processor Control Register......................................398
8.8.3.6 LV2—Level 2 Register ..............................................................400
8.8.3.7 GPE0_STS—General Purpose Event 0 Status Register...................400
8.8.3.8 GPE0_EN—General Purpose Event 0 Enables Register...................404
8.8.3.9 SMI_EN—SMI Control and Enable Register..................................405
8.8.3.10 SMI_STS—SMI Status Register..................................................407
8.8.3.11 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register...................410
8.8.3.12 ALT_GP_SMI_STS—Alternate GPI SMI Status Register..................411
8.8.3.13 MON_SMI—Device Monitor SMI Status and Enable Register...........411
8.8.3.14 DEVACT_STS—Device Activity Status Register.............................412
8.8.3.15 DEVTRAP_EN— Device Trap Enable Register ...............................414
8.8.3.16 BUS_ADDR_TRACK— Bus Address Tracker..................................415
8.8.3.17 BUS_CYC_TRACK— Bus Cycle Tracker........................................415
8.9 System Management TCO Registers (D31:F0)......................................................416
8.9.1 TCO Register I/O Map............................................................................416
8.9.2 TCO1_RLD—TCO Timer Reload and Current Value.....................................417
8.9.3 TCO1_TMR—TCO Timer Initial Value........................................................417
8.9.4 TCO1_DAT_IN—TCO Data In Register......................................................418
8.9.5 TCO1_DAT_OUT—TCO Data Out Register.................................................418
8.9.6 TCO1_STS—TCO1 Status Register...........................................................419
8.9.7 TCO2_STS—TCO2 Status Register...........................................................421
8.9.8 TCO1_CNT—TCO1 Control Register .........................................................422
8.9.9 TCO2_CNT—TCO2 Control Register .........................................................423
8.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .......................................423
8.9.11 Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Register ..............424
8.9.12 Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation Register...424
8.10 General Purpose I/O Registers (D31:F0) .............................................................425
8.10.1 GPIO Register I/O Address Map ..............................................................425
8.10.2 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register ...........426
8.10.3 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select Register....426

Intel®6300ESB I/O Controller Hub
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Contents—Intel®6300ESB ICH
8.10.4 Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output Register.. 427
8.10.5 Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register............... 429
8.10.6 Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal Invert Register................. 430
8.10.7 Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO Use Select 2 Register........ 431
8.10.8 Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2 Register432
8.10.9 Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2 Register ...
432
9 IDE Controller Registers (D31:F1) ......................................................................... 435
9.1 PCI Configuration Registers (IDE—D31:F1)......................................................... 435
9.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1) ..................... 436
9.1.2 Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F1)...................... 436
9.1.3 Offset 04h - 05h: CMD—Command Register (IDE—D31:F1) ....................... 437
9.1.4 Offset 06 - 07h: STS—Device Status Register (IDE—D31:F1)..................... 438
9.1.5 Offset 08h: RID—Revision ID Register (IDE—D31:F1) ............................... 439
9.1.6 Offset 09h: PI—Programming Interface (IDE—D31:F1).............................. 439
9.1.7 Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1) ..................................... 440
9.1.8 Offset 0Bh: BCC—Base Class Code (IDE—D31:F1).................................... 441
9.1.9 Offset 0Dh: MLT—Master Latency Timer (IDE—D31:F1)............................. 441
9.1.10 Offset 10h - 13h: PCMD_BAR—Primary Command Block
Base Address Register (IDE—D31:F1)..................................................... 441
9.1.11 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base
Address Register (IDE—D31:F1)............................................................. 442
9.1.12 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block
Base Address Register (IDE D31:F1)....................................................... 442
9.1.13 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block
Base Address Register (IDE D31:F1)....................................................... 443
9.1.14 Offset 20h - 23h: BM_BASE—Bus Master Base Address Register (IDE—D31:F1)..
443
9.1.15 Offset 24h - 27h: CPBA – IDE Command Posting Base Address................... 444
9.1.16 Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID
(IDE—D31:F1)..................................................................................... 445
9.1.17 Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—D31:F1)......................... 446
9.1.18 Offset 3Ch: INTR_LN—Interrupt Line Register
(IDE—D31:F1)..................................................................................... 446
9.1.19 Offset 3Dh: INTR_PN—Interrupt Pin Register (IDE—D31:F1)...................... 447
9.1.20 IDE_TIM—IDE Timing Register (IDE—D31:F1).......................................... 447
9.1.21 Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE Timing Register (IDE—D31:F1) ...
451
9.1.22 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1). 452
9.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1).
453
9.1.24 IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)..................................................................................... 455
9.2 Bus Master IDE I/O Registers (D31:F1).............................................................. 455
9.2.1 BMIC[P,S]—Bus Master IDE Command Register........................................ 456
9.2.2 BMIS[P,S]—Bus Master IDE Status Register............................................. 457
9.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register .................... 459
10 USB UHCI Controllers Registers............................................................................. 461
10.1 PCI Configuration Registers (D29:F0/F1)............................................................ 461
10.1.1 Offset 00 - 01h: VID—Vendor Identification Register
(USB—D29:F0/F1)................................................................................ 462
10.1.2 Offset 02 - 03h: DID—Device Identification Register
(USB—D29:F0/F1)................................................................................ 462
10.1.3 Offset 04 - 05h: CMD—Command Register
(USB—D29:F0/F1)................................................................................ 463

Intel®6300ESB ICH—Contents
Intel®6300ESB I/O Controller Hub
DS November 2007
20 Order Number: 300641-004US
10.1.4 Offset 06 - 07h: STA—Device Status Register
(USB—D29:F0/F1)................................................................................464
10.1.5 Offset 08h: RID—Revision Identification Register
(USB—D29:F0/F1)................................................................................464
10.1.6 Offset 09h: PI—Programming Interface (USB—D29:F0/F1).........................465
10.1.7 Offset 0Ah: SCC—Sub Class Code Register
(USB—D29:F0/F1)................................................................................465
10.1.8 Offset 0Bh: BCC—Base Class Code Register
(USB—D29:F0/F1)................................................................................465
10.1.9 Offset 0Dh: MLT—Master Latency Timer...................................................465
10.1.10Offset 0Eh: HTYPE—Header Type Register
(USB—D29:F0/F1)................................................................................466
10.1.11Offset 20 - 23h: BASE—Base Address Register
(USB—D29:F0/F1)................................................................................467
10.1.12Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
(USB—D29:F0/F1)................................................................................467
10.1.13Offset 2Eh-2Fh: SID—Subsystem ID (USB—D29:F0/F1).............................468
10.1.14Offset 3Ch: INTR_LN—Interrupt Line Register
(USB—D29:F0/F1)................................................................................468
10.1.15Offset 3Dh: INTR_PN—Interrupt Pin Register
(USB—D29:F0/F1)................................................................................469
10.1.16Offset 60h: USB_RELNUM—USB Release Number Register
(USB—D29:F0/F1)................................................................................469
10.1.17Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/
Mouse Control Register (USB—D29:F0/F1)...............................................469
10.1.18Offset C4h: USB_RES—USB Resume Enable Register (USB—D29:F0/F1)......472
10.2 USB I/O Registers............................................................................................473
10.2.1 Offset 00 - 01h: USBCMD—USB Command Register ..................................473
10.2.2 Offset 02 - 03h: USBSTA—USB Status Register.........................................478
10.2.3 Offset Base + (04 - 05h): USBINTR—Interrupt Enable Register...................479
10.2.4 Offset Base + (06 - 07h): FRNUM—Frame Number Register........................481
10.2.5 Offset Base + (08 - 0Bh): FRBASEADD—Frame List Base Address ...............481
10.2.6 Offset Base + OCh: SOFMOD—Start of Frame Modify Register ....................482
10.2.7 PORTSC[0,1]—Port Status and Control Register........................................483
11 USB EHCI Controller Registers
(D29:F7)485
11.1 USB EHCI Configuration Registers (D29:F7) ........................................................485
11.1.1 Offset 04 - 05h: Command Register........................................................486
11.1.2 Offset 06 - 07h: Device Status ...............................................................487
11.1.3 Offset 08h: RID—Revision ID Register.....................................................489
11.1.4 Offset 09h: Programming Interface.........................................................489
11.1.5 Offset 0Ah: Sub Class Code....................................................................489
11.1.6 Offset 0Bh: Base Class Code ..................................................................490
11.1.7 Offset 0Dh: Master Latency Timer...........................................................490
11.1.8 Offset 10 - 13h: Memory Base Address....................................................490
11.1.9 Offset 2C - 2Dh: USB EHCI Subsystem Vendor ID.....................................491
11.1.10Offset 2E - 2Fh: SID—USB EHCI Subsystem ID.........................................491
11.1.11Offset 34h: Capabilities Pointer...............................................................491
11.1.12Offset 3Ch: Interrupt Line......................................................................492
11.1.13Offset 3Dh: Interrupt Pin.......................................................................492
11.1.14Offset 50h: PCI Power Management Capability ID .....................................492
11.1.15Offset 51h: Next Item Pointer #1............................................................493
11.1.16Offset 52 - 53h: Power Management Capabilities ......................................493
11.1.17Offset 54 - 55h: Power Management Control/Status ..................................494
11.1.18Offset 58h: Debug Port Capability ID.......................................................495