International Rectifier SupIRBuck IRDC3863 User manual

IRDC3863
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USER GUIDE FOR IRDC3863 EVALUATION BOARD
BOARD FEATURES
SupIRBuckTM
DESCRIPTION
•VIN = +12V
•VCC = +5V
•VOUT = +1.05V
•IOUT = 0 to 6A
•FS = 300kHz @ CCM
•L = 2.2µH
•CIN = 22µF (ceramic 1210) + 68µF (electrolytic)
•COUT = 47µF (ceramic 0805) + 150µF (PC-CON)
Additional features include: pre-bias startup,
soft start, power good output, enable input with
voltage monitoring capability and over/under
voltage protection, making the device a very
flexible solution that is suitable for a broad
range of applications.
This user guide contains the schematic, bill of
materials, and operating instructions of the
IRDC3863 evaluation board. Detailed product
specifications, application information and
performance curves at different operating
conditions are available in the IR3863 data
sheet.
The IR3863 SupIRBuckTM
is an easy-to-use,
fully integrated and highly efficient DC/DC
voltage regulator. The onboard constant on
time hysteretic controller and MOSFETs make
IR3863 a space-efficient solution that delivers
up to 6A of precisely controlled output voltage
in a 4mm x 5mm QFN package.
In addition to excellent light load and full load
efficiency, the IR3863 offers features such as:
a 0.5V reference, programmable switching
frequency, temperature compensated over
current protection, thermal shutdown and
optional forced continuous conduction mode.

IRDC3863
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CONNECTIONS and OPERATING INSTRUCTIONS
Table 1. Connections
Connection Signal Name
VIN (TP2) VIN
PGND (TP5) Ground for VIN
VCC (TP16) VCC Input
PGND (TP17) Ground for VCC Input
VOUT (TP7) VOUT
(+1.05V)
PGND (TP10) Ground for VOUT
EN (TP4) Enable Input
An input supply in the range of 7 to 16V should be connected from VIN to PGND. A maximum load
of 6A may be connected to VOUT
and PGND. The connection diagram is shown in Fig. 1, and the
inputs and outputs of the board are listed in Table 1.
IRDC3863 has two input supplies, one for biasing (VCC) and the other for input voltage (VIN).
Separate supplies should be applied to these inputs. VCC input should be a well regulated 4.5V to
5.5V supply connected to VCC and PGND. Enable (EN) is controlled by the first switch of SW1, and
FCCM option can be selected by the second switch of SW1. Toggle the switch to the ON position
(marked by a solid square) to enable switching or to select FCCM. The absolute maximum voltage
of the external signal applied to EN (TP4) and FCCM is +8V.
The PCB is a 4-layer board. All layers are 1 oz. copper. IR3863 and other components are mounted
on the top and bottom layers of the board.
The power supply decoupling capacitors, bootstrap capacitor and feedback components are located
close to IR3863. To improve efficiency, the circuit board is designed to minimize the length of the on-
board power ground current path.
LAYOUT

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CONNECTION DIAGRAM
Fig. 1: Connection Diagram of IRDC3863 Evaluation Board
VIN
GROUND
VOUT = +1.05V
GROUND
VCC = +5.0V
EN
FCCM
Control Switch for:
GROUND

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Fig. 2: Board Layout, Top Components
PCB Board Layout
Fig. 3: Board Layout, Bottom Components

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Fig. 4: Board Layout, Top Layer
Fig. 5: Board Layout, Bottom Layer
PCB Board Layout

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Fig. 6: Board Layout, Mid-layer I
Fig. 7: Board Layout, Mid-layer II
PCB Board Layout

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Fig. 8: Schematic of the IRDC3863 Evaluation Board
TP7 TP10
EN
VCC
TP23 VOUTS TP24 PGNDS
C26 open
C27 open
VIN
C7 open
C8 open
C24 open
C9 150uF
C10 47uF
C11 open
C1 1uF
R7 2.80K R8 2.55K
C12 0.1uF
PGOOD ISET
+3.3V
VOUT
VCC
+3. 3V
VIN
TP6 PGND S
TP14 +3. 3V
U1 IR3863
3VCBP
8
FCCM
1
SS
6
PGOOD
3
FF 15
GND1
4
FB
5
GND 17
NC1
7
ISET
2
BOOT 14
VIN 13
VCC
10
NC2
9
PGND
11
PHASE 12
EN 16
C4 0.22uF
VCC
TP4
EN
SW1 EN / FCCM
1
2
4
3
TP17 PGND
C20 0.1uF
TP26 AGND
VSW
C21 1uF
TP11 PGOOD
R9 open
L1 2.2uH
R6 open
TP1 VINS
R4 10K
R3 200K
C13 open
C2 22uF
C16 open
+
C3 68uF
TP2 VIN TP5 PGND
C14 open
C17 open
C18 open
TP16 VCC
FB
R5 10K
C15 open
R10 open
C6 open
TP18 VOLTAGE SENSE
+Vins
1
+Vdd1s
2
+Vdd2s
3
+Vout1s
4
+Vout2s
5-Vout2s 10
-Vdd2s 8
-Vout1s 9
-Vins 6
-Vdd1s 7
R1 10K
FCCM
IR3863
+3. 3V
R11
20
C22 open
TP25 B
C25 1uF
VOUT
TP27 A
+3. 3V
TP28 VID
TP13 SS
VSW
R12 4.99
SS
R2 10K
C19 open
Q1 open
2
1
3
PGND VOUT
R13 open
C23 open

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Bill of Materials

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Fig. 9: Startup Fig. 10: Shutdown
TYPICAL OPERATING WAVEFORMS
Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified
EN
PGOOD
SS
VOUT
EN
PGOOD
SS
VOUT
5V/div 5V/div 1V/div 500mV/div 5ms/div 5V/div 5V/div 1V/div 500mV/div 1ms/div
Fig. 11: DCM (IOUT = 0.1A) Fig. 12: CCM (IOUT
= 5A)
VOUT
PHASE
iL
VOUT
PHASE
iL
20mV/div 10V/div 500mA/div 5µs/div 20mV/div 10V/div 2A/div 2µs/div
PGOOD
VOUT
PGOOD
FB
VOUT
iL
5V/div 1V/div 500mV/div 2A/div 50µs/div5V/div 1V/div 1V/div 5A/div 500µs/div
SS
Fig. 13: Over Current Protection (tested by
shorting VOUT to PGND)
Fig. 14: Over Voltage Protection
(tested by shorting FB to VOUT)
IOUT

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TYPICAL OPERATING WAVEFORMS
Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified
Fig. 15: Load Transient 0-2A Fig. 16: Load Transient 3-5A
VOUT
PHASE
iL
VOUT
PHASE
iL
50mV/div 10V/div 2A/div 50µs/div50mV/div 10V/div 2A/div 50µs/div
TYPICAL PERFORMANCE
VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 6A, TA = 25oC, no airflow
Fig. 17: Thermal Image (IR3863: 60oC, Inductor: 45oC, PCB: 32oC)

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Fig. 18: Efficiency vs. Load Current
TYPICAL OPERATING DATA
VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 0 ~ 6A, TA = 25oC, no airflow,
unless otherwise specified
Fig. 19: Switching Frequency vs. Load Current
Fig. 20: Load Regulation Fig. 21: Line Regulation at 6A Load
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
0123456
Load Current (A)
Output Voltage (V)
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
7 8 9 10111213141516
Input Voltage (V)
Output Voltage (V)
0
50
100
150
200
250
300
350
0123456
Load Current (A)
Switching Frequency (kHz)
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
0.01 0.1 1 10
Load Current (A)
Efficiency

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PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing
should be ≥0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard
extension ensures a large toe fillet that can be easily inspected.
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper, or no less than 0.1mm for 1 oz.
Copper, or no less than 0.23mm for 3 oz. Copper.

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Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled
away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of
0.05mm to accommodate solder resist misalignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥0.15mm due to the high aspect ratio of
the solder resist strip separating the lead lands from the pad land.

IRDC3863
Stencil Design
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the
amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the
center pad, the part will float and the lead lands will open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus
an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part
is pushed into the solder paste.
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IRDC3863
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]
TAC Fax: [phone]
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 06/2011
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