Intersil ISLKU060DEMO1Z User manual

Reference Manual
R34UZ0004EU0100 Rev.1.00 Page 1
Oct 15, 2021 © 2021 Renesas Electronics
Over the last decade satellites and spacecrafts have
seen an exponential increase in the need for
on-board data processing and storage demands.
Additionally, major satellite manufacturers have
recently announced their latest satellites to be
modular, fully digital ,and capable of in-orbit
reconfigurability. To meet these demands, satellite
and payload manufacturers are using high-end
FPGAs, ASICs, and processors. Xilinx’s Kintex
XQRKU060 FPGA is a radiation hardened FPGA that
has comparable performance to commercial
counterparts in demanding computing applications.
The Kintex XQRKU060 requires a complex power
solution with multiple low voltage supply rails that can
deliver high currents and a need for power supply
sequencing to eliminate high inrush currents. In
collaboration with Xilinx and Ibeos, Renesas offers a
Kintex XQRKU060 development board with the FPGA
powered by Renesas’ Radiation Hardened products.
Features
▪Radiation hardened QMLV power solution by
Renesas (MIL-PRF-38535)
▪Radiation tolerant Xilinx Kintex XQRKU060 FPGA
▪4x 4GB DDR3 Memory
▪512MB SPI Flash Memory
▪RJ45 interface for 10/100/1000 Gigabit Ethernet
▪DB9 RS-485 Communication Port
▪JTAG Configuration Header
Power Supply Specifications
▪5VDC ±10% (Banana Jack Connectors)
Related Information
▪ISL70002SEH, ISL70001ASEH, ISL75051ASEH,
ISL70005SEH, ISL70321SEH and ISL70244SEH
device pages
▪Xilinx Radiation Tolerant Kintex FPGA Overview
▪Xilinx Radiation Tolerant Kintex FPGA Datasheet
Figure 1. ISLKU060DEMO1Z Block Diagram
5V
Supply
RS-485
DB9
Ethernet
RJ45 SPI
Flash
4GB
DDR3
4GB
DDR3
4GB
DDR3
4GB
DDR3
JTAG
Header
Power Supply LEDs
Communication and
FPGA status LEDs
0.95V Core Supply Power
Supply
Power
Supply Power Supply
Power Supply
ISLKU060DEMO1Z
Renesas Rad Hard Power Management Reference Design for Xilinx’s Space Grade XQRKU060

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ISLKU060DEMO1Z Reference Manual
Contents
1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Kintex XQRKU060 Power Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Typical Performance Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

R34UZ0004EU0100 Rev.1.00 Page 3
Oct 15, 2021
ISLKU060DEMO1Z Reference Manual
1. Functional Description
The ISLKU060DEMO1Z development platform allows users to prototype and evaluate the performance of the
FPGA in different applications. Figure 1 shows a block diagram of the development board. The board includes 4x
4GB Double Data Rate 3 (DDR3) memory and 2x 256MB SPI flash memory, a Gigabit Ethernet (GbE) port, RS-
485 communication port and a JTAG header for programming. On-board DC/DC Point-of-Load (PoL) Converters
power the FPGA and peripherals from a 5V power supply input.
1.1 Getting Started
1. Power Switch SW1 switches power to the ISLKU060DEMO1Z. Before making connections, ensure it is in the
down (OFF) position.
2. Apply +5VDC to the banana connectors J5 and J6. J5 is positive terminal and J6 is GND.
3. Move SW1 to the up (ON) position to power on board.
4. The LED indicators in the upper right sequence on to indicate power sequencing to the FPGA.
5. When the FPGA is properly powered and configured successfully, the FPGA_PROG_B, FPGA_INIT_B and
FPGA_DONE LEDs in the lower left hand corner of the board illuminate green.
6. Visit the Xilinx Kintex Ultrascale website to download the Vivado Design Suite and get started on your design.
1.2 Kintex XQRKU060 Power Solution
Table 1 summarizes the Renesas part numbers, descriptions and operation conditions of the various DC-DC
converters used in the space grade design.
In addition to the power management ICs in Table 1, two ISL70321SEH quad power supply sequencers and an
ISL70062SEH NMOS load switch control the power-up and power-down sequences of the eight power supply
rails. An ISL70244SEH Radiation Hardened Op-Amp is also used for buffering the VREF of the DDR3 VTT supply.
Table 1. Renesas Power Management Solution for Kintex RT XQRKU060
Part Number Description
Input
Voltage
Output
Voltage Function
ISL70002SEH Radiation Hardened and SEE Hardened 22A
Synchronous Buck Regulator with Current
Sharing
5V 0.95V[1]
1. A mechanical potentiometer, labeled R4781, is available to tune the VCC Core voltage across a range of 0.95V to 0.98V. This feature
allows adjusting to a specific core voltage as determined by the Xilinx Power Estimator (XPE) tool when configuring the Kintex
XQRKU060.
VCC Core
ISL70001ASEH Radiation and SEE Tolerant 3V to 13.2V, 9A
Buck Regulator
5V 2.5V FPGA VCCO
Ethernet AVDD and I/O
1.8V Auxiliary VCC, Auxiliary I/O and
SYSMON ADC
3.3V VCC 3.3V I/O and SPI Flash
ISL75051ASEH 3A, Radiation Hardened, Positive, Ultra-Low
Dropout Regulator
2.5V 1.0V Ethernet DVDD
1.0V GTH Analog VCC
1.2V GTH Termination VTT
1.8V GTH Auxiliary VCC
ISL70005SEH Radiation Hardened Dual Output Point-of-Load,
Integrated Synchronous Buck and Low Dropout
Regulator
5V 1.35V DDR VDDQ
1.35V 0.675V DDR VTT

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ISLKU060DEMO1Z Reference Manual
Figure 2 shows the power tree connections from the two ISL70321SEH sequencer outputs to the enable inputs of
the various DC-DC converters.
The power-up sequence of the power supplies is summarized below:
1. The external 5V supply is monitored by the ISL70321SEH and when it reaches 4.3V, it enables the two
ISL70002SEH set up in current-sharing configuration to provide 0.95V to the FPGA core.
2. When the 0.95V supply reaches 0.8V, an ISL70001ASEH is enabled to provide 2.5V for four down-stream
ISL75051ASEH LDOs.
3. When the 2.5V supply reaches 2.1V, two ISL75051ASEHs are enabled. One provides 1.0V for the DVDD to
the Ethernet controller. The other provides 1.0V for the GTH transceiver Analog VCC. To minimize power
dissipation in the LDO, the ISL75051ASEH input voltage comes from the 2.5V rail.
Figure 2. ISLKU060DEMO1Z Power Tree and Sequencing
Primary
ISL70321SEH
Secondary
ISL70321SEH
0.95V
2x
ISL70002SEH
2.5V
ISL70001ASEH
1.0V
ISL75051ASEH
1.2V
ISL75051ASEH
1.8V
ISL75051ASEH
1.8V
ISL70001ASEH
1.35V/0.675V
ISL70005
3.3V
ISL70001ASEH
ISL70062SEH
+5VDC
5V_PG
0V95_PG
2V5_PG
1V0_PG
1V2_PG
VCC 1V8_PG
MGT 1V8_PG
DDR 1V35_PG
DONE
NEXT
EN 0V95
EN 2V5
EN 1V0
EN 1V2
EN VCC 1V8
EN MGT 1V8
EN 3V3 DDR
DONE
EN 0V95
EN 2V5
EN 1V0
EN 1V2
EN VCC 1V8
EN MGT 1V8
EN 3V3 DDR
EN 3V3 DDR
VCC_INT
VCC_INT_I/O
VCC_BRAM
VCCO_2.5V
AVDD_ETH_PHY
EN 3V3 DDR
VMGTAVCC
VMGTAVTT
VMGTVCCAUX
VCCAUX
VCCAUXIO
VCCADC
VDDR_VDDQ
VDDR_VTT
VCCO_3.3V
1
2
3
4
5
6
7
1
2
3
4
5
6
7
7
7
1.0V
ISL75051ASEH
EN 1V0 DVDD_ETH
3

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ISLKU060DEMO1Z Reference Manual
4. When the 1.0V supply reaches 0.87V, an ISL75051ASEH is enabled to provide 1.2V for the GTH transceiver
Termination VTT. To minimize power dissipation in the LDO, the ISL75051ASEH input voltage comes from the
2.5V rail.
5. When the 1.2V supply reaches 1.0V, an ISL70001ASEH is enabled to provide 1.8V for the Auxiliary VCC,
Auxiliary I/O and to the SYSMON ADC supply.
6. When the 1.8V supply reaches 1.5V, an ISL75051ASEH is enabled to provide 1.8V for the GTH transceiver
Auxiliary VCC. To minimize power dissipation in the LDO, the ISL75051ASEH input voltage comes from the
2.5V rail.
7. When the second 1.8V supply rail reaches 1.5V, the final two supply rails are enabled. An ISL70001ASEH is
enabled to provide 3.3V for the VCC I/O and for the SPI Flash Memory. The ISL70005SEH is enabled to
provide 1.35V for the VDDQ and 0.675V for the VTT of the DDR3 memory. The 0.675V before the VTT rail is
also buffered by an ISL70244SEH op-amp to provide VREF for the DDR3 memory. There is also an
ISL70062SEH NMOS load switch that is turned on by the second 1.8V supply rail, which provides 2.5V for the
FPGA VCC I/O, Ethernet AVDD and I/O.
Figure 3 shows the power-up sequence of the ISLKU060DEMO1Z board.
Figure 3. ISLKU060DEMO1Z Power-Up Sequencing

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ISLKU060DEMO1Z Reference Manual
2. Typical Performance Graphs
Typical performance curves for Figure 9 through Figure 13 are derived from the datasheet of the associated part.
Actual performance on the ISLKU060DEMO1Z may be different due to test conditions.
Figure 4. Output Ripple of ISL70002SEH for the FPGA VCCINT Core Voltage
Figure 5. Output Ripple of ISL75051ASEH for the FPGA 1.0V VMGTAVCC Voltage

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ISLKU060DEMO1Z Reference Manual
Figure 6. Output Ripple of ISL75051ASEH for the FPGA 1.2V VMGTAVTT Voltage
Figure 7. Output Ripple of ISL75051ASEH for the FPGA 1.8V VMGTACCAUX Voltage

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ISLKU060DEMO1Z Reference Manual
Figure 8. ISL70321SEH Power Sequencing Enable
Figure 9. Efficiency vs Load, VIN = 5.0V Figure 10. ISL70002SEH Efficiency, VIN = 5V, 500kHz
Figure 11. ISL70005SEH Buck Efficiency, VIN = 5V, 1MHz Figure 12. ISL70005SEH LDO Load Regulation
70
75
80
85
90
95
100
I
LOAD
(A)
EFFICIENCY (%)
0123456
1.5V
1.2V
1.8V
2.5V 3.3V
50
55
60
65
70
75
80
85
90
95
100
0246810121416182022
Efficiency (%)
Load Current (A)
0.95VOUT 1.2VOUT
1.5VOUT 1.8VOUT
2.5VOUT 3.3VOUT
50
55
60
65
70
75
80
85
90
95
0.0 0.5 1.0 1.5 2.0 2.5
3.0
Efficiency (%)
Load Current (A)
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
Vout = 1.5V
0.740
0.745
0.750
0.755
0.760
0.765
-1.5 -1.0 -0.5 0.0 0.5 1.0
1.5
LDO Voltage (V)
LDO Current (A)
L_VCC = B_VCC = 5V
L_VIN = 1.5V
L_EA+ = 0.75V

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ISLKU060DEMO1Z Reference Manual
Figure 13. ISL75051ASEH Load Regulation, VADJ vs IOUT
0.5160
0.5165
0.5170
0.5175
0.5180
0.5185
0.5190
0.5195
0.5200
0.5205
0.5210
0.5215
0.00 1.00 2.00 3.00 4.00
VADJ (V)
IOUT (A)
128C,Vadj (mV)
25C,Vadj (mV)
-58C,Vadj (mV)

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ISLKU060DEMO1Z Reference Manual
3. Board Design
Figure 14. Top of Board
Figure 15. Bottom of Board

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ISLKU060DEMO1Z Reference Manual
3.1 Layout Guidelines
As the Xilinx Kintex XQRKU060 is a high-performance FPGA, careful consideration must be taken with regards to
the layout for the power management ICs. Per the FPGA datasheet for recommended operating conditions for
each of the supply rails, it can be seen they must operate with the tolerances described. In addition to choosing
the right components for the design, the layout is equally as critical in maintaining the electrical performance within
the tolerance window. The load current transitions from one DC/DC regulator can cause voltage spikes across the
interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate
noise into the circuit and lead to device overvoltage stress. Proper component layout and printed circuit board
design minimizes these voltage spikes. Below are general recommended guidelines for proper layout:
▪Ground planes have two important uses. They should be used to shield the switch node of Buck regulators to
contain radiated EMI. Ground planes are also used to provide low impedance returns for the supply currents.
▪Signal routing should be on dedicated layers. Avoid routing signals on every layer without regard to how layers
above and below may interact with the signal. Typically, the top and bottom layer of the board are dedicated for
signals. Always shield the layer above and below signal layers with ground planes.
▪Keep the signal and power grounds for each IC separate but have them tied together in a low noise area of the
PCB. Note: Be careful that noise or high current paths from the power supply grounds does not disrupt the
signal ground. Avoid placing signal and sensitive analog grounds in the paths of these noise and high current
grounds.
▪Place low ESR ceramic bypass capacitors directly at the power supply inputs of DC/DC regulators. These
capacitors are necessary to filter out any high frequency noise on the power supply traces.
▪Provide enough PCB trace width to carry the power supply currents. This is especially important for the core rail
which provides very high currents. Route the power dissipation across the PCB trace in such a way the thermal
dissipation can be properly carried away from the board.
▪For DC/DC regulator ICs that have a back side EPAD, expose the PCB solder mask to provide proper thermal
transfer from the IC to the PCB. In addition, include the proper amount of vias to maximize thermal
performance. The vias should connect to all ground layers to spread out the heat.

R34UZ0004EU0100 Rev.1.00 Page 12 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
3.2 Schematic Diagrams
Figure 16. Schematic Page 1

R34UZ0004EU0100 Rev.1.00 Page 13 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 17. Schematic Page 2
There is no recommended sequence for
VMGTVCCAUX so MGT1V8 can follow VCC1V8
70001 and 75051 LX rise typically < 15 ms
70001 PGOOD 30 ms from EN
75051 PGOOD 7 ms from EN
PGTMR set to 40ms
TDLY set to 20ms
Primary Sequencer
Cascaded Sequencer
Power LED Indicators
MGT_1V2 VCC_1V8 MGT_1V8 VDDR_1V35
VCC_5V_HK
VCC_0V95 VCC_2V5_HK MGT_1V0
VCC_5V_HK
VCC_5V_HK
VCC_5V_HK
VCC_5V_HK VCC_0V95 VCC_2V5_HK MGT_1V0
MGT_1V2 VCC_1V8 MGT_1V8 VDDR_1V35
EN_0V95
EN_2V5
EN_1V0
EN_1V2
EN_VCC_1V8
EN_MGT_1V8
EN_3V3_1V35_0V675
Title
Size Document Number Rev
A
ISLKU060DEMO1ZA Reference Design
Title
Size Document Number Rev
A
ISLKU060DEMO1ZA Reference Design
Title
Size Document Number Rev
A
ISLKU060DEMO1ZA Reference Design
240
R4846
DS10
GREEN
U463
MMPQ2222A
C1-1
1
C1-2
2
C2-1
3
C2-2
4
C3-1
5
C3-2
6
C4-1
7
C4-2
8B4 9
E4 10
B3 11
E3 12
B2 13
E2 14
B1 15
E1 16
C2944
470nF
10V
10%
R4537
10K
1%
C2940
220nF
25V
10%
VDD
EN1
EN2VM2
VCC5
VREF
EN3
EN4
KILL
GND
DONE
VM1
UP
VM3
VM4
PGTMR
INIT
TDLY
U453
ISL70321SEH
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
0
R4794
0
R4792
0
R4795
24.9K
R4807
1%
0
R4793
DS17
GREEN
2.74kR4838
R4540
10K
1%
36.5k
R4801
DS15
GREEN
36.5k
R4797
R4529
10K
1%
54.9k
R4804
U464
MMPQ2222A
C1-1
1
C1-2
2
C2-1
3
C2-2
4
C3-1
5
C3-2
6
C4-1
7
C4-2
8B4 9
E4 10
B3 11
E3 12
B2 13
E2 14
B1 15
E1 16
R4530
10K
1%
2.74kR4854
2.74kR4857
5.9k
R4810
1.0K
R4815
240
R4853
R4541
10K
1%
C2693
220nF
25V
10%
R4539
10K
1%
VDD
EN1
EN2VM2
VCC5
VREF
EN3
EN4
KILL
GND
DONE
VM1
UP
VM3
VM4
PGTMR
INIT
TDLY
U452
ISL70321SEH
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
24.9K
R4806
1%
240
R4851
36.5k
R4798
36.5k
R4799
5.9k
R4809
2.74kR4841
2.74kR4855
54.9k
R4802
R4543
10K
30.1K
R4740
1%
R4531
10K
1%
R4533
10K
1%
DS13
GREEN
R4742
10K
1%
DS12
GREEN
54.9k
R4805
R4532
10K
1%
DS16
GREEN
2.74kR4840
DS14
GREEN
2.74kR4839
1.0K
R4608
R4534
10K
1%
100K
R4811
C2757
470nF
10V
10%
R4733
10K
1%
54.9k
R4803
24.9K
R4808
1%
C2690
220nF
25V
10%
C2688
220nF
25V
10%
240
R4849
100K
R4812
240
R4852
36.5k
R4800
2.74kR4856
240
R4848
100K
R4813
R4538
10K
1%
240
R4847
0
R4789
30.1K
R4695
1%
0
R4790
DS11
GREEN
240
R4850
0
R4791
100K
R4814

R34UZ0004EU0100 Rev.1.00 Page 14 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 18. Schematic Page 3
Master
Current Share Config
Master: ISHSL = DGND, ISHEN=DVDD, M/S=DVDD
Slave: ISHSL = DVDD, ISHEN=DVDD, M/S=DGND
Fsw programmed to 500kHz
Slave
Current Share Config
Master: ISHSL = DGND, ISHEN=DVDD, M/S=DVDD
Slave: ISHSL = DVDD, ISHEN=DVDD, M/S=DGND
0.95V-0.98V
0.95V-0.98V
Max combined current = 38A
Max current/device = 22A
Efficiency @ 22A = 63%
Maximum power delivered (combined) = 38W
Maximum power dissipated (combined) = 22W
OCP set to 21.9A
SS ramp time = 2.6 ms
Isat_10% = 13.8A
Isat_20% = 22A
Isat_30% = 29.5A
Vary output voltage with R4781
It is recommended to run the
Xilinx Power Estimator (XPE)
on a given design to
establish a set-point
VCC_5V_HK
VCC_5V_HK
VCC_5V_HK
VCC_0V95
VCC_0V95
VCC_5V_HK
VCC_5V_HK
VCC_5V_HK
VCC_5V_HK
VCC_0V95
VCC_5V_HK
EN_0V95
CORE_SENSE+
EN_0V95
R4635
10K
1%
C2910
10V
22UF
+ C3035
47UF
35V
0
R4700
C2935
1000p
50V
1%
0
R4631
C2932
0.1uF
16V
10%
0
R4652
0
R4645
R4639
10K
1%
0
R4697
C861
470nF
10V
10%
TP103
0
R4644
C860
470nF
10V
10%
+ C3019
47UF
35V
10
R4759
1%
C2938
10V
22UF
D13
20V
2 1
2.74k
R4767
1%
+ C2909
470UF
6.3V
0
R4778
C2953
220nF
25V
10%
C3016
4700pF
16V
10%
C2911
1000p
50V
1%
0
R4677
+ C3020
47UF
35V
R4779
1.87k
0.1%
0
R4782
C2923
470nF
10V
10%
0
R4701
L34
29.5A
0.47UH
XGL6060-471MEC
1 2
0
R4665
TP116
C2926
10V
1uF
10%
10
R4783
1%
C2955
0.01uF
TP104
2.74k
R4765
1%
C2925
10V
1uF
10%
0
R4632
TP92
C865
16V
0.01uF
10%
2.74k
R4766
1%
C869
0.1uF
16V
10%
0
R4662
1.0K
R4702
U423
ISL70002SEHVFE
FB
1
ISHA
2
ISHREFA
3
ISHB
4
ISHREFB
5
ISHC
6
ISHREFC
7
AVDD 8
AGND
9
DGND
10
DVDD 11
SS
12
PGOOD 13
ISHCOM
14 ISHSL 15 ISHEN 16
PORSEL
17
TDO 18
TDI 19
TPGM 20
SYNC
22
PVIN10 23
LX10 24
PGND10
25 PGND9 26
LX9 27
PVIN9 28
M/S
29
FSEL
30
NC 31
PVIN8 32
LX8 33
PGND8
34 PGND7 35
LX7 36
PVIN7 37 PVIN6 38
LX6 39
PGND6
40 PGND5 41
LX5 42
PVIN5 43 PVIN4 44
LX4 45
PGND4
46 PGND3 47
LX3 48
NC/HS* 50
SC0
51 SC1
52 LX2 54
PGND2
55 PGND1 56
LX1 57
PVIN1 58
EN
59
OCSSB 60
OCB 61
OCSSA 62
OCA 63
REF
64
PVIN3 49 PVIN2 53
GND
21
HS 65
C2920
470nF
10V
10%
+ C2915
47UF
35V
NI
R4630
C857
470nF
10V
10%
C863
10V
1uF
10%
C2924
470nF
10V
10%
C2921
470nF
10V
10%
C864
10V
1uF
10%
+ C2919
47UF
35V
TP121
1.0K
R4696
0
R4777
R4657
10K
1%
2.74k
R4763
1%
C2927
16V
0.01uF
10%
R4641
1.0K
0.05%
+ C2929
470UF
6.3V
U2
ISL70002SEHVFE
FB
1
ISHA
2
ISHREFA
3
ISHB
4
ISHREFB
5
ISHC
6
ISHREFC
7
AVDD 8
AGND
9
DGND
10
DVDD 11
SS
12
PGOOD 13
ISHCOM
14 ISHSL 15 ISHEN 16
PORSEL
17
TDO 18
TDI 19
TPGM 20
SYNC
22
PVIN10 23
LX10 24
PGND10
25 PGND9 26
LX9 27
PVIN9 28
M/S
29
FSEL
30
NC 31
PVIN8 32
LX8 33
PGND8
34 PGND7 35
LX7 36
PVIN7 37 PVIN6 38
LX6 39
PGND6
40 PGND5 41
LX5 42
PVIN5 43 PVIN4 44
LX4 45
PGND4
46 PGND3 47
LX3 48
NC/HS* 50
SC0
51 SC1
52 LX2 54
PGND2
55 PGND1 56
LX1 57
PVIN1 58
EN
59
OCSSB 60
OCB 61
OCSSA 62
OCA 63
REF
64
PVIN3 49 PVIN2 53
GND
21
HS 65
R4781
10k
10%
C2954
220nF
25V
10%
C2931
10V
22UF
D12
20V
2 1
C2933
6.8nF
10%
50V
C2937
6.8nF
10%
50V
TP94
C859
470nF
10V
10%
C2956
16V
0.01uF
C858
470nF
10V
10%
C2939
10V
22UF
0
R4664
0
R4654
TP93
C2914
6.8nF
10%
50V
C2912
6.8nF
10%
50V
0
R4663
+ C3034
47UF
35V
C2922
470nF
10V
10%
NI
R4651
R4780
10.5k
0.1%
0
R4698
R4656
10K
1%
L33
29.5A
0.47UH
XGL6060-471MEC
1 2
SYNC_0V95
ISHCOM ISHA ISHREFC ISHREFB ISHREFA ISHC ISHB
0V95_MASTER_LX
0V95_SLAVE_LX
SYNC_0V95
ISHA ISHB ISHC ISHREFA ISHREFB ISHREFC ISHCOM
PGOOD_0V95_SLAVE
PGOOD_0V95_MASTER
0V95_REF
0V95_REF
0V95_FB
0V95_FB

R34UZ0004EU0100 Rev.1.00 Page 15 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 19. Schematic Page 4
1.004 V
1.205V
Max current / device = 3A
OCP set just shy of 3A
1.2V Max Dissipation = 3.9W
1.2V Max Delivery = 3.6W
1.0V Max Dissipation = 4.5W
1.0V Max Delivery = 3.0W
1.004 V
Place near Ethernet PHY
VCC_5V_HK
MGT_1V0
VCC_2V5_HK
VCC_2V5_HK
MGT_1V2
VCC_5V_HK
VCC_2V5_HK
VCC_1V0
VCC_5V_HK
EN_1V0
EN_1V2
EN_1V0
Title
Size Document Number
Renesas KU060 Reference Design
Title
Size Document Number
Renesas KU060 Reference Design
Title
Size Document Number
Renesas KU060 Reference Design
C2777
100p
16V
C2784
4700pF
16V
10%
1.0K
R4873
4.32k
R4872
0.1%
1.0K
R4703
C1272
0.1uF
16V
U40 ISL75051ASEH
VIN1
12
VIN2
13
ADJ 8
GND-LID
1
EN
10
OCP
11
VIN3
14
VIN4
15
VIN5
16
VIN6
17
VOUT1 2
VOUT2 3
PG 18
BYP 9
VOUT3 4
VOUT4 5
VOUT5 6
VOUT6 7
BASE-HS
19
TP95
+ C2783
330UF
10V
2.67K
R4706
1%
C3044
10V
22UF
1.47k
R4760
1%
R4876
10K
1%
3.28k
R4816
0.1%
1.0K
R4707
U38 ISL75051ASEH
VIN1
12
VIN2
13
ADJ 8
GND-LID
1
EN
10
OCP
11
VIN3
14
VIN4
15
VIN5
16
VIN6
17
VOUT1 2
VOUT2 3
PG 18
BYP 9
VOUT3 4
VOUT4 5
VOUT5 6
VOUT6 7
BASE-HS
19
U466 ISL75051ASEH
VIN1
12
VIN2
13
ADJ 8
GND-LID
1
EN
10
OCP
11
VIN3
14
VIN4
15
VIN5
16
VIN6
17
VOUT1 2
VOUT2 3
PG 18
BYP 9
VOUT3 4
VOUT4 5
VOUT5 6
VOUT6 7
BASE-HS
19
TP106
C3037
470nF
10V
10% C3040
4700pF
16V
10%
1.47k
R4875
1%
2.67K
R4705
1%
C3041
100p
16V
4.64k
R4817
0.1%
+ C2779
330UF
10V
TP96
R607
10K
1%
C2963
470nF
10V
10%
2.67K
R4871
1%
C2964
470nF
10V
10%
+ C3039
330UF
10V
4.32k
R4681
0.1%
C2774
10V
10uF
10%
TP105
C3043
10V
22UF
C2967
470nF
10V
10%
R4787
10K
1%
TP128
C2780
10V
10uF
10%
C2966
470nF
10V
10%
C3038
470nF
10V
10%
C3045
10V
22UF
1.47k
R4761
1%
4.64k
R4874
0.1%
TP127
C2785
100p
16V
C2945
4700pF
16V
10%
4.32k
R4683
0.1%
C2965
0.1uF
16V
C3042
0.1uF
16V
PGOOD_MGT_1V0
PGOOD_MGT_1V2
PGOOD_VCC_1V0

R34UZ0004EU0100 Rev.1.00 Page 16 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 20. Schematic Page 5
fsw = 850 kHz
DDR Supply
Buck OCP fixed, ~5.3A
Max buck current = 3A
Buck efficiency @ 3A = ~75%
Max buck dissipation = 1.3W
Max buck delivery = 4.0W
Buck soft-start = 2.6 ms
LDO OCP fixed, ~1.65A
Max LDO current = 1A
Max LDO dissipation = 0.7W
Max LDO delivery = 0.7W
LDO soft-start = 1.4 ms
0.674V
1.347V
VCC_5V_HK
VDDR_1V35
VDDR_1V35
VDDR_1V35
VDDR_0V675
VREF_0V675
VDDR_1V35
VCC_5V_HK
VCC_5V_HK
VCC_5V_HK
VCC_5V_HK
VCC_2.5V_HK
EN_3V3_1V35_0V675
Title
Renesas KU060 Reference Design
Title
Renesas KU060 Reference Design
Title
Renesas KU060 Reference Design
C2367
220nF
25V
C2366
10V
1uF
U422
ISL70005SEH
B_SS
1
B_FB
2
B_COMP
3
B_RT
4
B_VCC
5
B_SYNC
6
B_GND1
7
B_GND2
8
VREF
9
B_EN
10
L_EN
11
L_VCC
12
L_SS
13
L_EA+
14 L_EA- 15
L_GND 16
L_PGND 17
L_OUT 18
L_VIN 19
TEST 20
B_VIN1 21
B_LX1 22
B_PGND1 23
B_PGND2 24
B_LX2 25
B_VIN2 26
B_PG 27
L_PG 28
C2709
10V
1uF
C2606
10V
1uF
C2577
50V
680pF
-
+
Lid
NC
U460B
ISL70244SEH
8
7
9
6
4
180
R4709
1%
0
R4196
C1267
10V
10UF
V+
V-
-
+
U460A
ISL70244SEH
3
2
1
10
5
169kR4713
1%
+
C397
470UF
6.3V
C2373
10V
22UF
499
R4478
0.1%
C2575
2.2nF
50V
10%
C1268
10V
10UF
20k
R4156
+
C398
470UF
6.3V
C2952
47nF
16V
10%
C2374
10V
22UF
C2576
1000p
50V
0
R4194
499
R4479
0.1%
C2578
1000p
50V
TP107
0
R4714
C2376
10V
1uF
R41971.0K
0.05%100mW
C1291
50V
82PF
0
R4708
49.9
R4477
R4154
10K
1%
54.9k
R4193
+ C2961
330UF
10V
C2960
470nF
10V
10%
49.9
R4476
0
R4195
0
R4199
L24
9.2A
2.2uH
XAL5030-222MEC
+ C2962
330UF
10V
TP97
24.9K
R4688
1%
C2708
10V
1uF
C2951
0.1uF
16V
10%
R4198 1.0K 0.05%
C2368
10V
1uF
PGOOD_1V35

R34UZ0004EU0100 Rev.1.00 Page 17 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 21. Schematic Page 6
1.802V
Place 0.47uF, 22uF on the 3 sides of part near PVIN
OCP fixed, peak 18A
Max current = 6A
Efficiency @ 6A = 87%
Max dissipation = 1.6W
Max delivery = 11W
Soft-start = 2.6 ms
Max LDO current = 3A
Max LDO dissipation = 2.1W
Max LDO delivery = 5.4W
OCP set just shy of 3A
1.811V
VCC_5V_HK
VCC_5V_HK VCC_1V8
VCC_5V_HK
MGT_1V8
VCC_2V5_HK
VCC_5V_HK
EN_VCC_1V8
EN_MGT_1V8 0
R4594
R4497
1.0K
0.05%
+ C3023
47UF
35V
0
R4496
U39 ISL75051ASEH
VIN1
12
VIN2
13
ADJ 8
GND-LID
1
EN
10
OCP
11
VIN3
14
VIN4
15
VIN5
16
VIN6
17
VOUT1 2
VOUT2 3
PG 18
BYP 9
VOUT3 4
VOUT4 5
VOUT5 6
VOUT6 7
BASE-HS
19
C2766
4700pF
16V
10%
4.32k
R539
0.1%
C2644
10V
1uF
C506
10V
10uF
10%
0
R4495
C2745
470nF
10V10%
0
R4593
C2743
470nF
10V10%
TP110
C1274
0.1uF
16V
1.5k
R4819
0.05%
L27
7.0A
1.0UH
XEL4030-102MEC
C2643
10V
1uF
TP98
240
R4820
C2744
470nF
10V10%
C2648
0.1uF
16V
R4567
10K
1%
+ C2763
330UF
10V
+ C3022
47UF
35V
TP102
C2646
220nF
25V
10%
C2657
4700pF
16V
10%
R4796
10K
1%
U448 ISL70001ASEH
Heatsink 49
PGND1 1
PGND1 2
PGND2 47
PGND3 39
PGND2 48
PGND3 40
PGND4 37
PGND4 38
PGND5 29
PGND5 30
PGND6 27
PGND6 28
LX1 3
PVIN1
5PVIN1
4
SYNC 6
M/S
7
ZAP
8
TDI
9
TDO
10
PGOOD 11
SS 12
DVDD
13
DVDD
14
DGND
15
DGND
16
AGND
17
AGND
18
AVDD
19
REF 20
FB 21
EN
22
PORSEL
23
PVIN2
44
PVIN2
45
PVIN3
42
PVIN3
43
PVIN4
34
PVIN4
35
PVIN5
32
PVIN5
33
PVIN6
24
PVIN6
25
LX2 46
LX3 41
LX4 36
LX5 31
LX6 26
C2741
10V
22UF
C2659
16V
0.01uF
+ C3024
47UF
35V
+ C2647
470UF
6.3V
1.47k
R531
1%
TP99
C1275
470nF
10V
10%
2.67K
R4596
1%
C2765
100p
16V
C2713
10V
22UF
C2742
10V
22UF
499
R4818
0.1%
C2762
470nF
10V
10%
C3021
10V
22UF
VCC_1V8_PGOOD
MGT_1V8_PGOOD

R34UZ0004EU0100 Rev.1.00 Page 18 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 22. Schematic Page 7
3.315V
2.499V
OCP fixed, peak 18A
Max current = 6A
Efficiency @ 6A = 87%
Max dissipation = 3W
Max delivery = 20W
Soft-start = 2.6 ms
OCP fixed, peak 18A
Max continuous current = 6A
Efficiency @ 6A = 87%
Max dissipation = 2.3W
Max delivery = 15.3W
Soft-start = 2.6 ms
VCC_5V_HK
VCC_2V5_HK
VCC_3V3VCC_5V_HK
VCC_2V5_HK
VCC_5V_HK
VCC_2V5
VCC_5V_HK
VCC_5V_HK
EN_2V5
EN_3V3_1V35_0V675
EN_3V3_1V35_0V675
Title
Size Document Number Rev
A
Renesas KU060 Reference Design
Title
Size Document Number Rev
A
Renesas KU060 Reference Design
Title
Size Document Number Rev
A
Renesas KU060 Reference Design
+ C2662
470UF
6.3V
C2712
10V
22UF
R4680
10K
1%
C2679
4700pF
16V
10%
C2666
10V
1uF
C2749
470nF
10V10%
C2669
16V
0.01uF
C2695
0.1uF
16V
+ C3027
47UF
35V
+ C2678
470UF
6.3V
C2665
10V
1uF
C3029
10V
22UF
TP101
+ C3032
47UF
35V
C2753
470nF
10V10%
C2701
16V
0.01uF
U451 ISL70001ASEH
Heatsink 49
PGND1 1
PGND1 2
PGND2 47
PGND3 39
PGND2 48
PGND3 40
PGND4 37
PGND4 38
PGND5 29
PGND5 30
PGND6 27
PGND6 28
LX1 3
PVIN1
5PVIN1
4
SYNC 6
M/S
7
ZAP
8
TDI
9
TDO
10
PGOOD 11
SS 12
DVDD
13
DVDD
14
DGND
15
DGND
16
AGND
17
AGND
18
AVDD
19
REF 20
FB 21
EN
22
PORSEL
23
PVIN2
44
PVIN2
45
PVIN3
42
PVIN3
43
PVIN4
34
PVIN4
35
PVIN5
32
PVIN5
33
PVIN6
24
PVIN6
25
LX2 46
LX3 41
LX4 36
LX5 31
LX6 26
0
R4503
U459
ISL70062
SWI
1VCC 6
ON
7SWO 10
DON
9GND 8
THERM 15
R4516
1.0K
0.05%
+ C3031
47UF
35V
0
R4504
C2663
4700pF
16V
10%
C3033
0.1uF
16V
R4501
1.0K
0.05%
C2700
10V
1uF
C2746
10V
22UF
316
R4821
0.1%
L36
11.1A
1uH
XAL5030-102ME
C2668
0.1uF
16V
C2751
10V
22UF
0
R4566
+ C3026
47UF
35V
L35
11.1A
1uH
XAL5030-102ME
TP100
TP109
C2755
470nF
10V10%
C2754
470nF
10V10%
C2756
10V
1uF
0
R4716
+ C3028
47UF
35V
C2694
220nF
25V
10%
C2752
10V
22UF
+ C3030
47UF
35V
C2711
10V
22UF
R4679
10K
1%
221
R4823
0.1%
C2750
470nF
10V10%
C2748
470nF
10V10%
C2667
220nF
25V
10%
0
R4592
C2747
10V
22UF
TP108
U449 ISL70001ASEH
Heatsink 49
PGND1 1
PGND1 2
PGND2 47
PGND3 39
PGND2 48
PGND3 40
PGND4 37
PGND4 38
PGND5 29
PGND5 30
PGND6 27
PGND6 28
LX1 3
PVIN1
5PVIN1
4
SYNC 6
M/S
7
ZAP
8
TDI
9
TDO
10
PGOOD 11
SS 12
DVDD
13
DVDD
14
DGND
15
DGND
16
AGND
17
AGND
18
AVDD
19
REF 20
FB 21
EN
22
PORSEL
23
PVIN2
44
PVIN2
45
PVIN3
42
PVIN3
43
PVIN4
34
PVIN4
35
PVIN5
32
PVIN5
33
PVIN6
24
PVIN6
25
LX2 46
LX3 41
LX4 36
LX5 31
LX6 26
0
R4788
C3025
10V
22UF
0
R4715
+ C3015
47UF
35V
PGOOD_2V5
PGOOD_3V3

R34UZ0004EU0100 Rev.1.00 Page 19 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 23. Schematic Page 8
Decoupling designed to a 6A load step
Xilinx Reference Decoupling Network Impedance:
BOM-Optimized Decoupling Network Impedance:
Using KEMET's K-SIM capacitor simulation
software we find that the Xilinx design has
peak impedance of about 1.5 mOhm over
frequency. Iterating in the same tool we
derive a network with a similar figure, but
fewer components. This reduces the BOM
and simplifies PCB layout.
Both designs are under Ztarget = 3mOhm.
Title
Size Document Number
Renesas KU060 Reference Design
Title
Size Document Number
Renesas KU060 Reference Design
Title
Size Document Number
Renesas KU060 Reference Design

R34UZ0004EU0100 Rev.1.00 Page 20 Oct 15, 2021 ISLKU060DEMO1Z Reference Manual
Figure 24. Schematic Page 9
3x 470 uF
15x 22 uF
22x 10 uF
6x 1 uF
VCC_1V8
MGT_1V8
MGT_1V2
MGT_1V2
MGT_1V0
VCC_0V95
VCC_0V95
CORE_SENSE+
C2522
10V
10UF
C3013
10V
1uF
C2997
10V
10UF
C2527
10V
22UF
C2895
10V
10UF
C2978
10V
22UF
C2520
10V
10UF
C3004
10V
10UF
C2558
16V
2.2uF
C2995
10V
10UF
C2524
0.1uF
16V
C2986
10V
22UF
XCKU060-1FFVA1517I
U34-18
MGTAVCC_L_1
AB34
MGTAVCC_L_2
AC32
MGTAVCC_L_3
AD34
MGTAVCC_L_4
AE32
MGTAVCC_L_5
AF34
MGTAVCC_L_6
P34
MGTAVCC_L_7
R32
MGTAVCC_L_8
T34
MGTAVCC_L_9
U32
MGTAVCC_L_10
V34
MGTAVCC_L_11
Y34
MGTAVTT_L_1
AA36
MGTAVTT_L_2
AB38
MGTAVTT_L_3
AC36
MGTAVTT_L_4
AD38
MGTAVTT_L_5
AE36
MGTAVTT_L_6
AF38
MGTAVTT_L_7
AG36
MGTAVTT_L_8
N36
MGTAVTT_L_9
P38
MGTAVTT_L_10
R36
MGTAVTT_L_11
T38
MGTAVTT_L_12
U36
MGTAVTT_L_13
V38
MGTAVTT_L_14
W36
MGTAVTTRCAL_L
AF32
MGTAVTTRCAL_RS
AV10
MGTRREF_L
AF33
MGTRREF_RS
AV9
MGTVCCAUX_L_1
AA32
MGTVCCAUX_L_2
W32
MGTAVCC_RN_1 B8
MGTAVCC_RN_2 C6
MGTAVCC_RN_3 D8
MGTAVCC_RN_4 E6
MGTAVCC_RN_5 F8
MGTAVCC_RN_6 G6
MGTAVCC_RN_7 H8
MGTAVCC_RN_8 J6
MGTAVCC_RN_9 K8
MGTAVCC_RN_10 L6
MGTAVCC_RN_11 M8
MGTAVCC_RN_12 N6
MGTAVCC_RN_13 P8
MGTAVCC_RN_14 R6
MGTAVCC_RN_15 U6
MGTAVCC_RS_1 AA6
MGTAVCC_RS_2 AC6
MGTAVCC_RS_3 AE6
MGTAVCC_RS_4 AF8
MGTAVCC_RS_5 AG6
MGTAVCC_RS_6 AH8
MGTAVCC_RS_7 AJ6
MGTAVCC_RS_8 AK8
MGTAVCC_RS_9 AL6
MGTAVCC_RS_10 AM8
MGTAVCC_RS_11 AN6
MGTAVCC_RS_12 AP8
MGTAVCC_RS_13 AR6
MGTAVCC_RS_14 AT8
MGTAVCC_RS_15 AU6
MGTAVCC_RS_16 AV8
MGTAVCC_RS_17 W6
MGTAVTT_RN_1 B4
MGTAVTT_RN_2 C2
MGTAVTT_RN_3 D4
MGTAVTT_RN_4 E2
MGTAVTT_RN_5 F4
MGTAVTT_RN_6 G2
MGTAVTT_RN_7 H4
MGTAVTT_RN_8 J2
MGTAVTT_RN_9 K4
MGTAVTT_RN_10 L2
MGTAVTT_RN_11 M4
MGTAVTT_RN_12 N2
MGTAVTT_RN_13 P4
MGTAVTT_RN_14 R2
MGTAVTT_RN_15 T4
MGTAVTT_RN_16 U2
MGTAVTT_RS_1 AA2
MGTAVTT_RS_2 AB4
MGTAVTT_RS_3 AC2
MGTAVTT_RS_4 AD4
MGTAVTT_RS_5 AE2
MGTAVTT_RS_6 AF4
MGTAVTT_RS_7 AG2
MGTAVTT_RS_8 AH4
MGTAVTT_RS_9 AJ2
MGTAVTT_RS_10 AK4
MGTAVTT_RS_11 AL2
MGTAVTT_RS_12 AM4
MGTAVTT_RS_13 AN2
MGTAVTT_RS_14 AP4
MGTAVTT_RS_15 AR2
MGTAVTT_RS_16 AT4
MGTAVTT_RS_17 AU2
MGTAVTT_RS_18 AV4
MGTAVTT_RS_19 V4
MGTAVTT_RS_20 W2
MGTAVTT_RS_21 Y4
MGTVCCAUX_RN_1 T8
MGTVCCAUX_RN_2 V8
MGTVCCAUX_RS_1 AB8
MGTVCCAUX_RS_2 AD8
C2998
10V
10UF
C2525
0.1uF
16V
C3014
10V
1uF
C3005
10V
10UF
C2555
0.1uF
16V
C2518
10V
10UF
C2991
10V
10UF
R4293
100 63mW
0.02%
+ C2969
470UF
6.3V
C2979
10V
22UF
C2557
16V
2.2uF
C2996
10V
10UF
C3009
10V
1uF
C412
10V
22UF
C2990
10V
10UF
C2999
10V
10UF
C2523
0.1uF
16V
C3006
10V
10UF
C2972
10V
22UF
C2982
10V
22UF
C2563
0.1uF
16V
+ C2970
470UF
6.3V
C2980
10V
22UF
C3010
10V
1uF
C2562
16V
2.2uF
C2989
10V
10UF
C3007
10V
10UF
C3000
10V
10UF
C2976
10V
22UF
C2981
10V
22UF
C2988
10V
10UF
C2992
10V
10UF
C2983
10V
22UF
C2561
16V
2.2uF
+ C2971
470UF
6.3V
C2564
0.1uF
16V
C3011
10V
1uF
C2975
10V
22UF
C2519
10V
10UF
XCKU060-1FFVA1517I
U34-26
VCCINT_1
AA12
VCCINT_2
AA14
VCCINT_3
AA18
VCCINT_4
AA20
VCCINT_5
AA22
VCCINT_6
AA24
VCCINT_7
AB13
VCCINT_8
AB17
VCCINT_9
AB19
VCCINT_10
AB21
VCCINT_11
AB23
VCCINT_12
AC12
VCCINT_13
AC14
VCCINT_14
AC16
VCCINT_15
AC18
VCCINT_16
AC20
VCCINT_17
AC22
VCCINT_18
AC24
VCCINT_19
T11
VCCINT_20
T13
VCCINT_21
T15
VCCINT_22
U12
VCCINT_23
U14
VCCINT_24
U16
VCCINT_25
U18
VCCINT_26
U20
VCCINT_27
U22
VCCINT_28
U24
VCCINT_29
V11
VCCINT_30
V13
VCCINT_31
V15
VCCINT_32
V17
VCCINT_33
V19
VCCINT_34
V21
VCCINT_35
V23
VCCINT_36
V25
VCCINT_37
W12
VCCINT_38
W14
VCCINT_39
W18
VCCINT_40
W20
VCCINT_41
W22
VCCINT_42
W24
VCCINT_43
Y11
VCCINT_44
Y13
VCCINT_45
Y17
VCCINT_46
Y19
VCCINT_47
Y21
VCCINT_48
Y23
VCCINT_49
Y25 VCCINT_IO_1 AA26
VCCINT_IO_2 AB25
VCCINT_IO_3 AC26
VCCINT_IO_4 U26
VCCINT_IO_5 W26
VCCAUX_1 AA30
VCCAUX_2 AC30
VCCAUX_3 T29
VCCAUX_4 U30
VCCAUX_5 W30
VCCAUX_IO_1 AA28
VCCAUX_IO_2 AB27
VCCAUX_IO_3 AB29
VCCAUX_IO_4 AC28
VCCAUX_IO_5 AD29
VCCAUX_IO_6 T27
VCCAUX_IO_7 U28
VCCAUX_IO_8 V27
VCCAUX_IO_9 V29
VCCAUX_IO_10 W28
VCCAUX_IO_11 Y27
VCCAUX_IO_12 Y29
VCCBRAM_1 AA10
VCCBRAM_2 AC10
VCCBRAM_3 U10
VCCBRAM_4 W10
C2987
10V
10UF
C3008
10V
10UF
C3002
10V
10UF
C2560
16V
2.2uF
C3001
10V
10UF
C2984
10V
22UF
C2993
10V
10UF
C2521
10V
10UF
C2974
10V
22UF
C2517
10V
10UF
C2559
16V
2.2uF
C3012
10V
1uF
C2528
10V
22UF
+ C2894
47UF
35V
C2977
10V
22UF
C2973
10V
22UF
C3003
10V
10UF
C2526
0.1uF
16V
C2985
10V
22UF
C2994
10V
10UF