Intersil ISL97671 User manual

1
Application Note 1581
ISL97671/2/3/4IRZ-EVAL Quick Start Guide
This quick start guide pertains to the
ISL97671/2/3/4IRZ-EVAL Evaluation Board. This board
comes populated with 72 LEDs in a 6P12S configuration
to simplify evaluation and testing. Please install the
Sunlight ISL97670 GUI from Intersil’s website, which will
be used to control ISL97671/3/4 parts via I2C. Note the
slave address on the ISL97671, ISL97673 and ISL97674
is hexadecimal 58; see Figure 1. Please refer to
“ISL97671” on page 1, “ISL97672” on page 2,
“ISL97673” on page 2 and “ISL97674” on page 3, for
jumper settings and power-up instructions.
ISL97671
1. Jumpers JP7B, JP8B, JP9, JP10, JP11, JP12 and JP13
should be inserted for LED's in 6P12S configuration.
2. Jumpers in line 1, plus JP14, JP15, JP16, JP17, JP18
and JP19 should be inserted for LED's in 6P10S
configuration.
3. Jumper JP5A, JP3A and JP6A are inserted.
4. Connect the I2C interface board to the
ISL97671/2/3/4IRZ-EVAL Evaluation Board as shown
in Figure 2 for I2C control.
FIGURE 1. EXAMPLE OF GUI INTERFACE
FIGURE 2. I2C INTERFACE BOARD CONNECTED TO ISL97671IRZ-EVAL EVALUATION BOARD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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2August 3, 2010
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5. JP1 should be inserted only if the input fault MOSFET
Q1 is not used.
6. Apply input voltage to the VIN and GND post on the
top left corner of the ISL97671IRZ-EVAL Evaluation
Board.
7. Jumper JP3 should be in the right position and EN
signal from a 2.5V/3.3V logic supply connected to
the EN jumper, J5.
8. Jumper JP8A should be in the top position and PWM
signal from a function generator connected to the
PWMI jumper, J6.
9. Insert JP5A, JP6A and J3A.
10.To enable the board in SMBus mode, write a hex 05
in register 01; by writing a hex 01 in register 01 will
enable DPST (see data sheet FN7631 for more
details); writing a hex 03 in register 01 will allow
PWM dimming only.
11.For non-I2C control of ISL97671, remove the I2C
interface board, JP3A and ground J3(SCL post) and
J4 (SDA post). The board can now be controlled via
the EN and PWMI signal.
12.The LED current is calibrated to 20mA/channel,
which can be changed by measuring current across
JP7B and varying POT R15 by Equation 1:
The measured current divided by six is the LED
current per channel. For example, 120mA measured
current will correspond to 20mA/channel.
13.The PWM dimming frequency is calibrated to 200Hz
on this evaluation board but can be adjusted by
varying POT R11 by Equation 2:
14. ISL97671IRZ-EVAL Evaluation Board should be
powering 6P10S or 6P12S LED's.
ISL97672
1. Jumpers JP7B, JP8B, JP9, JP10, JP11, JP12 and JP13
should be inserted for LED's in 6P12S configuration.
2. Jumpers in line 1, plus JP14, JP15, JP16, JP17, JP18
and JP19 should be inserted for LED's in 6P10S
configuration.
3. Jumper JP8A inserted in top position.
4. Jumper JP3 should be in the right position.
5. JP1 should be inserted only if the input fault MOSFET
Q1 is not used.
6. Apply input voltage to the VIN and GND post on the
top left corner of the ISL97672IRZ-EVAL Evaluation
Board.
7. Apply a 2.5/3.3V signal to EN jumper, J5.
8. Apply a PWM signal from a function generator to
PWMI jumper, J6.
9. The LED current is calibrated to 20mA/channel
which can be changed by measuring current across
JP7B and varying POT R15 by Equation 3:
The measured current divided by six is the LED
current per channel. For example, 120mA measured
current will correspond to 20mA/channel.
10.The boost switching frequency is calibrated to
600kHz on this evaluation board but can be
adjusted by varying POT R11 by Equation 4:
11. At this point, the ISL97672IRZ-EVAL Evaluation
Board should be powering 6P10S or 6P12S LED's.
ISL97673
1. Jumpers JP7B, JP8B, JP9, JP10, JP11, JP12 and JP13
should be inserted for LED's in 6P12S configuration.
2. Jumpers in line 1, plus JP14, JP15, JP16, JP17, JP18
and JP19 should be inserted for LED's in 6P10S
configuration.
3. Jumpers JP3A, JP5A and JP6A are inserted.
4. Connect the I2C interface board to the ISL97673/4IRZ-
EVAL Evaluation Board, as shown in Figure 3.
ILED 401.8 R15 ⁄=(EQ. 1)
FSW 6.66 107
×()R11 ⁄=(EQ. 2)
ILED 401.8 R15
⁄=(EQ. 3)
FSW 510
10
×()R11 ⁄=(EQ. 4)
FIGURE 3. I2C INTERFACE BOARD CONNECTED TO ISL97673IRZ-EVAL EVALUATION BOARD
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3August 3, 2010
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5. JP1 should be inserted only if the input fault MOSFET
Q1 is not used.
6. Apply input voltage to the VIN and GND post on the
top left corner of the ISL97673IRZ-EVAL Evaluation
Board.
For PWMI dimming, only go to Step 7; for SMBus
dimming go to Step 8; for direct PWM go to Step 9;
for DC current adjustment go to Step 10.
7. JP7A in the bottom position corresponds to SEL2 pin
being high, which corresponds to fixed delay;
floating JP7A corresponds to float on SEL2 pin,
which corresponds to equal phase shift; inserting
JP7A in the top position, corresponds to no delay.
8. JP5 inserted in the bottom position
9. Insert JP5A in top position and JP7A in the top
position.
10.Insert JP5 in the top position
11.Jumper JP3 should be in the left position and
EN/PWM signal from function generator connected
to PWMI jumper, J6.
12.To enable the board in SMBUS dimming, write a hex
05 in register 01; writing a hex 01 in register 01 will
enable DPST (see data sheet FN7633 for more
detail); writing a hex 03 in register 01 will only allow
external PWM signal for dimming.
13.The LED current is calibrated to 20mA/channel
which can be changed by measuring current across
JP7B and varying POT R15 by Equation 5:
The measured current divided by six is the LED
current per channel. For example, 120mA measured
current will correspond to 20mA/channel.
14.The PWM dimming frequency is calibrated to 200Hz
on this evaluation board but can be adjusted by
varying POT R11 by Equation 6:
15. At this point, the ISL97673IRZ-EVAL Evaluation
Board should be powering 6P10S or 6P12S LED's.
ISL97674
1. Jumpers JP7B, JP8B, JP9, JP10, JP11, JP12 and JP13
should be inserted for LED's in 6P12S configuration.
2. Jumpers in line 1, plus JP14, JP15, JP16, JP17, JP18
and JP19 should be inserted for LED's in 6P10S
configuration.
3. Insert jumpers JP3A, JP5A and JP6A.
4. Connect the I2C interface board to the
ISL97674IRZ-EVAL Evaluation Board, as shown in
Figure 4.
ILED 401.8 R15 ⁄=(EQ. 5)
FSW 6.66 107
×()R11 ⁄=(EQ. 6)
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4August 3, 2010
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5. Jumper JP3 should be in the left position and
En/PWM signal from function generator connected
to PWMI jumper, J6.
6. JP1 should be inserted only if the input fault MOSFET
Q1 is not used.
7. Apply input voltage to the VIN and GND post on the
top left corner of the ISL97674IRZ-EVAL Evaluation
Board.
8. Insert JP8A in the bottom position and apply a 60Hz
VSYNC signal to VSYNC post, J7.
9. To enable the board in SMBUS control dimming,
write a hex 05 in register 01; for PWM dimming
control, write a hex 03 in register 01.
10.The LED current is calibrated to 20mA/channel
which can be changed by measuring current across
JP7B and varying POT R15 by Equation 7:
The measured current divided by six is the LED
current per channel. For example, 120mA measured
current will correspond to 20mA/channel.
11.The boost switching frequency can be programmed
to either 600kHz or 1.2MHz by writing a '1' or a '0'
in hex register 08, Bit 2. See ISL97674 data sheet,
FN7634, Table 2B for more details.
12. At this point, the ISL97674IRZ-EVAL Evaluation
Board should be powering 6P10S or 6P12S LED's.
FIGURE 4. I2C INTERFACE BOARD CONNECTED TO ISL97674IRZ-EVAL EVALUATION BOARD
ILED 401.8 R15
⁄=(EQ. 7)
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5August 3, 2010
AN1581.0
ISL97671/2/3/4IRZ-EVAL Evaluation Board Schematic
C2
0 .1u F/ 50 V
C7
1uF/10V
C8
3.3nF
L1
10uH
D1
SS25
R2A
10K
R1
358K
C9
100pF/50V
C10
CAP
C3 4 .7u F/ 50 V
R5A
RES1
R2
10k
J7(VSYNC)
VS YN C
J5 (EN)
EN
J4 (SDA)
SDA
J3 (SCL)
SCL
J1(Vin)
VIN= 4.75 ~26V
J9A
LX
R6
4.7k
R7
4.7k
J2 (VLogic)
Vlo gic
JP3A
C4 4 .7u F/ 50 V C5 4 .7u F/ 50 V C6 4 .7u F/ 50 V
C1
10uF/50V
C19
CAP
C17
CAP
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED26
LED25
LED24
LED23
LED22
LED21
LED20
LED19
LED18
LED17
LED16
LED15
LED14
LED27
LED28
LED29
LED30
LED31
LED32
JP8B JP9 JP10 JP11
LED33
LED34
LED35
LED36
LED37
LED38
LED39
LED52
JP12
LED51
LED50
LED49
LED48
LED47
LED46
LED45
LED44
JP13
LED55
LED56
LED57
LED58
LED59
LED60
LED61
LED62
LED64
LED65
LED78
LED77
LED76
LED75
LED74
LED73
LED43
LED42
LED41
LED40
LED53
LED63
LED72
LED54
LED71
LED70
LED69
LED68
LED67
LED66
JP15 JP16 JP17 JP18 JP 19JP14
C14
1nF
C13
1nF
C12
1nF
C11
1nF
C15
1nF
C16
1nF
TP5
CH4
TP6
CH5
ISL97671 - R4 stuffed and R5,C20, C19 = no stuff
ISL97672 - R4 stuffed and R5,C20, C19 = no stuff
ISL97673 - R4 stuffed and R5,C20, C19 = no stuff
ISL97674 - R4 no stuff ed and R5=, C20=, C19=
C3 ~ C6 a re X7R 50V r ated c eram ic c a ps
C4~C6 are reserved pa ds
Y5V ceram ic cap is not recomm ended
TP1
CH0
TP3
CH1
TP2
CH2
TP4
CH3
J 1 0( V o ut )
Vout JP7B
C20
390pF
SDA
SCL
EN
PWM
J9(VDC)
VDC
R21
100
R22
100
JP5A
JP6A
JP4
1
2
3
JP3
HEADER 3
1
2
3
JP8A
HEADER 3
1
2
3
JP7A
HEADER 3
R9
open
For 2 laye rs boa rd, connect top lay er P GND
R11
100k
R13
open
R15
1M
R12
27K
R16
5K
R14
0
R10
0
A1
R5
0 or Open
A3A2
JP23
JP22
JP21
JP20
FAULT
1
VIN
2
EN, EN, EN/PWM, EN/PWM
3
VDC
4
PWM, PWM, SEL1, VSYNC
5
SMBDAT/SDA, _FLAG, SMBDAT/SDA/_FLAG, SDA
6
SMBCLK/SCL, NC, SMBCLK/SCL /SEL2, SCL
7
FP WM, FSW , FP WM, P LLC
8
AGND 9
CH0 10
CH1 11
CH2 12
CH3 13
CH4 14
CH5 15
OVP 16
RSET
17
COMP
18
PGND 19
LX 20
PAD
C
ISL97671~4
ISL97671~4
1
2
3
JP5
HEADER 3
JP1A JP1B JP1C JP1D JP 1E
J6 (PWMI)
PWMI
R23
100
VSYNC
1
2
3
4
5
6
7
8
9
10
HDR1
HEADER10(FMale)
PWM
EN
SCL
SCL
SDA
SDA
SCL
SDA
P1 P3P2
1
2
5
6
4
3
Q1
FDMA530PZ
1 2
WR
C18
Open
ISL97671/2/3/4IRZ-EVAL Evaluation Board Layout
FIGURE 5. TOP LAYER
Application Note 1581

6
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
August 3, 2010
AN1581.0
FIGURE 6. BOTTOM LAYER
ISL97671/2/3/4IRZ-EVAL Evaluation Board Layout (Continued)
Application Note 1581