Intersil ISL28113 User manual

1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Single, Dual, Quad General Purpose Micropower, RRIO
Operational Amplifier
ISL28113, ISL28213, ISL28413
The ISL28113, ISL28213, and ISL28413 are single, dual, and
quad channel general purpose micropower, rail-to-rail input and
output operational amplifiers with supply voltage range of 1.8V
to 5.5V. Key features are a low supply current of 130µA
maximum per channel at room temperature, a low bias current
and a wide input voltage range, which enables the ISL28x13
devices to be excellent general purpose op-amps for a wide range
of applications.
The ISL28113 is available in the SC70-5 and SOT23-5 packages,
the ISL28213 is in the MSOP8, SOIC8, SOT23-8 packages, and
the ISL28413 is in the TSSOP14, SOIC14 packages. All devices
operate over the extended temperature range of -40°C to
+125°C.
Related Literature
•SeeAN1519 for “ISL28213/14SOICEVAL2Z Evaluation Board
User’s Guide”
•SeeAN1520 for “ISL28113/14SOT23EVAL1Z Evaluation
Board User’s Guide”
•SeeAN1542 for “ISL28213/14MSOPEVAL2Z Evaluation Board
User’s Guide”
Features
• Low Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 130µA
• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
• Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2MHz
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20pA, Max.
• Operating Temperature Range. . . . . . . . . . . . .-40°C to +125°C
•Packages
- ISL28113 (Single) . . . . . . . . . . . . . . . . . . . . . SC70-5, SOT23-5
- ISL28213 (Dual). . . . . . . . . . . . . . . . MSOP8, SOIC8, SOT23-8
- ISL28413 (Quad) . . . . . . . . . . . . . . . . . . . . . SOIC14, TSSOP14
Applications
• Power Supply Control/Regulation
• Process Control
• Signal Gain/Buffers
• Active Filters
• Current Shunt Sensing
•Trans-impedanceAmps
IN-
IN+
RF
RREF+
ISL28x13
+5V
V-
V+
RIN-
10kΩ
RIN+
10kΩ
-
+
100kΩ
VREF
100kΩ
VOUT
LOAD
RSENSE
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
GAIN = 10
FIGURE 1. TYPICAL APPLICATION
June 9, 2011
FN6728.5

ISL28113, ISL28213, ISL28413
2FN6728.5
June 9, 2011
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28113FEZ-T7 (Note 1) BJA 5 Ld SC-70 P5.049
ISL28113FEZ-T7A (Note 1) BJA 5 Ld SC-70 P5.049
ISL28113FHZ-T7 (Note 1) BCYA 5 Ld SOT-23 P5.064A
ISL28113FHZ-T7A (Note 1) BCYA 5 Ld SOT-23 P5.064A
ISL28213FUZ 8213Z 8 Ld MSOP M8.118A
ISL28213FUZ-T7 (Note 1) 8213Z 8 Ld MSOP M8.118A
ISL28213FBZ 28213 FBZ 8 Ld SOIC M8.15E
ISL28213FBZ-T7 (Note 1) 28213 FBZ 8 Ld SOIC M8.15E
ISL28213FBZ-T13 (Note 1) 28213 FBZ 8 Ld SOIC M8.15E
Coming Soon
ISL28213FHZ-T7 (Note 1) TBD 8 Ld SOT-23 P8.064
Coming Soon
ISL28213FHZ-T7A (Note 1) TBD 8 Ld SOT-23 P8.064
ISL28413FVZ 28413 FVZ 14 Ld TSSOP MDP0044
ISL28413FVZ-T7 (Note 1) 28413 FVZ 14 Ld TSSOP MDP0044
ISL28413FVZ-T13 (Note 1) 28413 FVZ 14 Ld TSSOP MDP0044
ISL28413FBZ 28413 FBZ 14 Ld SOIC MDP0027
ISL28413FBZ-T7 (Note 1) 28413 FBZ 14 Ld SOIC MDP0027
ISL28413FBZ-T13 (Note 1) 28413 FBZ 14 Ld SOIC MDP0027
ISL28113SOT23EVAL1Z Evaluation Board
ISL28213MSOPEVAL2Z Evaluation Board
ISL28213SOICEVAL2Z Evaluation Board
Coming Soon
ISL28413TSSOPEVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28113, ISL28213, ISL28413. For more information on MSL please
see Techbrief TB363.
Pin Configurations
ISL28113
(5 LD SC-70)
TOP VIEW
ISL28113
(5 LD SOT-23)
TOP VIEW
ISL28213
(8 LD MSOP, 8 LD SOIC, 8 LD SOT-23)
TOP VIEW
IN+
VS-
IN-
VS+
OUT
1
2
3
5
4
OUT
VS-
IN+
VS+
IN-
1
2
3
5
4
OUT_A
IN-_A
IN+_A
VS-
VS+
OUT_B
IN-_B
IN+_B
1
2
3
45
6
7
8

ISL28113, ISL28213, ISL28413
3FN6728.5
June 9, 2011
ISL28413
(14 LD TSSOP, 14 LD SOIC)
TOP VIEW
Pin Configurations (Continued)
OUT_A
IN-_A
IN+_A
VS+
IN+_B
IN-_B
OUT_B
OUT_D
IN-_D
IN+_D
VS-
IN+_C
IN-_C
OUT_C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
5 LD
SC-70
5 LD
SOT-23
8 LD MSOP,
8LDSOIC,
8LDSOT-23
14 LD TSSOP,
14 LD SOIC
OUT
OUT_A
OUT_B
OUT_C
OUT_D
41
1
7
1
7
8
14
Output
CIRCUIT 1
VS- 2 2 4 11 Negative supply voltage
CIRCUIT 2
IN+
IN+_A
IN+_B
IN+_C
IN+_D
13
3
5
3
5
10
12
Positive Input
CIRCUIT 3
IN-
IN-_A
IN-_B
IN-_C
IN-_D
34
2
6
2
6
9
13
Negative Input
VS+ 5 5 8 4 Positive supply voltage See “CIRCUIT 2”
V
+
V-
OUT
V+
V-
CAPACITIVELY
TRIGGERED
ESD CLAMP
IN+IN-
V+
V-

ISL28113, ISL28213, ISL28413
4FN6728.5
June 9, 2011
Absolute Maximum Ratings (TA= +25°C) Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V++ 0.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V++ 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
Machine Model
ISL28113, ISL28213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350V
ISL28413. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
5 Ld SC-70 (Notes 4, 5) . . . . . . . . . . . . . . . . 250 N/A
5 Ld SOT-23 (Notes 4, 5) . . . . . . . . . . . . . . . 225 N/A
8 Ld MSOP (Notes 4, 5). . . . . . . . . . . . . . . . 180 100
8 Ld SOIC Package (Notes 4, 5) . . . . . . . . . 126 90
8 Ld SOT-23 (Notes 4, TBD) . . . . . . . . . . . . 240 TBD
14 Ld TSSOP Package (Notes 4, 5) . . . . . . 120 40
14 Ld SOIC Package (Notes 4, 5). . . . . . . . 90 50
Ambient Operating Temperature Range . . . . . . . . . . . . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is the top of the package.
Electrical Specifications VS+ = 5V, VS- = 0V, RL= Open, VCM = VS/2, TA= +25°C, unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNIT
DC SPECIFICATIONS
VOS Input Offset Voltage -5 0.5 5 mV
-6 6 mV
TCVOS Input Offset Voltage Temperature
Coefficient
-40°C to +125°C 2 10 µV/°C
IOS Input Offset Current 130 pA
IBInput Bias Current ISL28113 -20 3 20 pA
-100 100 pA
ISL28213, ISL28413 -20 3 20 pA
-50 50 pA
Common Mode Input
Voltage Range
- 0.1V +5.1V V
ZIN Input Impedance 1012 Ω
CIN Input Capacitance 1 pF
CMRR Common Mode Rejection Ratio VCM = -0.1V to 5.1V 72 dB
-40°C to +125°C 70 dB
PSRR Power Supply Rejection Ratio VS= 1.8V to 5.5V 71 dB
-40°C to +125°C 70 dB
VOH Output Voltage Swing, High RL = 10kΩ4.985 4.993 V
4.98 V
VOL Output Voltage Swing, Low RL= 10kΩ13 15 mV
20 mV
V+Supply Voltage 1.8 5.5 V

ISL28113, ISL28213, ISL28413
5FN6728.5
June 9, 2011
ISSupply Current per Amplifier RL = OPEN 90 130 µA
170 µA
ISC+ Output Source Short Circuit Current RL = 10Ωto V- -22 mA
ISC- Output Sink Short Circuit Current RL = 10Ωto V+ 16 mA
AC SPECIFICATIONS
GBWP Gain Bandwidth Product VS= ±2.5V
AV= 100, RF= 100kΩ,
RG=1kΩ, RL= 10kΩ to VCM
2MHz
eN VP-P Peak-to-Peak Input Noise Voltage VS= ±2.5V
f = 0.1Hz to 10Hz
14 µVP-P
eNInput Noise Voltage Density VS= ±2.5V
f = 1kHz
55 nV/√(Hz)
iNInput Noise Current Density VS= ±2.5V
f = 1kHz
5fA/√(Hz)
Cin Differential Input Capacitance VS= ±2.5V
f = 1MHz
1.0 pF
Common Mode Input Capacitance 1.3 pF
TRANSIENT RESPONSE
SR Slew Rate 20% to 80% VOUT VOUT = 0.5V to 4.5V 1 V/µs
tr, tf, Small Signal Rise Time, tr10% to 90% VS= ±2.5V
AV= +1, VOUT = 0.05VP-P,
RF=0Ω, RL= 10kΩ, CL= 15pF
100 ns
Fall Time, tf10% to 90% 115 ns
tsSettling Time to 0.1%, 4VP-P Step VS= ±2.5V
AV= +1, RF = 0Ω, RL=10kΩ,
CL= 1.2pF
7.5 µs
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications VS+ = 5V, VS- = 0V, RL= Open, VCM = VS/2, TA= +25°C, unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C, unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNIT

ISL28113, ISL28213, ISL28413
6FN6728.5
June 9, 2011
Typical Performance Curves VS= ±2.5V, VCM = 0V, RL= Open, unless otherwise specified.
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 3. INPUT NOISE VOLTAGE SPECTRAL DENSITY
FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL= 100kΩ, CL = 10pF, VS= ±0.9V
FIGURE 5. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL=100kΩ, CL = 10pF, VS= ±2.5V
FIGURE 6. CMRR vs FREQUENCY, VS= ±2.5 FIGURE 7. PSRR vs FREQUENCY, VS= ±0.9V, ±2.5V
-50
-40
-30
-20
-10
0
10
20
30
40
50
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
IBIAS (pA)
SIMULATION
FREQUENCY (Hz)
10
100
1000
INPUT NOISE VOLTAGE (nV/√Hz)
1 10 100 1k 10k 100k
V+= ±2.5V
AV= 1
10,000
-80
-60
-40
-20
0
20
40
60
80
100
120
0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
OPEN LOOP GAIN (dB)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
PHASE (°)
RL= 100k
SIMULATION
CL= 10pF
PHASE
GAIN
V+= ±0.9V
-80
-60
-40
-20
0
20
40
60
80
100
120
0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
OPEN LOOP GAIN (dB)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
PHASE (°)
RL= 100k
SIMULATION
CL= 10pF
PHASE
GAIN
V+= ±2.5V
0
10
20
30
40
50
60
70
80
0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
CMRR (dB)
SIMULATION
PSRR (dB )
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
100 1k 10k 100k 1M 10M
RL= INF
AV= +1
VCM = 100mVP-P
CL= 4pF
PSRR- VS= ±2.5V
PSRR+ VS= ±0.9V
PSRR- VS= ±0.9V
PSRR+ VS= ±2.5V

ISL28113, ISL28213, ISL28413
7FN6728.5
June 9, 2011
FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 9. FREQUENCY RESPONSE vs VOUT
FIGURE 10. GAIN vs FREQUENCY vs RLFIGURE 11. GAIN vs FREQUENCY vs CL
FIGURE 12. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 13. CROSSTALK, VS= ±2.5V
Typical Performance Curves VS= ±2.5V, VCM = 0V, RL= Open, unless otherwise specified. (Continued)
FREQUENCY (Hz)
GAIN (dB)
100k 1M 10M
10 10k
1k
100
70
-10
0
10
20
30
40
50
60
100M
V+= ±2.5V
VOUT = 50mVP-P
CL= 4pF
RL= 10k
AV= 1
AV= 100
AV= 1000
AV= 10
R
g
= 100, R
f
= 100k
Rg= OPEN, Rf= 0
R
g
= 1k, R
f
= 100k
Rg= 10k, Rf= 100k
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100 1k 10k 100k 1M 10M
VS= ±2.5V
AV= +1
RL= 10k
CL= 4pF
VOUT = 1VP-P
VOUT = 100mVP-P
VOUT = 50mVP-P
VOUT = 10mVP-P
VOUT = 500mVP-P
VOUT = 200mVP-P
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100 1k 10k 100k 1M 10M
V+= ±2.5V
AV= +1
VOUT = 50mVP-P
CL= 4pF
RL= 49.9k
RL= 1k
RL= 499
RL= 100
RL= 10k
RL= 4.99k
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
100k 1M 10M
10k
1k
-4
-3
-2
-1
0
1
2
3
4
5
6
VS= ±2.5V
RL= 10k
AV= +1
VOUT = 50mVP-P
CL= 1004pF
CL= 474pF
CL= 224pF
CL= 104pF
CL= 26pF
CL= 4pF
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
100k 1M 10M
10k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
CL= 4pF
RL= 10k
AV= +1
VOUT = 50mVP-P
VS= ±2.5V
VS= ±0.9V
VS= ±1.25V
VS= ±1.75V
0
20
40
60
80
100
120
140
10 100 1k 10k 100k 1M 10M
CROSS-TALK (dB)
FREQUENCY (Hz)
RL-RECEIVER = 10k
AV= +1
VSOURCE = 1VP-P
CL= 4pF
RL-DRIVER = INF
VS= ±2.5V

ISL28113, ISL28213, ISL28413
8FN6728.5
June 9, 2011
FIGURE 14. SMALL SIGNAL TRANSIENT RESPONSE, VS= ±2.5V FIGURE 15. LARGE SIGNAL TRANSIENT RESPONSE vs RL
VS= ±0.9V, ±2.5V
FIGURE 16. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS= ±0.9V, ±2.5V
FIGURE 17. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS= ±0.9V, ±2.5V
FIGURE 18. % OVERSHOOT vs LOAD CAPACITANCE, VS= ±2.5V
Typical Performance Curves VS= ±2.5V, VCM = 0V, RL= Open, unless otherwise specified. (Continued)
TIME (ns)
SMALL SIGNAL (mV)
-30
-20
-10
0
10
20
30
0 200 400 600 800 1000 1200 1400 1600 1800 2000
RL= 10k
AV= +1
CL= 15pF
VOUT = 50mVP-P
VS= ±2.5V
-3
-2
-1
0
1
2
3
0 2 4 6 8 101214161820
TIME (ms)
LARGE SIGNAL (V)
RL= 10k
AV= +1
CL= 15pF
VOUT = RAIL
VS= ±0.9V
VS= ±2.5V
012345678910
TIME (ms)
INPUT (V)
OUTPUT (V)
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
INPUT
RL= INF
AV=10
CL= 15pF
Rf= 9.09k, Rg= 1k
OUTPUT @ VS=±0.9V
OUTPUT @ VS= ±2.5V
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
012345678910
TIME (ms)
INPUT (V)
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT (V)
INPUT
RL= INF
AV=10
CL= 15pF
Rf= 9.09k, Rg= 1k
OUTPUT @ VS=±0.9V
OUTPUT @ VS= ±2.5V
CAPACITANCE (pF)
10 100 1k 10k
OVERSHOOT (%)
0
10
20
30
40
50
60
70
80
90
OVERSHOOT+
VS= ±2.5V
RL= 10k
AV= 1
VOUT = 50mVP-P
OVERSHOOT-

ISL28113, ISL28213, ISL28413
9FN6728.5
June 9, 2011
Applications Information
Functional Description
The ISL28113, ISL28213 and ISL28413 are single, dual and
quad, CMOS rail-to-rail input, output (RRIO) micropower
operational amplifiers. They are designed to operate from single
supply (1.8V to 5.5V) or dual supply (±0.9V to ±2.75V). The parts
have an input common mode range that extends 100mV above
and below the power supply voltage rails. The output stage can
swing to within 15mV of the supply rails with a 10kΩ load.
Input ESD Diode Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails (see “Pin Descriptions -
Circuit 1” on page 3). For applications where the input voltage
may exceed either power supply voltage by 0.5V or more, an
external series resistor must be used to ensure the input currents
never exceed 20mA (see Figure 19).
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28113, ISL28213 and ISL28413 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
Unused Channels
If the application requires less than all amplifiers one channel,
the user must configure the unused channel(s) to prevent it from
oscillating. The unused channel(s) will oscillate if the input and
output pins are floating. This will result in higher than expected
supply currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is to short
the output to the inverting input and ground the positive input (as
shown in Figure 20).
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load, power supply conditions and
ambient temperature conditions. It is therefore important to
calculate the maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to remain in the
safe operating area. These parameters are related using
Equation 1:
where:
•P
DMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
•PD
MAX for each amplifier can be calculated using Equation 2:
where:
•T
MAX = Maximum ambient temperature
•θJA = Thermal resistance of the package
•PD
MAX = Maximum power dissipation of 1 amplifier
•V
S= Total supply voltage
•I
qMAX = Maximum quiescent supply current of 1 amplifier
•V
OUTMAX = Maximum output voltage swing of the application
•R
L= Load resistance
ISL28113, ISL28213 and ISL28413 SPICE
Model
Figure 21 shows the SPICE model schematic and Figure 22 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC
parameters are IOS, total supply current and output voltage swing.
The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 4. The AVOL is adjusted
for 85dB with the dominate pole at 100Hz. The CMRR is set 72dB,
f = 35kHz). The input stage models the actual device to present an
accurate AC representation. The model is configured for ambient
temperature of +25°C.
Figures 23 through 32 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Large Signal 5V Step Response, CMRR and Open Loop Gain
Phase.
FIGURE 19. INPUT ESD DIODE CURRENT LIMITING
-
+
RIN-
RL
VIN-
V+
V-
RIN+
RF
RG
FIGURE 20. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
TJMAX TMAX θJAxPDMAXTOTAL += (EQ. 1)
PDMAX VSIqMAX VS
(- VOUTMAX)VOUTMAX
RL
------------------------
×+×=(EQ. 2)

ISL28113, ISL28213, ISL28413
10 FN6728.5
June 9, 2011
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications, and the
Licensee may make copies of this macro-model for use within
their company only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.

ISL28113, ISL28213, ISL28413
11 FN6728.5
June 9, 2011
IOS
25E-12
EOS
VCM
+
-
+
-
G1A
G2A
1
1
14
RA1
RA2
4
5
V++
D1
DX
D2
DX
R10
1E9
100
R9
15
R6
V2
1E-6V
+
-
V1
1E-6V
+
-
R5
R7 R8
10
10
11
I2
5E-3
6
I1
5E-3
R2
R1
R3 R4
1.0004
10 10
Cin1
1.26pF
Cin2
1.26pF
CinDiff
1.02pF
R22
5E11
R23
5E11
+
-
+
-
En
VOUT
V+
V-
+
-
+
-
+
-
+
-
D3
DX
D4
DX
V3
0.61V
V4
0.61V
G1
G2
R11
1
R12
1
4
5
V++
16
18
17
+
-
+
-
+
-
+
-
D5
DX
D6
DX
V5
V6
0.604V
G3
G4
R13
R14
Vg
20
19
C2
5.0nF
C3
5.0nF
Vmid
Vmid
+
-
+
-
G5
G6
R15
1E6
R16
22
21
L1
4.5474
L2
4.5474
1E6
VCM
+
-
+
-
ISY
90uA
V++
V-
V+
+
-
+
-
G11
G12
R19
50
R20
26 27
50
V--
VCM
Vc
+
-
+
-
D11
DY D12
DY
D9
DX D10
DX
D7 DX
D8 DX
Vg
V++
V--
V--
+
-
+
-
V7
V8
0.08V
0.08V
Vg
+
-+
-
Vc
G10
G9
VOUT
24
25
1ST Gain Stage (Cont) Mid Supply Ref 2nd Gain Stage Common Mode Gain Stage
Supply Isolation Stage
E2
E3
Output Stage
C4
10pF
C3
10pF
R17
5305.32
R18
5305.32
23
+
-
G8
+
-
G7
Vmid
Vmid
0.604V
318.329E3
318.329E3
+
-
+
-
E4
Pole Stage
+
-+
-
Vin+
+
-
En
R21
800E3
V9
0.00035V
D13
DN
V--
V--
28
29
In+
1
2
34
5
Vmid
Vc
11 12
910
13
7
8
1.0004
M14 M15
M16 M17
1ST Gain Stage
Input Stage
Vin- Vmid
Vc
FIGURE 21. SPICE SCHEMATICFIGURE 21. SPICE SCHEMATIC
Voltage Noise Stage

ISL28113, ISL28213, ISL28413
12 FN6728.5
June 9, 2011
* source ISL28113_SPICEmodel
* Revision D, LaFontaine February 22, 2010 Improved noise
performance
* Model for Noise, supply currents, CMRR 72dB f=35kHz, AVOL
85dB f=100Hz
* SR = 1.0V/us, GBWP 2MHz, 2nd pole 3MHz Output voltage clamp
and short ckt I limit
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
* | -input
* | | +Vsupply
* | | | -Vsupply
* | | | | output
* | | | | |
.subckt ISL28113subckt Vin+ Vin- V+ V- VOUT
* source ISL28113_DS rev1
*
*Voltage Noise
E_En VIN+ EN 28 0 1
D_D13 29 28 DN
V_V9 29 0 0.45
R_R21 28 0 30
*
*Input Stage
M_M14 3 1 5 5 NCHANNELMOSFET
M_M15 4 VIN- 6 6 NCHANNELMOSFET
M_M16 11 VIN- 9 9 PMOSISIL
M_M17 12 1 10 10 PMOSISIL
I_I1 7 V-- DC 5e-3
I_I2 V++ 8 DC 5e-3
I_IOS VIN- 1 DC 25e-12
G_G1A V++ 14 4 3 1404
G_G2A V-- 14 11 12 1404
V_V1 V++ 2 1e-6
V_V2 13 V-- 1e-6
R_R1 3 2 1.0004
R_R2 4 2 1.0004
R_R3 5 7 10
R_R4 7 6 10
R_R5 9 8 10
R_R6 8 10 10
R_R7 13 11 1
R_R8 13 12 1
R_RA1 14 V++ 1
R_RA2 V-- 14 1
C_CinDif VIN- EN 1.02E-12
C_Cin1 V-- EN 1.26e-12
C_Cin2 V-- VIN- 1.26e-12
*
*1st Gain Stage
G_G1 V++ 16 15 VMID 334.753e-3
G_G2 V-- 16 15 VMID 334.753e-3
V_V3 17 16 .61
V_V4 16 18 .61
D_D1 15 VMID DX
D_D2 VMID 15 DX
D_D3 17 V++ DX
D_D4 V-- 18 DX
R_R9 15 14 100
R_R10 15 VMID 1e9
R_R11 16 V++ 1
R_R12 V-- 16 1
*
*2nd Gain Stage
G_G3 V++ VG 16 VMID 24.893e-3
G_G4 V-- VG 16 VMID 24.893e-3
V_V5 19 VG .604
V_V6 VG 20 .604
D_D5 19 V++ DX
D_D6 V-- 20 DX
R_R13 VG V++ 318.329e3
R_R14 V-- VG 318.329e3
C_C2 VG V++ 5E-09
C_C3 V-- VG 5E-09
*
*Mid supply Ref
E_E4 VMID V-- V++ V-- 0.5
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
I_ISY V+ V- DC 90e-6
*
*Common Mode Gain Stage with Zero
G_G5 V++ VC VCM VMID 0.25118
G_G6 V-- VC VCM VMID 0.25118
E_EOS 1 EN VC VMID 1
R_R15 VC 21 0.001
R_R16 22 VC 0.001
R_R22 EN VCM 5e11
R_R23 VCM VIN- 5e11
L_L1 21 V++ 4.547418E-09
L_L2 22 V-- 4.547418E-09
*
*Pole Stage
G_G7 V++ 23 VG VMID 0.18849
G_G8 V-- 23 VG VMID 0.18849
R_R17 23 V++ 5.30532
R_R18 V-- 23 5.30532
C_C4 23 V++ 1e-8
C_C5 V-- 23 1e-8
*
*Output Stage with Correction Current Sources
G_G9 26 V-- VOUT 23 0.02
G_G10 27 V-- 23 VOUT 0.02
G_G11 VOUT V++ V++ 23 0.02
G_G12 V-- VOUT 23 V-- 0.02
V_V7 24 VOUT .08
V_V8 VOUT 25 .08
D_D7 23 24 DX
D_D8 25 23 DX
D_D9 V++ 26 DX
D_D10 V++ 27 DX
D_D11 V-- 26 DY
D_D12 V-- 27 DY
R_R19 VOUT V++ 50
R_R20 V-- VOUT 50
.model pmosisil pmos (kp=16e-3 vto=-0.6)
.model NCHANNELMOSFET nmos (kp=3e-3 vto=0.6)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28113subckt
FIGURE 22. SPICE NET LIST

ISL28113, ISL28213, ISL28413
13 FN6728.5
June 9, 2011
Characterization vs Simulation Results
FIGURE 23. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 24. SIMULATED INPUT NOISE VOLTAGE
FIGURE 25. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY FIGURE 26. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 27. CHARACTERIZED LARGE SIGNAL TRANSIENT
RESPONSE vs RL, VS= ±0.9V, ±2.5V
FIGURE 28. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs
RL, VS = ±0.9V, ±2.5V
FREQUENCY (Hz)
10
100
1000
INPUT NOISE VOLTAGE (nV/√Hz)
1 10 100 1k 10k 100k
V+= ±2.5V
AV= 1
10,000
FREQUENCY (Hz)
1 10 100 1k 10k 100k
10
100
1000
10,000
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
GAIN (dB)
100k 1M 10M
10 10k
1k
100
70
-10
0
10
20
30
40
50
60
100M
V+= ±2.5V
VOUT = 50mVP-P
CL= 4pF
RL= 10k
AV= 1
AV= 100
AV= 1000
AV= 10
Rg= 100, Rf= 100k
Rg= 10k, Rf= 100k
Rg= 1k, Rf= 100k
Rg= OPEN, Rf= 0
GAIN (dB)
(A) AC sims.dat (active)
FREQUENCY (Hz)
10 100 1.0k 10k 100k 1.0M 10M 100M
0
20
40
60
-10
70
-3
-2
-1
0
1
2
3
02468101214161820
TIME (ms)
LARGE SIGNAL (V)
RL = 10k
AV= +1
CL= 15pF
VOUT = RAIL
VS= ±0.9V
VS= ±2.5V
(A) AC sims.dat (active)
TIME (µs)
051015202530
-3
-2
-1
-0
1
2
3
RL= 10k
AV= +10
CL= 15pF
VOUT = RAIL
VS= ±2.5V
VOUT
VIN
LARGE SIGNAL (V)

ISL28113, ISL28213, ISL28413
14 FN6728.5
June 9, 2011
FIGURE 29. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 30. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 31. SIMULATED (DESIGN) CMRR FIGURE 32. SIMULATED (SPICE) CMRR
Characterization vs Simulation Results (Continued)
-80
-60
-40
-20
0
20
40
60
80
100
120
0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
OPEN LOOP GAIN (dB)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
PHASE (°)
RL= 100k
SIMULATION
CL= 10pF
PHASE
GAIN
V+= ±2.5V
OPEN LOOP GAIN (dB)/PHASE (°)
(A) AC sims.dat (active)
FREQUENCY (Hz)
0.01 0.1 10 100 1.0k 10k 100k 1.0M 10M 100M
0
40
80
120
160
200
1.0
0
10
20
30
40
50
60
70
80
0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
CMRR (dB)
SIMULATION
CMRR (dB
)
(A) AC sims.dat (active)
FREQUENCY (Hz)
0.01 0.1 1.0 1.0k 10k 100k 10M
0
20
40
60
80
100 1.0M 100M10

ISL28113, ISL28213, ISL28413
15 FN6728.5
June 9, 2011
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you
have the latest Rev.
DATE REVISION CHANGE
5/18/11 FN6728.5 - On page 2, Ordering Information table: ISL28113FHZ-T7 & -T7A PKG DWG # changed from MDP0038 (Obsoleted) to
P5.064A. Removed ISL28213FHZ and added “Coming Soon” to parts ISL28213FHZ-T7A and ISL28413TSSOPEVAL1Z.
- On page 3, Pin Descriptions: Circuit 3 diagram, removed anti-parallel diodes from the IN+ to IN- terminals.
- On page 4, Absolute Maximum Ratings: changed Differential Input Voltage from "0.5V" to "V-- 0.5V to V++ 0.5V".
- On page 4, updated CMRR and PSRR parameters in Electrical Specifications table with test condition specifiying -40°C
to 125°C typical parameter.
- On page 5, updated Note 6 (“over-temp” note) referenced in MIN and MAX column headings of Electrical Specifications
table from "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested." to new standard "Compliance to datasheet limits is
assured by one or more methods: production test, characterization and/or design."
- On page 9, under “Input ESD Diode Protection,” removed “They also contain back to-back diodes across the input
terminals.” Changed “For applications where the input differential voltage is expected to exceed 0.5V, an external series
resistor...” to “For applications where the input differential voltage may exceed either power supply voltage by 0.5V or
more, an external series resistor...”. Removed “Although the amplifier is fully protected, high input slew rates that exceed
the amplifier slew rate (±1V/µs) may cause output distortion.”
- On page 9, Figure 19: updated circuit schematic by removing back-to-back input protection diodes.
- On page 18, replaced Package Outline Drawing MDP0038 (obsolete) with P5.064A.
3/23/10 FN6728.4 Page 1, 2nd paragraph - Added “...SOT23-8 packages...” and changed “SO8” to “SOIC8”.
Also global, changed S08 to SOIC8
Pg 2, Ordering Information table: Part # ISL28213FEZ changed to ISL28213FHZ and Part Marking changed to "TBD"
-Added Related Literature on page 1, updated ordering information by adding Eval boards.
-Added to ordering information part number ISL28213FHZ 8 Ld SOT-23 Package as coming soon.
-Replaced Figure 24 Simulated Input Noise Voltage with following changes:
Y-axis from “10 to 100” to “10,000 to 10”
Removed (A) AC sims.dat (active) from top of graph
Curve changed to improve noise performance
Made changes to Spice Net List as follows:
-Changed Revision from “C” to “D” and added improved noise performance to Revision line.
-Changed in Voltage Noise
“V_V9 29 0 .00035” to “V_V9 29 0 0.45”
“R_R21 28 0 800E3 TC=0,0” to “R_R21 28 0 30”
-Removed TC=0 in Input Stage from R_R1 through C_Cin2
-Removed TC=0 in 1st Gain Stage from R_R9 through R_R12
-Removed TC=0 in 2nd Gain Stage from R_R13 through C_C3
-Changed in Common Mode Gain Stage with Zero
“G_G5 V++ VC VCM VMID 2.5118E-10” to “G_G5 V++ VC VCM VMID 0.25118”
“G_G6 V-- VC VCM VMID 2.5118E-10” to “G_G6 V-- VC VCM VMID 0.25118”
Removed TC=0 from R_R16 through R_R23
-Changed in Pole Stage
“G_G7 V++ 23 VG VMID 188.49e-6” to ‘G_G7 V++ 23 VG VMID 0.18849”
“G_G8 V-- 23 VG VMID 188.49e-6” to “G_G8 V-- 23 VG VMID 0.18849”
Removed TC=0 from R_R17 through C_C5
Removed TC=0 in Output Stage with Correction Current Sources from R_R19 and R_R20
Made changes to Spice Schematic Figure 21 as follows:
-Input Stage - Modified connection to the EOS (voltage control voltage source)
-Added to Thermal Information 8 LD SOT-23 as TBD
-Added to pin configuration for the ISL28213 8 Ld SOT-23
12/16/09 FN6728.3 Removed “Coming Soon” from MSOP package options in the “Ordering Information” on page 2.
Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W on page 4.
11/17/09 FN6728.2 Removed “Coming Soon” from SC70 and SOT-23 package options in the “Ordering Information” on page 2.
11/12/09 FN6728.1 Changed theta Ja to 250 from 300. Added license statement (page 10) and reference in spice model (page 12).
10/26/09 FN6728.0 Initial Release

ISL28113, ISL28213, ISL28413
16
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6728.5
June 9, 2011
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL28113, ISL28213, ISL28413
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php

ISL28113, ISL28213, ISL28413
17 FN6728.5
June 9, 2011
Small Outline Transistor Plastic Packages (SC70-5)
D
e1
E
E1
C
L
C
C
L
eb
C
L
A2
AA1
C
L
0.20 (0.008) M
0.10 (0.004) C
C
-C-
SEATING
PLANE
45
123
VIEW C
VIEW C
L
R1
R
4X θ1
4X θ1
GAUGE PLANE
L1
SEATING
αL2
C
PLANE
c
BASE METAL
WITH
c1
b1
PLATING
b
0.4mm
0.75mm
0.65mm
2.1mm
TYPICAL RECOMMENDED LAND PATTERN
P5.049
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.031 0.043 0.80 1.10 -
A1 0.000 0.004 0.00 0.10 -
A2 0.031 0.039 0.80 1.00 -
b 0.006 0.012 0.15 0.30 -
b1 0.006 0.010 0.15 0.25
c 0.003 0.009 0.08 0.22 6
c1 0.003 0.009 0.08 0.20 6
D 0.073 0.085 1.85 2.15 3
E 0.071 0.094 1.80 2.40 -
E1 0.045 0.053 1.15 1.35 3
e 0.0256 Ref 0.65 Ref -
e1 0.0512 Ref 1.30 Ref -
L 0.010 0.018 0.26 0.46 4
L1 0.017 Ref. 0.420 Ref. -
L2 0.006 BSC 0.15 BSC
α0o8o0o8o-
N5 55
R 0.004 - 0.10 -
R1 0.004 0.010 0.15 0.25
Rev. 3 7/07
NOTES:
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.

ISL28113, ISL28213, ISL28413
18 FN6728.5
June 9, 2011
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
Dimension is exclusive of mold flash, protrusions or gate burrs.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
Foot length is measured at reference to guage plane.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
INDEX AREA
PIN 1
SEATING PLANE
GAUGE
0.45±0.1
(2 PLCS)
10° TYP
4
1.90
0.40 ±0.05
2.90
0.95
1.60
2.80
0.05-0.15
1.14 ±0.15
0.20 CA-B DM
(1.20)
(0.60)
(0.95)
(2.40)
0.10 C
0.08-0.20
SEE DETAIL X
1.45 MAX
(0.60)
0-3°
C
B
A
D
3
3
3
0.20 C
(1.90)
2x
0.15 C
2x
D
0.15 C
2x
A-B
(0.25)
H
5
2
4
5
5
END VIEW
PLANE

ISL28113, ISL28213, ISL28413
19 FN6728.5
June 9, 2011
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions “D” and “E1” are measured at Datum Plane “H”.
This replaces existing drawing # MDP0043 MSOP 8L.
Plastic interlead protrusions of 0.25mm max per side are not
Dimensioning and tolerancing conform to JEDEC MO-187-AA
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW 1
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW 2
included.
included.
GAUGE
PLANE
3°±3°
0.25 C A B
B
0.10 C
0.08 C A B
A
0.25
0.55 ± 0.15
0.95 BSC
0.18 ± 0.05
1.10 Max
C
H
4.40
3.00
5.80
0.65
3.0±0.1 4.9±0.15
1.40
0.40
0.65 BSC
PIN# 1 ID
DETAIL "X"
0.33 +0.07/ -0.08 0.10 ± 0.05
3.0±0.1
12
8
0.86±0.09
SEATING PLANE
and AMSE Y14.5m-1994.

ISL28113, ISL28213, ISL28413
20 FN6728.5
June 9, 2011
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”