
CIRCUIT DESCRIPTION MODEL445
2.
The Delay Hold circuit gates the output of
the Oscillator depending on the state of the "RS
flip-flop" and elle "Hold 1" control line. A uni-
junction timing circuit provides a delay period
before a conversion is initiated. The time delay
is selected by the front panel DISPLAY RATEControl.
3. The BCDcounter serves as a master timing
control for the A/D conversion cycle. The timing
is accomplished by the "1000" co"neer which has
five
coded
states, namely 0, 1, 2, 3,
and
4.
4:
The
Program/Decoder controls the sequence Of
commandsbased an the coded etatee from the BCD
counter. The decoded commandsare described as
shown in Table 3-2.
the "2"
commandinitiates the
integrator ZEROperiod which removes any residual
charge on the integrator capacitor. The "3,4" CO",-
mand initiates the
INTEGRATE
period which permits
an integration of the analog signal. At the end of
the INTEGRATEperiod, the "0,l" commandinitiates
the COUNTperiod.
TABLE 3-2.
Command F""ction
2
ZERO
3,4 INTEGRATE
031 COUNT
5.
When the "3,4" commandis given, the integra-
tor is charged by the analog signal for B period of
1 line cycle of 16.67 milliseconds.
6,
When the "O,l" commandis given, the analog
signal is removed and the integrator output is driv-
en to zero by a reference current. The Zero Cross-
ing detector senses a zero crossing of the Ineegra-
tar output and removes the reference cuxene. The
Detector provides outputs as shown in Table 3-1. The
+1.5 volt levels are provided for control of the
Integrator and Polarity Storage Register. A pulse
commandis also produced to initiate a Buffer/Store
and Print Commando"tp"t.
7. When the Buffer/Store commandis given, the
Buffer/Storage Register copies the BCDCOUnterStateS
at that instant of time. The BCDcoded information
in the RegFster is then available for the Decoder/
Driver and external printout.
8.
The
Decoder/Driver decodes then Buffer/Storage
output and drives the'Numerica1 Readout for a digit-
al display.
9. The RCDOutput information is available at the
Model 4401 Buffer Card o"tp"ts in the form of posi-
tive (+lO volt) tr"e logic (l-2-4-6 BCDCode).
10. The conversion cycle is completed when the BCD
Counter reaches 2000 co"nt~ and the Program/Decoder
provides a "2" commandto initiate a new con"ersFon
cycle.
11. The Unijunction Timing Circ"it will initiate
the ZEROperiod after a present time delay controlled
by the front panel DISPLAY
RATE
Control.
3-5.
ANALOG-TO-DIGITALCONVERTERCIRCUITRY.
a. General. The circuits described in this aectio
are located on the various Sub-Assemblies listed beloh
and in Table 7-2 of Section 7.
1. Oscillator Board, K-217.
2. Integrator Board, K-219.
3. Display/Overload Board, X-241.
4.
Readout Board, PC-229.
5.
Polarity Board, K-207.
6.
Output Buffer Board, X-218.
7. Output Buffer Board, X-209.
b. Oscillator Board. The Oscillator Board contains
portions of three circuits: the Oscillator (clock)
circuit, the Delay/Hold circuit, and the Discharge-
Voltage CUrrent source circuit.
1. Oscillator Circ"if. Transistor Q501, crystal
Y501, and phase shift capacitors C501, and C502 farm
a "Colpitts"
type oscillator. Capacitors C503
and
C504
are used for trimming the oscillator frequency.
The output is taken from the collector of transistor
Q510 which is a commonemitter gain stage'used for
squarLng the output. Transistor
Q507 serves as an
emitter-follower to reduce output impedance.
2. Delay/Hold Circuit. There are three major
components in ehe Delay/Hold circuit: an "RS" type
flip-flop circuit, a "Unijunction" timing circuit
and a "Hold" gate circuit.
a). "RS" Type Flip-Flop Circuit. The flip-flop
gafes ehe output of the clock depending an the
input8 Bt pins R and S. The RS flip-flop is con-
structed of gates QA5OlB and QASOlC. The pins
are identified as shown in Figure 16.
b). "Unijunction " Timing Circuit. The "nijunc-
tion timing circuit determines the time delay be-
tween conversion cycles to obtain the desired con-
version rate as determined by the front panel DIS-
PLAY RATEControl. The circuit is composed of
transistors Q513 and 0514, timing capacitor C507,
and timing resistors R532 and R1269 (DISPLAY RATE
Control potentiometer located on the front panel.
C).
"HOLD" Gate Circuit
. (Refer to Figure 16
for identification of switches Sl and S2). The
"HOLD" gate circuit is composed of gates QA501A,
QASOlD, and QA502 (A, B, C, and D). Switch Sl is
gate QA501Aand is controlled by eirher~the "HOLD
2"
external line or the "MAX" position on the DIS-
PLAYRATEControl. Switch S2 is transistor Q513
which is controlled by either the "Q" output of
the flip-flop or the "HOLD2" external line. The
"HOLD
1" circuit is composed of gates
QA502B
and
QA502C.
3. Discharge-Voltage Current Source Circuit.
The positive current source composed of transiseors
Q502 and Q506 delivers a constant current of ~7.5
milliamperes to drive a 9-volt zener diode D602
(located on the Integrator Board, W-246) "hen +REF
Terminal (Pin 13) is greater than +0.7 volt. The
negative current source composed of transistors
QSOSand Q509 delivers a constant current of -7.5
milliamperes to drive a g-volt zener diode ~601
(also located on the Integrator Board, X-219).
16 0971