Kenwood TM-2550A User manual

KENWOOD
MU-1,
MB-10,TU-7,
PG-2K,VS-1
M-2000A/E,TM-2530A
144Miiz FM TRANSCEIVER
Photo is TM-2550A.
CONTENTS
CIRCUIT
DESCRIPTION
.........
0.0000
ce
ae
2
TERMINAL
FUNCTIONS
.................0.
37
PARTS
LIST...
0...
0.
cc
eee
16
BLOCK
DIAGRAM
(TM-2550A,
TM-2530A)
......
38
DISASSEMBLY
........
2...
0.0
c
cee
eee
uaae
30
SCHEMATIC
DIAGRAM
(TM-2550A,
TM-2530A)
..
39
ADJUSTMENT
1.0.0.0...
0.
cee
ee
32
SCHEMATIC
DIAGRAM
(TM-2550E)
...........
40
PC
BOARD
VIEWS
BLOCK
DIAGRAM
(TM-2550E)...............
41
MIC
AMP.
(X59-1000-10)
...
2...
....
00008
36
LEVEL
DIAGRAM
......
0.0.0...
cc
eee
eee
42
MIC
AMP.,S-METER
(X59-1010-10)
2.2.2.0...
36
MU-1
(MODEM
UNIT)
..............200000-
42
ALERT,
VACANT
CH.
(X59-1020-10)
..
2.2...
36
MB-10
(MOBILE
MOUNT)
..................
43
CENTER
DETECTOR
(X59-1030-10)
...
2.2...
36
TU-7
(TONE
UNIT)
..
2.2...
eee
44
SQUELCH
CONTROL
({X59-1040-10)
..
0.2.00.
36
PG-2K
(DC
POWER
CABLE)
.................
45
COMPOUND
UNIT
(X60-1280-XX)
.
2.0.0.0.
36
VS-1
(VOICE
SYNTHESIZER)..............-.
46
CONTROL
UNIT
(X53-1440-XX).....0.0..00.
36
PACKING
(TM-2550A/E,
TM-2530A)
...........
47
PLL
UNIT
(X50-2030-XX)
..
2
eee
ee
eee
36
SPECIFICATIONS
................
BACK
COVER
DISPLAY UNIT (X54-1860-10) 2... ...2.000, 37
FINAL UNIT (X45-1440-XX) 22... 2.000000. 37

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
TM-2550A (K1,M1,M3)
TM-2550E (T,W) TM-2530A (K2,M2,M4)
FINAL UNIT X45- 1440-10
X45- 1440-10 X45- 1440-11
PLL UNIT X50-2030-10
X50- 2030-51 X50-2030-11
X53-1440-10 (K1,M1)
CONTROL UNIT
X53-1440-21 (M3)
X53- 1440-51 (T)
X53- 1440-61 (W)
X53- 1440-10 (K2,M2)
X53- 1440-21 (M4)
DISPLAY UNIT X54-1860-10
X54- 1860-10 X54-1860-10
COMPOUND UNIT
X60- 1280-10
X60- 1280-51 X60- 1280-10
Table 1 TM-2550A/E, TM-2530A PC board chart
RX SECTION
Signals from the antenna are applied to the FINAL unit
(X60-1280-XX) transmit receive swithing circuit, D2 and
D4. In receive, diodes D2 and D4 are reverse biased forcing
the incoming receive signal down thru L3 to the RA (Re-
ceive Antenna) terminal. There the incoming receive signal
is then coupled to the COMPOUND Unit {X60-1280-XX).
The signal is filtered by a low pass filter and amplified by
Q1 the first RF amplifier, a GaAs FET : 3SK129(S). The
amplified RF signal is then mixed with the LR (Receiver
Local Oscillator) signal in the first mixer Q2 : 3SK74(L) to
obtain the First iF frequency of 10.695MHz. This IF signal
is filtered by Helical Resonator, L4, and a two stage MCF
(Monolithic Crystal Filter), L8, which combine to provide
excellent two-signal characteristics and sensitivity.
The First IF signal from the MCF is then amplified by the
First 1F amplifier Q3 : 2SC2668(Y} and applied to the FM
iF Amplitier/Mixer/Detector, (C2 : TA7761P. This signal
IC mixes the IF signal with the 10.24MHz 2nd Locai Oscil-
lator signal (L14} to obtain the 2nd IF frequency of
455kHz, then amplifies, routes the signal thru external
filter L16, and finally convertes it into the received audio
signal with the internal quadrature detector. The 2nd Local
Oscillator signal from L14 and IC2 is also used by the PLL
unit as a Reference signal.
The detected audio output from |C2 is applied to the
SQUELCH CONTROL (X59-1040-10), and to the de-
emphasis circuit R56 and C99. The (de-emphasized) audio
is amplified by Audio preamplifier Q9 : 2SC2458(Y) and
then applied thru the AF GAIN contro! to the Audio Amp-
lifier [C1 ; ¢PC1241H which drives the speaker.
The noise component of the detected audio is filtered by a
band-pass filter, in order to obtain a frequency of appro-
ximately 30kHz (which is well outside the normal voice
bandwidth) and then amplified by the noise amplifiers
contained inside 1C2. This amplified noise is rectified by
diodes D6 and D5 and applied to O1 of the Squeich Switch.
Q1 is used to control the conduction of O2, which controls
AF Preamp Q9.
A center-stop tuning circuit is provided to ensure that the
incoming signal is actually on frequency before the squelch
is opened. A portion of the 455kHz IF signal is coupled
thru the secondary of L17 and applied to CENTER STOP
unit (X59-1030-10) where Ceramic Discriminator L12, and
Window comparator IC1 : NJM4558M are used to deter-
mine if the incoming signal is actually the channel center.
When the detected signal applied to the window compara-
tor reaches a predetermined level, Q5 of the Squeich Switch
will be turned OFF or ON. The Squeich Switch determines
if there is an incoming signal at the same time. If the in-
coming signal is at the proper level, and on frequency, the
squelch will open and the C.TUNE indicator in the LCD
display will turn ON. This indicator is controlled by IC2,
the main microprocessor on ithe CONTROL unit
(X53-1440-XX), thru inputs supplied from the COM-
POUND unit via the BD line. During Open Channel Scan-
ning of the DCL system Q3, Q1, and Q2 of the Squelch
Switch are controlled by the main microprocessor via the
SOS line. During DCL operations open channel search thre-
shold levels are controlled by VR3 of the Compound ass’y.
Transistor O6 of the Squelch Switch, is used to prevent the
Center Stop circuit from activating during Open Channel
Scan Operation.
Note 1:
The Center Stop circuit is not activated during Open Chan-
nel Scan.
Vv
Window comparator frequency
bandwidth.
o— = f
Pw
Frewuency
of
desired
Open
Channel
Channels
Interference such as IMDfrom strong adjacent channels
makes the use of the Center Stop function erratic during
Open channel scan.
Fig. 1
Audio Preamplifier Q9 is controlled by Q1 of the Alert,
Vacant CH. unit (X59-1020-10) during Alert, code Squelch
and Open Channel operations.

Li2 CFY455S
CIRCUIT DESECRIPTION
TM-2550A/E,2530A
Input/Output characteristics Principle of operation of window comparator
of L12.
8R CENTER DATECTOR
9 (X59-1030-10) +e
eo
Et: 4.1V—0 (4.06V) |
“ 1 6 se
i - 7 1 ,
Rt 1 ae et
Ct 5 101 (2/2) Et E2 et &1 £2
y OR? ei=4.1Vi0e 1C1(2/2)
q Wr
C4 01
Qi b> ]}~ C4172) oe beg
4iv_ 23 2
g = | J. E2
3 -e
q 3 @ : Set voltage at time when .
82V Ns detuning from 3kHz. .
[
ST
(About
0.04V)
Ei
e2
et
—_
10 ; 4
ry = a¢ Center detection
od Set to “H” when signals received from |
outside is within about + 3kHz. BD : Center stop signal
Set to “L" when in SOL OPEN mode at center.
z
[CONT-14
-
BD]
e
8R n
L +4 SOL CONTROL
3
9
{(X89-
1040-10)
§ at | cunemmens a
Q6 tusned on when in SQL. OPEN 4 turned on when
mode while searching vacant channels. in SQL OPEN mode
Lis = R1 R5 at center.
a
NOISE
FILTER ‘|
as a
7 | D5 10 RG 1 Q3 turned on
NOISE when in SQL :
P FM DET 5 turned on when signal
| iF AM KY AMP. H + Set to “H" when in OPEN mode. received from outside is
© ° SQL OPEN mode. at center.
Le ———- a 5 ” Set to about OV when in
: Ic. SQL CLOSE or TX mode.
[ ” . omeatiien.® - ;
I NOISE DET.
| awit th. Q39 is cut off for muting when in SQL
| 6 x CLOSE, TX, or ALERT mode. 1
| ° ox
| , ” o | C103 «C104 At 1 A se
F PA
| c100 3 + im
“
‘ 7
| AF VR
10
—
a1
Q2 turned on when searching Q1 is turned on and O9
vacant channels to change is cut off for muting when °
Q3 Q2| >” from SQL to VR3. in TX or ALERT mode. Set to “L" normally.
mode. Set to “H’ when searching
vacant channels in DCL
04 RS OPERATION mode.
> a Jz |
Q3 turned off when RT 2 T Sas
searching vacant —ed
channels. ZL °
7 7
ALERT, VACANT CH. (X§9- 1020-10) |
Fig. 2 Center datector, Alert, Vacant CH, SQL control circuit

TM-2550A/E,2930A
CIRCUIT DESECRIPTION
Item Rating
Item Rating
Nominal center frequency (fo) | 10.695MHz
Nominal center frequency (fo) | 455kHz
Pass bandwidth +7.5kHz or more at 3dB 6dB
bandwidth +6kHz or more
+25kHz or less at 40dB
£45k Hz or less at 6OdB
Attenuation bandwidth
1. 70dB or more within +1MHz
2. Spurious jevel = 40dB or more
at fo—fo + 500kHz
3. Spurious level = 80dB or more
at fo—(910kHz+10kHz)
Guraranteed attenuation
Ripple 1.0dB or less
Loss 1.5dB or less
Impedance 3kQ/0pF
Table 2 MCF (L71-0216-05) COMP unit L8
+12.5kHz or more
3dB or less
6dB or less
35dB or more
50dB bandwidth
Ripple (within 455+5kHz)
Loss
Guaranteed attenuation
(within 455+100kHz)
Input and output impedance
2.0k2
Table 3. Ceramic filter (L72-0315-05) COMP unit L16
® @®
t ! Qio r if ®
Qis6
0 2 Ris
«
o ° R13 :
a i 2 + 7
aia Qi? Qi8 ©
N
Q3 Py
rs ae
a
OVER
az
ais
VOLTAGE x4
N t & 4
ant ° SURGE pia | 01S pte ©
PROTECTION 4
Q5 a7 o 38
Sr m
at =
a2 a4 RG c1 5% Jats
W-o 1 ¢
wo
° , ' | a
Qi2 ‘
Q6 Qs S aii o20 +5)
t 13 THERMAL. SHORT
rd SHUT ciRCcUIT
oye DOWN PROTECTION ~
210 2 z= Ome ne wo =3
Sa Se Se ¢£ abr te z> x «
lL“) ¥28
Fig.3 PC1241H Equivalent circuit (COMP unit 1C1)
TX SECTION
Incoming microphone audio from the DISPLAY unit
(X54-1860-10 C/3) is amplified by Q8 : 2SC1775(E). This
amplified audio is then buffered by buffer amplifier Q7 :
2SC2458(Y) and applied to D2 : 188181 of the MIC
AMP/S METER unit (X59-1010-10) for limiting. The signal
is then amplified by a portion of 1C1 : NJM4558M on the
MiC AMP/S METER unit. D2 of the MIC AMP unit
(X59-1000-10) provides additional limiting. The micro-
phone audio is filtered by a 2 stage active LPF, IC1 :
NJM4558M and applied to varactor diode D3 : 1$2208 in
the PLL unit (X50-2030-XX) for phase modulation of the
transmit VCO, 08.
The phase-modulated FM signal is amplified by driver tran-
sistors Q10 : 2SC2688(Y), Q11 : 28C2347 and Q12 :
2SC2538-22-A (TM-2530) or 2SC3019 (TM-2550) and
applied to the FINAL unit (X45-1440-10 : TM-2550A/E or
4 X45-1440-11 : TM-2530A).
This signal is amplified by the Hybrid Final Amplifier
Module Q1 M57737 (TM-2530A) or M57726 (TM-
2550A/E) and applied to the antenna via the transmit/
receive switching diode D2. During transmit, forward bias is
applied to D2 allowing the transmit signal to pass. Diode
D3 is also forward biased during transmit. The value of L3
was selected to present a high impedance to the transmitted
signal. Any of the transmit signal that passes thru L3 is
shunted to ground thru D3 to protect the receiver circuits
and prevent feedback. Once the signal has been passed thru
D2 it proceedes thru the LPF and to the antenna.
The APC (Automatic Protection Circuit) on the FINAL
unit consists of two circuit, a negative feedback circuit that
senses output power and an SWR protection circuit.

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
The
negative
feedback
circuit
samples
the
transmitted
signal,
rectifies
this
signal
with
D4,
and
applies
the
rectified
signal
to
NF
GAIN
amplifier
Q6
:
2SC2458(Y).
This
amp-
lifier
supplies
a
signal
to
Differential
Amplifiers
Q4
and
Q5
:
2SC2458(Y)
which
control
the
bias
applied
to
the
PA
module
pin
2,
and
driver
transistor
Q12
of
the
PLL
unit,
via
bias
regulators
Q2
:
2SD1406(Y)
and
O3
:
2SA1015(Y).
|
|
if
High/Low power swithing is accomplished by applying a
ground
to
pin
number
1
of
connector
(2)
on
the
FINAL
unit.
This
causes
VR3
to
act
as
a
voltage
divider
that
cont-
rols
the
condution
of
NF
GAIN
amplifier
Q6.
L
Reflected
power
is
coupled
thru
D5
on
the
FINAL
unit
and
is
used
to
control
the
conduction
of
Q7.
This
transistor
function
like
Q6
to
control
differential
amplifers
Q4
and
O5,
and
thus
the
bias
applied
to
the
Power
Amplifier.
Item Symbol | Tc(°C) Condition Rating
Operating Vee 25 17V
DC
current
Iec
25
7A
Operating
case
temp.
|
Tc
(op)
—30~
+
110°C
Storage
temp.
Tstg
—40~
+
110°C
Power input Pin 25 Zg = Zi = 502 0.4W
Power output Po 25 Zg = ZI = 502 40W
Table
4
M57737
Max.
rating
(TM-2530A
Final
unit
01)
lik
Lo Le
@IinPpuT @Vcci @Vcc2 @MouT @Gnod
Fig.4 M57737 Equivalent circuit
Item Symbol | Te (°C) Rating
Operating voltage Vee 25 17V.
DC current icc 25 14A
Operating case temp. | Tc (op) —30~ + 110°C
Storage temp. Tstg —40~ + 110°C
Table5 M57726 Max. rating (TM-2550A/E Final unit Q1)
Value
Item Symbol | Tc (°C) Condition
Min.
Typ.
Vcc = 12.5V.
F = 144~148MHz,
PIN =O0.4W,
ZL = ZG = 502
Power output Po 25 43W
47W
Vee = 12.5V,
F = 144~148MHz,
PIN = 0.4W,
ZL = ZG = 502
Total efficiency nT 25 50%
54%
Table 6 ™M57726 Electrical characteristic
H
1,
@in @vcci1 @Vcc2 Mout Ono
Fig.5 M57726 Equivalent circuit
PLL CIRCUIT
The PLL circuit is divided into two main loops : transmit
and receive.
Receive PLL Loop
The signal generated by the RX VCO (Voltage Controlled
Oscillator) Qi6 : 2SK192A(GR)*P is applied to buffer
amplifier Q17 : 2SC2668(Y) and mixed with the HET
(Heterodyne) signal by Q21 : 2SC2668(Y) where it be-
comes the PLL IF signal (K,M 13.015 to 15.010MHz, T,W
12.865 to 19.86MHz). This PLL IF signal is then amplified
by 020 : 2SC2668(Y} and applied to the Phase Detector
{C2 : MC145155P*K where it is divided to obtain a 5kHz
signal. The divide ratio is determined by Serial Data from
the CONTROL unit. This 5kHz signal is compared with the
5kHz reference signal obtained by dividing the 10.240 MHz
Reference signal.
The Phase Detector compares the phase of these two signals
and transmits an error control signal to the VCO. The cont-
rol signal is filtered by an Active Low Pass filter composed
of 013 : 2SK30A(O) and Q14: 2SC2458(Y) to remove
any AC fluctuations to obtain a DC correction voltage. The
correction voltage is used to change the capacitance of
Varactor Diode D5 : 1SV50, which varies the output of the
RX VCO to lock it on frequency.
If the phase difference is too great to be corrected by the
control voltage applied to D5, an unlock signal is generated
by the Phase Detector. This signal turns OFF Q15 :
2SC2458(Y) which turns OFF output amplifier O18 :
2SC2668(Y) to prevent operation outside the authorized
limits.
The PLL HET Oscillator, Q19 : 2SC2668(Y) oscillates at
39.48MHz. This signal is applied to frequency tripler Q22 :
2SC2688(Y) to obtain a signal of 118.44MHz which is
applied to mixer Q21.

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
Transmit PLL Loop
The
signal
generated
by
the
TX
VCO
O8
:
2SK125
(KM
142.00
to
148.995MHz,
T,W.
144.00
to
145.995MHz}
is
mixed
with
the
RX
PLL
output,
by
Q7
:
2SC2688(Y)
and
applied
to
the
Transmit
Phase
Detector
IC1
:
MC145151P.
This
signal
and
the
10.240MHz
signal
from
IC2
are
divided
by
512,
to
obtain
20kHz.
These
two
signals
are
compared
and
an
error
correction
signal
is
applied
to
the
Active
Low
Pass
filter
Q3,
Q4
and
O5
:
2SC1775(E).
Comparision
at
a
frequency
of
20kHz
provides
shorter
response
times,
a
real
necessity
in
transmit.
The
DC
correction
voltage
from
the
LPF
is
used
to
contro!
varactor
diode
D2
:
1SV50.
The divide ratio is increased by 91 during transmit opera-
tions. This causes the TX VCO frequency to be locked at a
frequency 455kHz higher than the RX VCO frequency
which prevents internal mixing. When an error occurs that
is greater than the correction voltage limits an unlock signal
is generated by !C1. This signal controls the conduction of
Q1 : 2SC2458(Y) which controls Q2 : 2SA1048(Y) to stop
transmissions. Q2 interrupts the bias of the TX driver
stage..
vppo2—>
RA2O7—*
cE
LOCK
8
VssC
7
RAI
Org
12
x
8
ROM
REFERENCE
DECODER
DETECT
-—C)
LD
OSC
OUT
|
Ledbetter
ey
1
OSC
IN
7
2b}
+2
bs
12-BIT
+
R
COUNTER
ER
PHASE
6
¢y_
|
DETECTOR
F-O
PD
OUT
A
t
4
REF
OUT
PHASE
L—OoR
DETECTOR
|
3
9
B
r—O
oV
FIN
14-BIT
+
N
COUNTER
o_o
voo—w—
-ttttitifittiit
P
ENABLEO
LATCH
>|
LATCH
f—OswW!
4
TEEFEEEtETTTT
tf
DATAO—
>
J
>.
Cc
14-BIT
SHIFT
REGISTER
7a
ER.
crock
ol?
Fig.6
MC145155P«K
Block
diagram
(PLL
unit
IC2)
rao
Oe
12
x8
ROM
REFERENCE
DECODER
Lock
128,15
OSC
OUT
RAO
02>
DETECT
teed
di
ty
osc
Ino=
=2
bs]
12-BIT
+R
COUNTER
PHASE
4
Vss
oO
DETECTOR
-—©
PD
OUT
Vppot>
{
9
FINO!
os
14-BIT
+
N
COUNTER
DE
eOTOR
fe
B
FEEEEEPT
PTI
10
TRANSMIT
94
—OfV
RECEIVE
O
TRANSMIT
OFFSET
ADDER
EEEEEEDEERNEAR
N13 -° N11
N44 N2
Fig. 7 MC145151P Block diagram (PLL unit IC1)

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
— —
118.44MHz —-39.48MHz
—— a21: a22 : aig:
Tic2: mc145156P+K 2Sc2668(Y) 2SC2668(Y) 28C2668(Y) 142,0~148.995MHz (K,M)
l 144.0~145.995MHz (T,W)
| j 131.308~138.300MHz (K,M)
l 133.305~135.300MHz (T,W}
5kHz ,
| P.D LPF }- reo {MIX
1/2048} l
| | O13: 28K30A(0) a6:
_y ata: 2802458(Y) 2SK192A(GR}+P
N : 2573~3972 (RX) (K,M)
2664~4063 (TX) (KM) | | 135 969~138.755MHz (K,M)
2973~3360 (RX) (TW) | | 1 33'769~135.755MHz (TW)
3064~3451 (TX) (T,W) : 10,695MHz
10.24MHz
TMP47C46N-9042
(
: 142.0~148.995MHz (K,M)
10.24MHz
ors
144,0~145.995MHz
(T,W)
|
|
Q7 : 28C2668(Y)
|
|
- TX
20kHz
| Q3~5: Qs :
28C1775(E) 2SK125
PLL UNIT
=
el
Fig.8 Frequency-related block diagram
(7.2V) (7.6V) (8.3V)
(*8.3V) (*8.35V) (*OV)
*: UNLOCK
To
RF
AMP
(Q10—12)
To
COMP
unit
(0.9V)
ist
MIX
FET
Q2
(*0V) (8.4V)
(*8.4V)
Z 8T
(7.2V)
(*0V)
NORMAL
UNLOCK
»:
UNLOCK
4.5V 4V
28
‘-
a
7
58V
ic1
15V
*1.3V
a]
NORMAL
UNLOCK
1
4
ov
ov-
:
8 6
+f
0.2ms
+f
0.3ms
50us 100us 4Vv
——|
a
>
1c2
v
|
|
I
|
7 2v 2V
W—Wwa—| ACTIVE
FILTER
™
TX
VCO
|
|
10.24MHz
ov
ov
From 1C2 (10.24MHz)
TX
section
RX
section
Fig.9
Unlock
circuit

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
CONTROL
UNIT
(X53-1440-XX)
The
CONTROL
unit
uses
two
Microprocessors.
the
Main
Microprocessor
1C2
:
TMP47C46N-9042
and
Auxilliary
Microprocessor
[C3
:
uPD75008HC-056.
Both
utilize
4
bit
architecture
and
have
4K
Bytes
of
ROM
available.
The
Main
Microprocessor
controls;
frequency,
offset,
tone,
memory
frequency,
key,
switch,
encoder,
frequency
dis-
play,
DCL
system
and
the
Auxillary
Microprocessor.
The
Auxilliary
Microprocessor
controls;
the
voice
synthesizer,
display/contrl/and
memory
for
telephone
number
func-
tions,
tone
frequencies
(K,M),
audio
oscillator,
and
digital
signal
conversion
and
analysis
processing
for
DCL
system.
The
Main
Microprocessor
utilizes
a
serial
interface
bus
to
the
Auxilliary
processor.
A
CMOS
static
RAM,
IC6
:
TC5047AP-1
with
a
capacity
of
1K
x
4
bits,
is
used
for
external
memory
storage
of
operator
programmed
data
such
as
memory
frequencies
and
telephone
number
data.
It
also
functions
as
a
data
buffer
when
exchanging
data
bet-
ween
the
Main
and
Auxilliary
processors.
Memory
address-
ing
is
performed
by
1C5
:
TC40H374P
with
read
and
write
operations
being
handled
by
the
Data
Bus.
¢.sa | M.CH /|
KOO a
KO1
SW RETURN
A,
Ga
&
§ D
mM a m
i
we!
=z ioe > ie
KO2
F.LOCK vA DCL J SCAN wal
4 Fd
KO3 #
RC2 R41 R40:
SW SCAN OUTPUT (ACTIVE LOW)
Fig. 10 Diode matrix
Switch Section
With a few exceptions most switch inputs on the front
panel are arranged in a diode matrix. The Main Micropro-
cessor reads the inputs via a keyboard status scan system.
This system determines which key, if any, has been de-
pressed.
The diode matrix is illustrated in Fig. 10.
The PHONE switch (K,M), P.MR switch (TW) TONE
switch, PTT switch, UP switch and DOWN switch all supply
inputs directly to the Main Microprocessor.
Keyboard section
Fig. 11 iHustrates the keyboard section circuit diagram. The
keyboard receives scan pulses from the Main Micropro-
cessor ports P10 thru P13. The current keyboard status is -
returned via ports R70 thru R73. Pull-up resistors of P10
thru P13 are controlled by port R90. Keyboard status is
scanned when R90 is pulled up from logic low by QO3 :
DTA114YF.
Display section
Fig. 11 shows the layout of the LCD.
The LCD driver (Keyboard ass'y) is controlled via 8 data
lines and 4 control lines on a parallel bus system by the
Main and Auxilliary microprocessors.
Data transfer is possible only when the CS line is Low and
in conjuction with the teading edge of the WE pulse. The
DCL and COS LED's are lit by transistors O04 and O5 which
are controlled by the Main Microprocessor.

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
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11
Keyboard
section
circuit
diagram
9

TM-2550A/E,2530A
10
CIRCUIT DESECRIPTION
DTMF circuit (K,M Type)
The
DTMF
(Dual
Tone
Multiple
Frequency)
signal
is
gene-
rated
by
IC4
:
LR4087
on
the
CONTROL
unit.
Power
for
the
tone
generator
is
obtained
from
the
8T
(8
volts
on
transmit)
line.
During
receive
the
IC
is
grounded
preventing
unwanted
tone
generation.
During
transmit
the
non-exclusive
port
R9O
is
a
logic
High,
causing
pull-up
resistors
P10
thru
P13
to
open
allowing
the
DTMF
signals
to
be
generated
by
pressing
one
of
the
key-
board
keys.
During automatic transmission of telehphone number infor-
mation port R90 is a logic Low, connecting pull-up resistors
P10 thru P13. P10 thru P13 apply a logic High, and P70
thru P73 a logic low, so that the desired DTMF signals are
generated. While the DTMF signal is being generated IC4
(CONTROL unit) mutes the normal transmitted audio.
_—_ —_ —_ . — a ee
i 5V - IC4 : LR4087
10 osc
aor
|
MES
MEOUT
“IN
z
|
ak
42
ar:
os
O13
yy
3
-_-—
|
—f
84
EH
_*
ie
Rt
OSC
OUT
0
4
4S
4S
fs
|
O14
43
16
|
oe eee eee kt R2 TOOUTE > TT | | |
7
|s
|9
[Lo
j
O15
yo
care
L
J
mmm
rm
1
R3 C3
|
Sy
ty
oy
Us
j
IN
4
L2
M
9
rs
rs
;
OG
,,
car
|
mM —_t}
So
oy
co
Ce
R4
Ct
|
.
|
\
t |
|
K,MTYPE ONLY |
‘
| oY
P10 P11 P12 P13. R73 R72 R71 R70
(K1) (K2) (K3) (K4) (KB) (K7) (K6) (KS)
Yv v
KEY
SCAN
KEY
RETURN
R30
Fig. 12 DTMF circuit
R1 R2 R3 R4 VE ove
141312)
1
—
—
— —
©
-
——7
ANA
Vt
MUTE
|
mM
KB>—]
50
OUT
—— Why
|
$—w-
|
|
[
yggare
var
ve
|
|
SIGN
D/A
|
ROW WAVE b+ TER
COUNTER
Jw—
COUNTER
CONVER
TONE
OUT
COLUMN
SIGN
D/A
Ve
COUNTER
ja—@
COUNTER
|
CONVERTER
|
KEYBOARD __f VKB |
| Locic Le yvxs
V+ XMTR
|
<M
:
sw
AAO
48)
SINGLE
TONE
Ww
~
INHIBIT
Wye VV —
3445
HO
—
eo
———
———
—
—
IJ
ci c2 C3 C4
Fig.13
LR4087
Block
diagram
(Control
unit
1C4)
K,
M
type
only

TM-2950A/E,2530A
CIRCUIT DESECRIPTION
PLL and Tone data (KX,M type)
PLL
and
Tone
data
are
sent
from
the
Main
Microprocessor
on
P30
and
the
Clock
signal
is
on
P33.
Data
and
Clock
signals
are
used
concurrently.
The
Enable
signal
is
trans-
mitted
on
P21
for
PLL
data
and
on
RCS
for
tone
data.
Audio Oscillator (CONTROL unit)
An
audible
confirmation
of
various
keyboard
inputs
is
provided
by
the
TM-2530/50.
This
audio
output
is
contro}-
led via
line
P21
of
the
Auxilliary
Microprocessor,
IC3.
The
Oscillator
isa
portion
of
i1C1
:
MC14584BCP
and
its
output
is
supplied
to
the
COMPOUND
unit
via
the
BZ
line.
Voice Synthesizer Control Section
The
Main
Microprocessor
(IC2)
analyzes
inputs
from
the
VOICE
unit,
and
provides
control
information
to
the
Auxil-
liary
Microprocessor
{IC3)
necessary
for
processing
the
Voice
data.
The
Auxilliary
Microprocessor
provides
control
input
and
output
via
data
lines
PSO
thru
PS4,
SR
and
BY.
Rotary Encoder Section
Fig. 14 shows the encoder output waveforms. Waveform Bis
used as a reference. The phase of waveform A is compared
with that of waveform B to determine if the dial base been
turned clockwise or counterclockwise. A portion of IC1 is
used as a Schmitt trigger to filter out any chattering of the
encoder contacts. The inverted waveforms from IC1 are
applied to the Main Microprocessor on pins RPO and RP1,
where the phase of the waveforms is compared. the number
of input pulses is also counted by the microprocessor to
detemine how much of a frequency change has been
ordered.
Other Input and Output Sections
1)
2)
3)
4)
5)
6)
Standby or push-to-talk
PTT switch status is sent to the Main Microprocessor
via the SS terminal on PS1. During manual or auto-
matic transmission a logic Low is supplied on the RA2
line to the COMPOUND unit. This signal turns on
the transmit voltage regulator and turns OFF the
receive voltage regulator.
Microphone UP/DOWN switches
Any switch chattering (Keyboard) is filtered by C11
and C12 and the inputs from the UP and DOWN
switch are applied to the Main Microprocessor on pins
RB3 and RB2 for processing.
Busy indicator (BD)
A signal is supplied from the COMPOUND unit Center
Tune circuit to the Main Microprocessor via pin RB2
to indicate when the radio has received an input and
squelch has opened.
Microphone Muting
In order to prevent inteference to the Digital signals
transmitted when using the DCL system the micro-
phone must be muted. This function is controlled by
Auxilliary Microprocessor via pin P61.
Squelch Switch (SC)
The Main Microprocessor provides a signal to control
the Squelch threshold level during Digital Channel
Linkage operations. Specifically this occurs when the
radio is scanning for an open channel. When the SC
terminal is a logic low, VR3 of the COMPOUND unit ©
is used to control the Squelch Threshold.
RX Audio Muting (AL)
The Main Micorprocessor provides a logic High on
P32 to mute the receive audio during Code Squelch
operation, Open Channel search operations, and
Priority channel scanning.
Fig. 14 Encoder output waveforms
11

TM-2550A/E,2530A
12
CIRCUIT DESECRIPTION
Resetting
the
Microprocessor
To
reset
the
Main
Microprocessor
(return
to
the
default
settings)
ground
pin
number
49
of
the
Main
Micropro-
cessor.
This
should
normally
only
be
required
when
re-
placing
the
Lithium
battery.
The
Auxilliary
microprocessor
is
reset
by
a
reset
pulse
from
IC7
:
PST520D.
N@TE
2:
The
operating
system
of
this
radio
is
in
NON-
ERASEABLE
memory
in
the
microprocessors.
Replacing/
removing
the
battery
will
not
require
reprogramming
of
Operating
System
paramaters.
Operator
programmed
in-
formation
(telephone
numbers,
memory
frequencies,
etc.)
will
require
reentry.
Memory backup
Transistor
Q2
2SC2458(Y)
and
zener
diode
D3
MTZ7.5JA
sense
when
the
voltage
supplied
to
the
DC
power
connector
drops
below
approximately
7.5
Vdc
from
its
normal
13.8
Vdc.
If
the
supply
voltage
falls
below
this
minimum
a
control
signal
is
supplied
to
the
HOLD
terminal
(pin
52)
of
the
Main
Microprocessor
via
a
Schmitt
trigger.
The
microprocessor
then
enters
the
backup
mode
and
draws
power
from
the
Lithium
battery.
17: PSTS20D |
SH
RESET (FL)
DCL. Contro System
A block diagram of the DCL contro! system is shown in
Fig. 16
Control of Open Channel searching is performed by the
Main Microprocessor. The microprocessor searches for an
open channel by controlling the frequency of the receiver
section. When an open channel is found the frequency data
of that channel is stored into RAM and a control signal is
applied
to
the
Auxilliary
microprocessor.
The
Auxilliary
microprocessor takes this signal, reads the frequency data
that was stored in the RAM, generates the Digital Contro!
signal, and applies this data to the MODEM unit
(X57-1140-20). The MODEM unit uses this incoming data
to generate the MSK (Minimum Shift Keying) signal which
is applied to the COMPOUND unit for transmission.
A portion of the incoming receive signal is applied to the
RD terminal of the MODEM unit. The MODEM unit
detects the prescence of any Digital Control signal and if
present relays it to the Auxilliary Microprocessor.
The Auxilliary microprocessor compares the incoming DCL
signal with the preprogrammed DCL data maintained in
memory. If the signals are equal a request is made to trans-
fer the incoming data into RAM. The Main microprocessor
detects this transfer request and passes the data into RAM,
and transmits a signal signifying data has been received, is
sounds an audible alarm.
The Main microprocessor performs any frequency shifts or
code squelch functions, determined by the incoming data.
«
[R91
PO3
inti
MC
rT
7
Tt
©
|
TX-RX
Control
8
Q
2
i
7
mo
|
:
2§
BUSY
Signal
54
§
peo
movem
unit
|
SO
[Ret
P22]
&e
°
1
(x57-1140-20)
|
zt
ao
|
Zé
Request
Signal
| 3a,
[poi
ME
|
Se
at
p-—_o—-+|
R80
P62
iL
-_
RAM
TC5047AP-1
RD
TD
Fig.
16
DCL
control
system
block
diagram
Power Momentary Power
ON power OFF
failure
Fig.
15
Reset
circuit
and
waveforms
at
respective
points

CIRCUIT DESECRIPTION
TM-2550A/E,2530A
PinNo. | Name |in/Out Function Logic | Pin No. | Name [In/Out Function Logic
1 RDO | Encoder E1 33 P20 is) 1750Hz Tone Controt (T,W) IL
2 RD1 | Encoder E2 34 P21 ie] PLL Enable Signal IL
3 R40 1/0 | Data Bus (DO) 35 P22 O | HD61602 RE Signal LS
4 R41 1/0 | Data Bus (D1) 36 P23 (o) HD61602 WR Signal “LY
5 R42 1/0 | Data Bus (D2) 37 P30 fa) PLL (Tone) Data Output
6 R43 1/0 | Data Bus (D3) 38 P31 (0) Squelch Control Signal TL
7 R50 1/0 | Data Bus (D4) 39 P32 O | Audio Mute Signal a
8 R51 1/O | Data Bus (D5) 40 P33 (0) PLL (Tone) Clock Output
9 R52 1/0 Data Bus (D6) 41 RBO j VOICE SW Input LI
10 R53 HO Data Bus (D7) 42 RB1 ) PHONE (K,M) SW input
14 R60 \ HD61602 READY Signal “LD P.MR (T,W) SW input LI
12 R61 | | SUB CPU Busy Signal IL) 43 RB2 ; MIC Down SW Input LE
13 R62 { Busy Signal 44 RB3 ! MIC Up SW Input LS
14 R63 \ Tone SW Input LP} 45 KOO ! SW Return (S1)
15 R70 | 16 Key Return (K1) 46 KO1 | SW Return ($2)
16 R71 { 16 Key Return (K2) 47 KO2 l SW Return (S3)
17 R72 { 16 Key Return (K3) 48 KO3 ! SW Return (S4)
18 R73 I 16 Key Return (K4) 49 RESET Reset Input LY
19 RAO O __| Memory Lamp SI-L| 50 Xin Clock
20 RA1 ie) RAM OD Signal Output 51 Xout Clock
21
RA2
QO
|
Standby
Signal
Output
‘LF
|
52.
|
ROLo
Back
up
Information
Input
LST
22 RA3 (e) RAM A8 Signal Output 53 R80 I SUB CPU Request Signal IL
23
POd
ie)
Address
Latch
S7k
54
R81
t
PTT
SW
Input
LI
24 PO1 ce) RAM CE Signal Output LA 55 R82 ! DCL Diode Matrix Input
25 PO2 (e) HD61602 CS Signal Qutput LI | 56 R83 \ SCAN Timer Trigger pulse
26 £03 ie) RAM CE2 Signal Output 57 R90 Oo Keyboard select
27 P10 ie) 16 Key Scan (K5) 58 R91 0) Serial Data Output
28 Pil ie] 16 Key Scan (K6) 59 R92 oO Serial Clock Output
29 P12 O__| 16 Key Scan (K7) 60 RCO O LED (DCL) Control LST
30 P13 ie) 16 Key Scan (K8) 61 RC1 io) LED (C.SQ) Control LI
31 TEST GND 62 RC2 Oo SW Scan
32
Vss
GND
63
RC3
Oo
Tone
DATA
LOAD
Signal
LST
64 VDD Power Supply
Table 7. TMP47C46N-9042 Terminal functions (Control unit 1C2)
Pin No. | Name |tn/Out Function Logic | PinNo. | Name [In/Out Function Logic
:| OOUT Open 21 CL2 Clock
2 P20 oO VS-1 PS4 22 INT1 ! Modem Clock Input
3 P21 (@) “Beeper’ Switching 23 POO i] Backup Clock Input
4 P22 (6) MAIN CPU Busy Signal STL 24 PO} ! Serial Clock Input
5 P23 ie) VS-1 SR 25 PO2 Open
6 P10 (e) Adress Latch SIL 26 PO3 | Serial Data Input
7 Pit 27 P6O 1/0 | Modem Data Input/Output
8 P12 i HD61602 READY Signal SILI 28 P61 e) Modem Me Signal Output
9 P13 O | VS-1 BY JL] 2 P62 O | MAIN CPU Request Signal STL
10 P30 ie) VS-1 PSO 30 P63 oO RAM A8 Signal Output
11 P31 (es) VS-1 PS1 31 P50 1/0 | DATA BUS (DO)
12 P32 oO VS-1 PS2 32 P51 1/0 | DATA BUS (D1)
13 P33 [e) VS-1 PS3 33 P52 1/0 | DATA BUS (D2)
14 P70 oO RAM OD Signal Output 34 P53 0 DATA BUS (D3)
15 P71 oO HD61602 €S Signal Output 35 P40 H/o DATA BUS (D4)
16 P72 oO RAM and HD61602 R/W 36 PA1 1/0 DATA BUS (D5)
17 P73 oO RAM CS7 Signal Output 37 P42 1/0 DATA BUS (D6)
18 RESET Reset Input 38 P43 (70 | DATA BUS (D7)
19 cli Clock 39 Vss GND
20 VDD Power Supply 40 EVENT GND
Table 8 uPD7508H-056 Terminal functions (Control unit IC3)
13

TM-2550A/E,2530A
14
CIRCUIT DESECRIPTION
TONE
unit
(X52-1330-20)
Incoming
serial
data
from
the
Controf
unit
is
converted
to
parallel
data
by
1C2:
MB88306.
Serial
data
on
the
DT
line,
and
the
serial
clock
is
on
the
CT
line.
When
the
ET
ter-
minal
is
high
data
is
transferred,
the
tone
output
can
be
disabled
by
setting
D1
to
logic
low.
This
can
also
be
done
by
switching
the
MIE
termina!
high.
iC1
:
S7116A
prevents
the
tone
generator
from
oscillating
outside
the
specified
limits.
MODEM
unit
(X57-1140-20)
The
modem
Q3
:
“PD65003C-20
uses
a
clock
frequency
of
3.6864MHz
that
is
supplied
across
pins
18
and
19.
Pin
13
is
used
to
select
transmit
or
receive
operation
of
the
modem.
Transmit
is
selected
when
pin
13
is
high,
and
receive
when
it
is
low.
Pin
12
supplies
the
modem
clock
(1200Hz)
to
the
MC
terminal
for
transmit
and
receive
clock
timing
purposes.
Data
transfers
are
based
on
this
clock
timing.
When
the
transmit
mode
has
been
selected
data
is
transferred
to
pins
1
thru
5
to
produce
the
1200
or
1800Hz
MSK
signal.
This
signal
is
then
digital
to
analog
converted
by
a
ladder
resistor
network
and
apptied
to
the
TD
terminal.
When
the
MODEM
unit
is
in
the
receive
mode
it
processes
the
signal
applied
to
pin
9.
This
digitized
Audio
Frequency
signal
is
received
from
the
RD
terminal
after
passing
thru
a
band-pass
filter
and
comparator
circuit.
This
signal
is
con-
verted
by
the
MODEM
unit
and
transferred
thru
pin
7,
shaped
by
the
LPF
and
comparator
and
applied
again
to
pin
8.
The
receive
data
and
clock
signa!
that
are
generated
by
the
modem
are
based
on
the
data
applied
to
pins
12
and
14.
12 8
MC °
13 nN
ME 3} LPF
MD
14
38
7
|_|
Waveform
w 8 / shaping
oe
ins] SS 49
A-D Convertor
Amp.
TD
_—__|
BPF
RD
|_|
Waveform
shaping
1200Hz 1800Hz
Fig. 17, MODEM unit (X57-1140-20) block diagram
VREF
VOUT(0)
(8C)
VOUT(1)
(8R)
©
CONTROL
(ST) ©-4
VOUT (2) (8T)
Lp—+—4t--4 | 4} +
CONTROL CIRCUIT
©
ono @—6-
Fig. 18 MB3756 Equivalent circuit (COMP unit 1C3)

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
51
ir aaa
1
cis Bias Cext C16 osc
I
.
15.
716
ar)
7
18
13
Power
supply
|
OSC,
Divider
COMMON
Vcc
To
other
circuit
LcD
|
Protection
EXCLUSI-
|
17
C
‘
VENOR
|
9 r
VOFF
ompare
fo)
;
OUT12
iN
Buffer
—
|
2
19
VR
max
R
!
VR
max
Buffer
-[_
oy
\
|
'
H
e
1
i}
.
AZo
VR
min
22)
GND
VR
mind
Buffer
a Rau 0 oD Part Name ne Nave 1/0 wD Remarks
3 $10 70
5 $s 8
7 $6 6
8
ss
O
_
LcD
5
Level
meter
segment
output
9
$4
4
10 $3 3
11 $2 2
12 $1 1
15
BIAS
-
Prevents
C12
oscillation
16
Cc
-
GND
External
clock
is
used;
C
is
grounded.
18 vcc ! _ Connector J6 8C2 | 8V power supply
19
|
VREF—MAX
Determines
level
10
voltage
value.
20 | VREF—MIN GND I Determines level 1 voitage value.
21 VIN D R21 Connector J6 M i Meter input (DC)
22 GND _ _ GND GND pin
Note: Pins not specified must remain open.
Table9 [R2429 Terminal functions
15

IM-2550A/E,2530A
PARTS LIST
CAPACITORS cc. 45 TH iH 220 J CC45 Color* © Capacitor value 1 0 3=0.01uF
1
2
3
4
5
6
=
0 1 O= 1PF 220 = 220F
1 = Type ...... ceramic, electrolyic, etc, 4= Voltage rating 1 0 0=10pF ‘ ;
2
=
Shape
......round,
square,
etc.
5
=
Value
|
1st
number
|
Multiplier
3
=
Temp.
coefficient
6
=
Tolerance
1
0
1=
100pF
2nd
number
@
Temperature
Coefficient
1
O
2=
1000pF
=
0.001
uF
1st Word c L P R s T U 2nd Word H R] K L
Color* Black | Red |Orange | Yellow | Green | Blue | Violet ppm/°C +30 | 260 | +120 | + 250 | + 500
°c 0 ~80 | —150 | —220 | —330 | —470 | —750
ppm/
Example
CC45TH
=
—470#60
ppm/°C
@ Tolerance
Code Cc D G J K M x Z P No code Code| 8 Cc D F G
(%) [2025/2065 | #2 | #5 | #10 | #20 | +40 | +80 |+100 | Moe topF—-10~+50 | fipF) | 201 |t025/205 | +1 | #2
-20 | —-20 | -o | 88 47yF-10~+75
Less than 10 pF
@ Rating voltage
2nd
word
A 8B Cc D £ F G H J K Vv
Ist
word
ie) 1.0 1.25 1.6 2.0 2.5 3.15 40 5.0 6.3 8.0 -
j 10 12.5 16 20 25 31.5 40 50 63 80 35
2 100 125 160 200 250 315 400 500 630 800 _
3 7000 4250 1600 2000 2500 3150 4000 5000 6300 8000 _
@ Chip capacitors Dimension
00 Di j d L
(EX)E=3
co}
.
esi
4
eons
23
_7—
Refer
to
the
above
table.
mension
code
Ww
T
yor i t ‘ ; Empty 5.6+0.5 5.0+0.5 | Less than 2.0
1 2 3
E 3.2 £0.2 1620.2 Less than 1.25
(Chip) (CH,RH,UJ.SL)
cK 73 fF F1HO00 2 F 2.0 + 0.3 1.25+0.2 Less than 1.25
(EX) ce3 Compe ye Sys
1234 5 6 7 Dimension
(Chip) (B.F} 1 = Type ...... ceramic, electrolytic, etc. | Dimension code L Ww T | Wattage
© Chip resistor (Carbon) 2 = Shape ...... round, square, etc. E 3.2+0.2 | 1640.2/057 | 2B
(exyhO 723 8 280004 3= Dimension F 2.04203 |1.2520.21045| 2A
ae) a ye a cya my 4 = Temp. coefficient
12 346 67 5 = Voltage rating Rating wattage
c ene) iN type) a ye eeance Cord | Wattage |} Cord | Wattage || Cord | Wattage Dimension
e orma = :
arbon resistor (Norma' type 2a |1 10w|| 2 | 1 4w | 3a [iw aw,
RO?t?4
8
82c¢cC000
$
hay
Lapeer ele ae el ms man 2B | 1 8WI 2H 1 2w || 3D 2W a
12345 6 7
16

TM-2550A/E,2530A
PARTS LIST
N_: New parts
SEMICONDUCTOR
*
:
Please
note
that
parts
are
sometimes
not
in
stock
and
it
takes
much
time
to
deliver.
{tem
metks
Part
No.
Item
mis
Part
No.
Diode
1N60
2SD1406(Y)
1N60A
1N4448
Chip
TR
28C2712(BL)
2SC2712(K)
181555
28C2712(Y)
181587
28C2714(Y)
1$2208
Digital
TR
28C3295(B)
18$106
188133
DTA1IT4YF
MA856
DTC114ES
MC911
DTC124EF
Mc921
DTC143TS
Mi308
M1407
N
|
UN2213
U15B
UM9401
FET
2SK30A(O}
2SK125
Chip
diode
.
N
18S$181
2SK192A(GR)*P
N 1S8S184
3SK74(L)
Vari-cap
41SV50
3SK129(S)
.
Power
module
M57726
Zener
diode
MTZ5.6JC
MTZ6.2JA
M57737
MTZ7 BJA
MTZ11JC
ic
N
HD61602
LED
N
|
LN38GPL
1R2429
LN222RP
LN322GP
LR4087
LN442YP
MB3756
N
U19DD306
MC14584BCP
MC145151P
LCD
N
FSS8066
MC145155P*K
Thermister
112-502-2
NES55P
TR
N
|
28A790(A)
NuM78M06A
2SA1015(Y)
NUM4558M
2SA1048(Y)
PST520D
2SC496(Y)
28C1775(E) N TA7761P
28C2347 TC40H374P
28C2458(Y) TC5047AP-1
28C2538-22-A TMP47C46N-9042
2SC2668(Y)
28C3019 N wPC1241H
uPD7508HC-056
TM-2550A
(K1,M1,M3)
TM-2550E
(T,W)
TM-2530A
(K2,M2,MA4)
FINAL
UNIT
X45-
1440-10
X45-
1440-10
X45-
1440-11
PLL UNIT X50-2030-10 X50-2030-51 X50-2030-11
CONTROL UNIT
X53-1440-10 (K1,M1)
X53-1440-21 (M3)
X53- 1440-51 (T)
X53- 1440-61 (W)
X53- 1440-10 (K2,M2)
X53-1440-21 (M4)
DISPLAY UNIT
X54- 1860-10
X84- 1860-10
X54-1860-10
COMPOUND UNIT
X60- 1280-10
X60- 1280-51
X60- 1280-10
17

TM-2550A/E,2530A
* New Parts
Parts without Parts No. are not suppliled.
Les articles mon mentionnes dans !e Parts No. ne sont pas fournis.
Telie onne Parts No. werden nicht gellefert.
PARTS LIST
Ref.
No.
Address
|New
Parts
No.
Description
Desti-
Parts
nation
SREes
|
£1
F
gm
#
FE
BASE
®
ic
TM-2550A/E,
TM-2530A
GENERAL
1
1G,2eF
|
*1
AQL-0996-02
METALLIC
CABINET
(TBP).
2
36
*)
ADI-0997-02
METALLIC
CABINET
(CBRTTRM)
3
2B,3F
|
*)
AZO-2550-03
PANEL
ASS
K1,K2,M1—M4
3
2B
*
20-2559-03
FANEL
ASSY
T1W1
4
2A
*{|
AZL-O791-04
DRESSING
PANEL.
(KEYB@ARD)
5
2A
*)
AL1L-O795~-04
DRESSING
PANEL
(DCL)
*
|
AL13B-0666-02
MOUNTAIN
BRACKET
ASSY
(R)
ACSY
-
*1
AL3-0667-02
MOUNTAIN
BRACKET
ASSY
(L}
ALSY
*
|
A13-0668-04
MBUNTAIN
HARDWARE
*|
BLi-0436-04
REFLECTION
GLASS
(BCS
»
CSM)
10
@F.2G|
*|
BO1-0655~-03
SIDE
ESCUTCHEBN
11
IF
*1
BO4-0411-04
SP
METAL
12
1F
BOS-0708-04
SP
SARAN
NET
13
2F
*)
BiQ-0675-04
FRONT
GLASS
14
3G
*|
B40-3610-04
MODEL,
NAME
PLATE
K1,.M1,M3
14
3G
*{
B40-3611-04
MODEL
NAME
PLATE
T1
Wi
14
3G
*]
B40-3619-04
M&DEL
NAME
PLATE
K2,M2,M4
1S
2A
*)
H43-1057-04
BADGE
K1,M1,M3
15
2A
*)|
H43~-1058~-04
BADGE
T1
1S
2a
*
|
B43-1059-04
BADGE
Wi
15
2A
*|
B43-1060-04
BADGE
K2,M2,M4
-
*|
Bli-O429-04
LIGHT
GUIDING
PLATE
(AL)
-
*)
B11-0430-04.
LIGHT
GUIDING
PLATE
(P.MR)
T1,.W1
*)
BLi-0431-04
LIGHT
GUIDING
PLATE
(F.LO&CK)
-
*)
B11-0432-04
LIGHT
GUIDING
PLATE
(PHONE)
K1,K2,M1—M4
-
*1
B11-0433-04
LIGHT
GUIDING
PLATE
(MAIN)
-
*|
Bii-0434-04
REFLECTION
GLASS(ON
AIR/F.
LACK
-
B46-0410-00
WARRANTY
CARD
K1,K2
~
*|
BSO-8039-00 INSTRUCTION
MANUAL
Ki,K2,M1—-M4,W1
-
*|
B5O-8040-00 INSTRUCTION
MANUAL
11
~
*
|
E30-2022-15
DC
CARD
ASSY
CACSY)
20
2G
Fi0-1206-04
GROUNDING
SPRING
al
it
F15-0649-04
SHADE
SHEET
(KEYB@ARD
PITB)
-
FOS-1031-05
FUSE
(108A)
ACSY
K1,M1,M3,11,W4
-
FOS-8021-05
FUSE
(8A)
ACSY
K2,M2,M4
-
F20-0521~-04
INSULATE
PLATE
(BOLITHIUM
BTRY
26
GO01-0818-04
COMPRESSION
SPRING
(KNOB)
27
G02-0505-05
KNQB
FITTING
SPRING
(AF/SQ}
28
it
*|
G10-0642e-04
SHADE
CLATH
-
*}
G11-0616-04
SHADE
SHEET
(F.
L&Ck)
~
*)
G13-0823-04
CUSHION
(MBUNTING
BRACKET
ACSY
-
*
|}
HO1-4671-03
ITEM
CARTAN
BAX
CINSIDE)
K1,M1,M3
-
#|
HO1-4672-03
ITEM
CARTQN
BRX
CINSIDE)
Ti
-
*
|
HO1-4673-03
ITEM
CARTON
B&X
(INSIDE)
Wi
~
*
|
HO1-4674-03
ITEM
CARTON
BX
CINSIDE)
K2,M2,M4
-
HO3-2268-04
QUTER
PACKING
CASE
K1,M1,M3
-
HO3~-2269-04
r
QUTER
PACKING
CASE
T1.W1
-
HO3-2270-04
QUTER
PACKING
(CASE
K2,M2,M4
-
H10-2501-03
POLYSTYRENE
FAMED
FIXTURE
|
-
*
|
H10-2608-02
PRLYSTYRENE
FAMED
FIXTURE
K1,M1,M3,T1,W1
-
*
|
H10-2609-02
POLYSTYRENE
F@AMED
FIXTURE
K2,M2,M4
18

» New Parts
TM-2590A/E,2530A
PARTS LIST
Parts without Parts No. are not supplied.
Les
articles
non
mentionnes
dans
le
Parts
No.
ne
sont
pas
fournis.
Telle ohne Parts No. werden nicht geliefert.
Ref. No. Address |New Parts No. Description Desti-
. Parts| nation
SRES & | Bd E FS BhaAS/sH i
- H25-0029-04 PRASTECTISN BAG (SCREW.NUT ETC)
- H25-0103-04 PROT TQN BAG (MIC.MNT BRET)
- H25-9106-04 PRAT TQN BAG
- HeS-01 16-04 PROT T8N BAG CALSY)
He5-O117-04 PROTECTION BAG (DE CARD)
33 IF J21~-1144~-24 SP MOUNTING HARDWARE (KEY/FIC)
34 wv * | JS21-4182-04 MOUNTING HARDWARE
35 1B;.28 J29-0409-04 SW KNOBS GUIDE CNBR)
_ JG2-0439-05 FART CARSY)
~ J19-1346-04 MI HRQK (ASY)
~ J61-0408-05 WIRE BAND
4) 3F *1 K21-0779-05 K NSB (MAIN)
41 3F #1 K23-0779-04 K'N&B CAF. SQ)
42 2A #] K29-3039-05 KNSB ASSY (PUSH SW)
43 a *| K29-3044-05 KN&B ASS (TACT SW)
45 N14-0526-14 ROUND NUT (VAL)
- NO?~-0008-04 HEX HEAD SCREW CALSY)
- NO9-0632-05 TAPTITE SCREW CALSY)
N14-0510-04 FLANGE NUT (ACSY)
NiS-1040-45 FLAT WASHER
NiS-1060-46 FLAT WASHER (ARSY)
~ Nt6-0060-46 SPRING WASHER (CAMSY)
- N8?-4008-41 BRAZIER TAPTITE SCREW CALSY)
_ N99-0304-04 SCREW WITH HEX HOLE (MNT BRET)
D NO9-0697-05 SEMUS SCREW (PANEL )
K N29-0301-04 STOPPER RING (TACT KNB&B)
- — $80-1406~-05 TAKT SW FOR MICRSHSNE (UP/DOWN)
48 1F *) TO?-0240-05 LBUDSPEAKER (FULLRANGE }
- T91-0331-05 MUCRBPHANE CALSY ) K1,K2,M1-M4,.W1
- T91-0335-05 MICROPHONE (ALSY) T1
50 In * | WO2-03571-05 RATARY ENCSDER
- WO1-0401-05 HEX WRENCH (ARSY)
- WO?-0326-05 LITHIUM BATTERY (BR2032)
oo éDs2G X45-1440-10 FINAL UNIT CTM-25500/E ) K1,.M1,M3,T1,W1
So 2D;2G| #1] X45-1440-11 FINAL UNTT (TM-253G0) K2,M2,M4
56 2G *] XS0-2030-10 PLL UNIT CTM-2550A ) K1,M1,M3
5G 2G * |) X50-2030-11 PLL UNIT (TM-25300A} K2,M2,M4
36 2G *] X50-2030-51 PLL UNIT CTM-25S0E } T1W1
a7 3F *) X53-1440-10 CANTRBL UNIT K1,K2,M1,M2-
a? 3F * | XS3-1440-21 CONTROL UNIT M3,M4
a? 3F #) XS3-1440-S1 CONTREL UNIT T1
5° 3F *| XS3-1440-61 CONTROL UNIT Wt
58 TR»LC] #; X54-1860-10 DISPLAY UNIT
39 2G *| X60--1290-10 CAYMPSUND UNIT K1,K2,M1—M4
59 2G #| X60-1280-S1 CONFOUND UNIT Ti Wt
FINAL UNIT (X45-1440-XX) -10: K1,M1,M3,T1,W1 -11:K2,M2,M4
Ci C455 2HO80D CERAMIC 8. ORF Dd K2,M2;,M4
Ce C4S5L2H1507 CERAMIC iSPF J
C3 Cl4SSL2HoOsor CERAMIC 5. OPF tC K1,M1,M3,T1Wt
c3 Cr4sSleHO60b CERAMIC & OFF Dd K2,M2,M4
4 CK45B2H1L02K. CERAMIC LOOOPF K
19

[M-2550A/E,2530A
20
> New Parts
Parts without Parts No. are not supplied.
Les articles non mentionnes dans le Parts No. ne sont pas fournis.
Telle ohne Parts No. werden nicht geliefert.
PARTS LIST
Ref.
No.
Address
|New
Parts
No.
Description
Desti-
Parts
nation
SRES
f&
££
F
Bm
FS
Bh
a/R
ie
CS
Ch4SsL2be2oT
CERAMIC
22PF
J
Cé
RC4SCHAHOLOC
CERAMIC
1.
OFF
Cc
Cr
9
Cl45SLeHe20T
CERAMIC
ear
J
C10
CC45CH1LHOLOC
CERAMIC
1.
OFF
C
mit
12
Ce45SL2Ht00D
CERAMIC
1LOPF
D
Ci3
REO4Witeeom
ELECTRA
22UF
16WY
14
CKASBLIHIO2K
CERAMIC
1000PF
kK
Cis
CEB4WICe2OM
ELECTR
Baur
16WV
16
-19
CRASBLHTO2K
CERAMIC
1OQ0PF
K
Cel
~25
CE4SBLHIO2K
CERAMIC
JOOOFF
kK
26
CSLSELCIRIM
TANTAL.
3.
3UF
L6WV
C27
C91-0667-05
CERAMIC
0.
BO47UF
kK
C28
CK45BiH1O2K
CERAMIC
1000FF
K.
29
C91-0667-05
CERAMIC
0.
OO47UF
Kk
[30
-34
CK4SBLH102K.
CERAMIC
1O000RF
K
100
3E
£04-0161-05
M
TYPE
RECEPTACLE
101
2D
E11-0401-05
EAR
PHONE
JAK
102
3D:2G6
E30-2021-25
PRWER
SUPFLY
CORD
105
PE,1G}
*}|
FO1-0931-05
HEAT
SINK
K1,.Mi,.M3,T1,W1
105
2E
1G)
*|
FO1-0935-05
HEAT
SINK
K2,Mz,Mi4a
Fi
FOS~-1031-05
FUSE
CiBA)
K1,M1,.M3,71,W1
Fi
FOS-8021-05
FUSE
(8A)
K2,.M2,M4
108
iD
#{
J11-0409-05
WIRE
CLAMPER
109
3D
J41-0017-05
BUSHING
CCARD)
Li
L34-1020-05
PATL
(93:3.
5)
Lz
L34-0908-05
CAT
(63,3.
57)
L3
L34-0692-05
CAIL
(65,47)
L4
34-0452~-05
BTL.
(83:61)
LS
L.34-0908-05
CATL
(63:3.
5T)
L6é
L34-0742-05
CATh
(93,55T)
L.?
L.34-0823-05
ATL,
(05537)
LB
9
L40-1092-14
SMALL
FIXED
INDUCTOR
C1UH)
mM
NO?-0623-04
SCREW
(SEMUSE
)
N
NO9-0626-04
SCREW
(SEMUSE
)
R92-0150-05
JUMPER
REST
QO
8HM
;
Re
RDL4DB2HiSiT
SMALL
-RD
150
Jo
o1/72W
(K1.M1,M3,T1,W1
R2
RDL4DB2H1817
SMALL.-RD
180
J
i/2W
1K2,M2,M4
VRI
Ri2-0434-05
TRIMMING
POT.
CiBO8HM)
VR2
R1i2-4417-05
TRIMMING
POT.
(SOKQHM)
VR3
Rile-3455-05
TRIMMING
FAT.
CLOKSHM)
VR4
R12-441
7-05
TRIMMING
POT.
CSOKSHM)
DI
ULSB
DIQDE
sy
MI407 DIQDE
K2,M2,M4
D2
UMI401
DIQDE
K1,M1,M3,T1,W1
D3
MI308
DIQDE
D4
35
1Sis587
DISDE
ai
MST
726
PQWER
MADULE
K1,M1,M3,T1,W1
mi
MS?
73?
PQWER
MODULE
K2,M2,M4
Qe
25D1406(7)
TRANSISTOR
3
258101350)
TRANS
ISTAR
4
—-?
eal243B
(Y)
TRANS
ISTSR