Kenwood TR-751A User manual

144MHz ALL MODE TRANSCEIVER
_TR-751A/E
|
TRIO-KENWOOD CORPORATIC
.
SERVICE
MANUAL
|
| ©1986-5 PRINTED IN JAPAN
BS51-2084-00(0)1501
Photo is TR-751A.

TR-751A/E
CIRCUIT DESCRIPTION
MODEL
UNIT
TR-751A (K, M1, M2)
TR-751E (W, T)
FINAL UNIT
X45-1490-11
X45-1490-11
CONTROL UNIT
X53-1460-11 (K, M1)
X53-1460-21 (M2)
X53-1460-51 (T)
-_X53-1460-61 (W)
COMPOSITE UNIT
X60-1310-11
X60-1310-
(PLL,
TX)
3
00:5319;0)
COMPOSITE
UNIT
a
X60-1320-11
X60-1320-00
|
Table 1 TR-751A/E PC board chort
FREQUENCY CONFIGURATION
The TR-751A/E utilizes a PLL synthesizer system in-
corporating
a
digital
VFO,
which
covers
each
band
in
50Hz steps. (See Fig. 1.)
Received
signals
are
mixed
with
the
first
local
oscillator
(133.305
to
137.295MHz)
to
produce
the
first
intermediate
frequency
of
10.695MHz.
In
SSB
or
CW,
the
receiver
operates
as
a
single
conversion
system.
The
10.695MHz
IF
signal
is
applied
to
crystal
filter
XF1
(L71-0249-05),
and
the
signal
is
then
applied
to
the
ring
detector
to
obtain
the
audio
output.
In
FM,
the
receiver
operates
as
a
double
conversion
system.
The
10.695MHz
signal
is
mixed
with
the
PLL
re-
ference
frequency
of
10.24MHz
to
produce
the
second
intermediate
frequency
of
455kHz.
The
transmitter
system
operates
as
a
double
conversion
system.
In
SSB
mode,
output
from
the
carrier
oscillator
is
modulated
by
a
balanced
modulator
to
produce
an
inter-
mediate
frequency
signal,
which
is
then
mixed
with
the
first
local
oscillator
signal
to
produce
the
two
meter
transmit
signal.
The
carrier
oscillator
circuit
is
controlled
by
the
microprocessor
according
to
the
selected
mode.
During
USB
or
CW
receive,
the
carrier
oscillator
fre-
quency
is
10.6935MHz.
During
LSB
receive,
it
is
10.6965
MHz.
During
CW
transmit,
it is
10.6943MHz.
In
FM,
a
455kHz
10.695MHz
crystal
oscillator
frequency
is
used
that
is
directly
modulated
and
then
mixed
with
the
first
local
oscillator
signal.
To
minimize
internal
heterodyne
tones
and
spurs
in
the
frequency
generator
and
analysis
are
controlled
by
a
microprocessor.
The
PLL-based
frequency
system
consists
of
two
PLL
synthesizer
loops
controlled
by
a
4-bit
high-
speed
microprocessor
and
a
stable,
analog
RIT
oscillator
circuit.
Item
Nominal frequency
10.695MHz_
Within 2200Hz at 6d8_
|'2.2kH2 or more at 6d8
| Witt +1.5kHz at 20dB
Within #2.4kHz at 608
Allowable center freq’ deviation
Pass bandwidth and
attenuation bandwidth
(based on minimum loss).
Ripple 7 248 or less
Minimum loss | SdB or less
Guaranteed
attenuation
4
60dB
or
more
within
t40kHz
1/0
terminating
impedance
1.2k225%/60F
25%
Table
2
Crystal
filter
10F2.2S
(L71-0249-05)
characteristics
(Composit unit (RX) XF1)
5 : 2sc2714(¥)
MIXER
Qn
1as0~te6
ome
10.6935MHz
10.6965MHz
L PLL SYSTEM ] 10.24Mtz
é T oWax : 10.c035mHe
"AR
OSC
;
iz
l CW-TX = 10.69¢3MH2 J
133.305~137.295MHz
10.695MHz
XF (RX, TX common)
10.695MHz rl
+
| MIXER
Fig. 1 Frequency configuration

RECEIVER SYSTEM
© General
Incoming
signals
from
the
antenna
pass
through
a
low-
Pass
filter
in
the
Transmitter
Final
unit
and
a
diode
switch
(D5,D6)
for
transmit/receive
selection.
The
signals
then
go
through
two
antenna
coils
(L201
and
L202)
and
then
are
amplified
by
a
GaAs
FET
(Q201).
Undesired
signals
are
removed
from
the
RF
signal
by
a
3-pole
helical
resonator
(L203)
and
the
resulting
signal
is
then
applied
to
the
first
mixer
(Q202).
The
signal
is
mixed
there
with
the
first
local
oscillator
signal
from
the
PLL
system
to
produce
the
first
IF
signal
of
10.695MHz.
Undesiable
adjacent
channel
signals
are
removed
from
the
first
IF
signal
by
a
two
stage
monolithic
crystal
filter
(MCF
:
XF201).
The
first
IF
signal
is
then
distributed
to
either
the
SSB
2 @
or FM circuits.
@
In
the
SSB
circuit,
the
first
IF
signal
goes
through
noise
blanker
gate
(D1
and
D2)
then
amplified
by
a
Dual
Gate
MOS
FET
(Q1)
and
then
applied
to
the
SSB
crystal
filter
(XF1).
The
filtered
signal
is
then
amplified
by
the
Ist
IF
Amplifier
(Q2)
and
the
2nd
IF
Amplifier
(Q3)
and
then
applied
to
the
ring
detector
(D5—D8)
to
obtain
the
recei-
ved audio signal.
In
the
FM
circuit,
the
first
IF
signal
is
amplified
bya
~
Grounded
Gate
(Q4)
J-FET
and
applied
to
the
second
é€
mixer
(Q5).
The
IF
signal
is
mixed
with
10.24MHz
to
pro-
duce
the
second
IF
signal
of
455kHz.
Adjacent
channel
~
_
interference
is
removed
from
the
second
IF
signals
by
FM
ceramic
filter
(CF1),
the
second
IF
signal
is
then
amplified
and
detected
by
IC2
to
obtain
the
received
audio
signal.
The
audio
signal
from
the
SSB
and
FM
circuits
is
then
amplified
by
a
common
audio
preamplifier
Q1
(X59-
1110-00).
High-frequency
components
are
removed
from
the
audio
signal
by
an
active
LPF
(Q2).
The
audio
signal
is
then
applied
to
the
audio
volume
control
on
the
front
6
Panel.
The
audio
signal
is
amplified
again
by
audio
amplifier
1C1
(X60-1310-XX)
and
then
applied
to
the
speaker.
Item
|
Rating
Nominal
center
frequency
(fo)
|10.695MHz
Pass
bat
width
_
‘a
___|
Within
£7.5kHz
at
348
Within *25kHz at 4008
Within 245kHz at 6008
Attenuation bandwidth
40d8 or more spurious
| at fo~fo + SOO0kHz
| 80d8 or more spurious at
_ | fo—(9102 10kHz)
Ripple
|
1.008
or
less
[inser
ion
loss
1.5dB
or
less
Guaranteed attenuation
70d8 or more within + 1MHz
| 3k2/00F
€ = _ [Terminating impedance
Table
3
10.695MHz
MCF
(L71-0216-05)
characteristics
(Composit
unit
(RX)
XF201)
TR-751A/E
CIRCUIT
DESCRIPTION
Item
|
Rating
Nominal
center
frequency
_|
455kHz#
1kHz
-
6dB
bandwidth
26kHz
(from
455kHz)
50dB
bandwidth
__|
Within
£12.5kHz
(from
455kH2)|
Ripple
(within
24kHz
from
455kH2)
_
|
948
oF
less
[iosertion
loss
—
68
or
less
_
Guaranteed
attenuation
(within
#100kHz
from
455kH2) |
9548
oF
less
|20ka
Lv matching impedance
Table
4
Ceramic
filter
CFW
455F
(L71-0315-05)
characteristics
(Composite
unit
(RX)
CF1)
© Front end and AGC circuit
The
performance
of
any
receiver
is
determined
largely
by
the
performance
of
its
front
end
section.
Important
factors
which
determine
the
performance
of
a
receiver
are
sensitivity
and
two
signal
characteristics.
Recently,
most
single
mode
receivers
have
used
GaAs
FETs
to
improve
their
sensitivity,
while
all-mode
receivers
used
Dual
Gate
MOS
FETs
for
improved
AGC
characteristics
and
RF
gain
control
of
their
high
frequency
amplifiers.
This
was
because,
even
though
the
AGC
line
was
placed
between
the
high
frequency
amplifier
and
intermediate
frequency
ampli-
fier,
the
best
way
to
improve
the
AGC
characteristic
had
been
to
control
the
second
gate
of
the
dual-gate
MOS
FET.
When
GaAs
FET’s
were
used,
such
AGC
characteris-
tics
had
not
been
obtained
even
if
the
second
gate
was
controlled
by
the
same
voltage
that
was
used
for
a
Dual
Gate
MOS
FET.
Fig.
2
shows
the
AGC
Vs.
gain
attenuation
Characteristics
obtained
from
the
high
frequency
amplifier
(MOS
FET
:
3SK76)
and
GaAs
FET
:
3SK129
used
ina
TR-9000G.
Since
the
intermediate
frequency
amplifier
uses
a
MOS
FET
:
3SK73,
almost
no
attenuation
occurs
in
the
high
frequency
amplifier
even
if
the
AGC
voltage
is
fed
directly
into
the
GaAs
FET.
RF AMP GAIN
OdB when G2 voltage is 4V
G2 Voltage (Vv)
————- 3SK76 MOSFET
————— 35K 129 GoAsFET
Fig.
2
AGC
attenuation
comparison
3

TR-751A/E
CIRCUIT DESCRIPTION
The TR-751A/E AGC circuit has been designed to allow
the AGC voltage to control the GaAs FET similar to the
control that was obtained with the MOS FET. As shown
in Fig. 3, AGC voltage from an amplifier similar to that
used in previous models is fed into the intermediate fre-
quency amplifier. The AGC voltage is approx. 4V when no
signal is present. The AGC voltage is amplified by the
non-DC current inversion amplifier circuit that is com-
posed of Op Amplifier (1C3). Its output is then applied to
the GaAs FET. The output voltage is set to approx. 2.5V
when no signal is present, or at minimum RF gain. The
AGC characteristics are shown in Fig. 4. The AGC time
constant is automatically switched to slow in SSB mode
or to fast in CW mode. The high sensitivity of the receiver
system is thus obtained without sacrificing any two signal
characteristic.
Additionally, the RF gain control, provides a convenient
method of tuning out undesired signals even when receiving
signals that are too strong from near by local stations.
AGC
BUFFER OErELTOR
VF
AGC TIME CONSTANT
AGC AMP SWITCHING CIRCUIT
RF AMP GAIN
wav.
0d8 when G2 volta
G2 Voltage (v)
Fig. 4 AGC attenuation comparison
RF AMP AGC
VOLTAGE SHIFT CIRCUIT
VF VF
IF AMP AGC
1 r 71
0 +8V
THRESHOLO.
LEVEL AO. 3
2,03
3SK73 c20
SSB IF AMP O—=—| |
To
O RF AMP AGC LINE
NON-DC CURRENT
INVERSION AM
1C3 : NIMASSBC
g RF GAIN
CONTROL
fo)
Sse SOL TIME CONSTANT SWITCHING
Fig. 3 AGC circuit black diagram
©@ SSB squelch circuit
The TR-751A/E SSB suqlech circuit is a noise operated
type squelch. As compared with signal type squelch,
noise detection squelch may be opened even by very weak
signals, such as are frequently encountered in SSB.
The high sensitivity of the squelch circuit provides
advantages
when
receiving
VHF
signals
from
distant
sta-
tions
and
when
scanning.
Generally,
signal
type
squelch
cannot surpass noise detection type in sensitivity, since
they
are
opened
by
changes
in
the
AGC
voltage.
It
means
that, to open a signal type squelch, sufficient voltage level
of signal to deflect the $ meter is required. The sensitivity
of
the
TR-751A/E
squelch
is
0.14V
or
less
(a
weak
signal
which will not deflect the S meter.)
The squelch signal is applied to 1C2 used in FM mode,
through the SSB filter, SSB IF, and buffer amplifier. This
IC, mixes the signal with 10.24MHz to produce 455kHz.
Like the FM IF, the 455kHz signal is also amplified by 1C2
and applied to the same squelch circuit as that used in FM
mode. Since SSB signals do not contain carrier, unlike FM
signals, the time constant circuit is switched between FM
mode and SSB mode to get an appropriate response time.

TR-751A/E
CIRCUIT DESCRIPTION
TRANSMITTER SYSTEM
© General
The transmitter system operates as a single conversion
system,
Audio signals from the microphone are amplified by a
low-noise transistor (Q25) and applied to the SSB or FM
circuits which provide approx. 26dB gain
In SSB, the amplified signal passes through the SSB
microphone gain control, and is amplified by (Q27) and
applied to the balanced modulator (IC4). The balanced
modulator consists of an IC that provides stable carrier
suppression without being influenced by changes in tem-
perature. Signals from the microphone amplifier are mixed
with the carrier to produce a DSB signal. The DSB signal is
applied to the SSB filter (with a center frequency of
10.695MHz) to produce the SSB signal.
In FM, the signal amplified by the SSB/FM common micro-
phone amplifier (Q25) is applied through the buffer ampli-
fier (Q24) and FM microphone gain control, and then to
the pre-emphasis circuit, amplified by (1C1), and limited by
Op amplifier (1C1). High frequency components are then
removed from the signal by a 18dB/oct splatter filter,
and the signal is sent to the FM modulation circuit.
In the FM modulation circuit, signals from the 10.695
MHz crystal oscillator circuit are directly modulated by
varactor diode (D21), variable capacitor. This direct fre-
quency modulation enables a flat transmitter frequency
response to be obtained from low frequencies to high
frequencies. If the frequency deviation becomes excessive,
the deviation level will vary from the upper to the lower
portion of the signal. The TR-751A/E is designed so that
the upper and lower portions of the signal are balanced
even with maximum frequency deviation.
SSB/FM switching is performed by diode switching cir-
cuit
according
to
the
selected
mode,
and
then
amplified
by the transmitter IF circuit. This IF amplifier circuit con-
sists
of
a
dual-gate
MOS
FET,
whose
second
gate
is
pro-
vided
with
ALC
voltage
to
control
the
transmitter
output.
The
transmitter
IF
signal
is
then
mixed
with
the
PLL
signal
by
balanced
mixer
consisting
of
two
FETs
(Q1,
Q2)
to
produce
a
144MHz
signal.
Undesirable
components
are
removed
from
the
signal
by
a
band-pass
filter
to
mini-
mize
spurious
emission.
The
signal
from
the
band-pass
filter
is
then
amplified
twice,
once
by
a
dual-gate
MOS
FET
(Q3)
and
once
by
transistor
(Q4),
to
raise
the
signal
to
the
level
necessary
to
drive
the
Final
unit.
The
TR-751A/E
contains
an
additional
transistor
amplifier
(Q5)
The
signal
from
the
drive
circuit
is
amplified
by
the
power
module
(Q1)
in
the
Final
unit,
and
goes
through
the
ANT
switching
and
diodes
(D5,
D6)
and
low-pass
filter
to
remove
higher
harmonics,
and
is
supplied
to
the
antenna
© CW circuit description
In CW, the balanced modulator is unbalanced by AGC
signal to allow the carrier to pass.
CW keying is performed by switching the balanced
mixer in the drive circuit and a bias voltage is applied to the
first gate of amplifier. Fig. 5 shows the keying waveform.
The leading and trailing edges are smoothed to prevent key
clicks.
To facilitate CW communications, the CW circuit con-
tains CW semi break-in and side tone circuits.
The CW semi break-in circuit is a Schmitt circuit consist-
ing of transistors (Q1—Q4) or the break-in sub assembly.
The delay time can be adjusted with VR7.
The side tone circuit operates whenever the key is
closed. The side tone circuit operates in modes other than
CW, so key adjustment and morse code practice can be
performed. Transistor (Q9) is used as the oscillator. Signals
from the side tone circuit are amplified by the audio amp-
lifier (1C1). The output frequency of approx. 800Hz
can be adjusted with potentiometer (VR4).
TT TM,
ai I
cell
iii |
|
ee LUTATNE EUUGUGLOGEUOCE!:SUEEUEE ALUTUNUELLETUONNL LY
| |--smeee
Fig. 5 CW waveform

TR-751A/E
CIRCUIT DESCRIPTION
@ ALC and SWR protection circuits
Fig.
6
shows
the
basic
ALC
and
SWR
protection
circuits.
The
SWR
protection
circuit
detects
and
amplifies
any
ALC
detection
is
made
by
amplifying
a
sample
from
the
reflected
power
due
to
mismatching
in
the
antenna
with
a
Power
module
in
the
Final
unit..
The
DC
output
signal
is
CM
coupler.
Output
from
the
SWR
protection
Circuit
amplified
by
transistor
(Q7)
lower
the
ALC
which
controls
lowers
the
ALC
reference
voltage
to
reduce
the
gain
of
the
the
gain
of
the
IF
amplifiers.
Low
power
is
selected
by
power
module
for
protection.
controling
the
ALC
Amplifier
(Q7)
with
transistor
(Q8)
If
the
linearity
of
the
Final
is
not
well
balanced
with
ALC
feedback,
SSB
distortion
may
occur.
The
TR-751A/E
is
designed
to
minimize
SSB
distortion.
—
a
FINAL
UNIT
(X45-1490-11)
TE IE
AME
|
ALC
DETECTOR
SWR
PROTECTION
DETECTION
f
1
fi
. ,
024:3SK73(GR)
|
91
:ms7727
= eee
COMPOSITE UNIT (X60-1310-XX)
LOW POWER SW
Low
POWER
SWITCHING
‘ALC
AMP,
PROTECTION
AMP
Fig. 6 ALC and SWR protectioncircuits

PLL SYNTHESIZER
Fig. 7 is the PLL system block diagram,
nd
The
most
important
feature
of
the
TR-751A/E
PLL
system
is
that
it
the
main
loop
VCO
(Loop
A)
is
composed
of
a
sub-unit
to
avoid
the
unit
being
influenced
by
outside
forces
(especially vibration),
which
improve
the
frequency
stability.
During
mobile
operation
in
SSB
or
CW,
this
Provides
a
great
increase
advantage
in
reliability.
The
PLL
system
uses
two
loops
to
form
a
digital
VFO
which
covers
each
band
in
50Hz
steps.
Each
of
the
loops
uses
a
PLL
IC
(TC9172P)
with
pulse
swallow
type
pre-
scaler.
The
B
loop
utilizes
a
2.5kHz
comparison
frequency.
The
range
of
its
VCO
output
fregency
is
from
28
to
27MHz
(frequency
division
ratio
11200
to
10800
:
1).
The
B
loop
VCO
output
is
frequency
divided
by
50
(to
produce
©
560
to
540kHz).
which
is
used
to
produce
a
signal
that
covers
20kHz
from
9.68
to
9.70MHz
in
5OHz
steps.
This
signal
is
then
mixed
with
the
reference
oscillator
frequency
of
10.24MHz.
UNLOCK Sw
6 a7
TR-751A/E
CIRCUIT DESCRIPTION
The
RIT
oscillator
circuit
utilizes
a
signal
of
11.805MHz
which
is
multipled
by
nine.
The
oscillator
frequency
range
can
be
varied
+1.2kHz
or
more
by
varying
the
voltage
of
the
variable
capacitor
in
the
oscillator
(analog
control).
When
the
RIT
switch
is
off,
the
variable
capacitor
voltage
is
fixed,
because
of
high
resistance,
and
the
RIT
oscillator
operates
as
a
stable
local
frequency
oscillator.
The RIT
ON
signal
is
detected
by
the
microprocessor
and
transferred
to
the
PLL
IC
containing
which
contains
an
I/O
port
to
control
the
RIT
switching
circuit.
The
RIT
oscillator
out-
Put
is
mixed
with
9.68
to
9.70MHz
to
produce
a
frequency
fange
from
115.925
to
115.945MHz
for
A
loop
mixing.
The
A
loop
uses
a
20kHz
comparison
frequency
to
control
loop
A
over
a
range
of
IF
17.38
to
19.37MHz
to
yield
a
VCO
output
range
frequency
from
133.305
to
137.305MHz
(frequency
division
ratio
869
to
1069
:
1).
To
cover
the
entire
band
in
50Hz
steps,
the
VCO
output
is
mixed
with
local
oscillator
signals
of
115.925
to
115.945
MHz.
As
described
above,
the
PLL
system
reliability
is
im-
Proved
by
incorporating
the
VCO
A
loop
asa
sub-unit
and
high
density
system
by
using
large
scale
integration.
fea TATBIO"
raw | 10. 20mne 5
b——4 ozenne A
~stoune
tan 10685
fet (133.305 ~137308 139.3065 ~137.3085 139.0:
NA _ 865-1088
7
NB
1120-10890
=
=
_
t
Fig.
7
PLLsystem
block
diagram

TR-751A/E
CIRCUIT DESCRIPTION
DIGITAL CONTROL UNIT
© General
The Control unit consists of two PC boards : one on the
front
panel
and
the
other
on
the
main
chassis.
The
pro-
cessing
is
controlled
by
three
microprocessor
(hereafter
called the MPUs).
Fig.
8
is
the
Control
unit
block
diagram.
The
Control
unit
includes
three
MPUs,
their
interface
ciruits,
an
input
circuit
(consisting
of
a
rotary
encoder,
keys,
and
switches),
a
reset
backup
circuit,
a
mode
switching
circuit,
and
various
other
switching
circuits.
tscan'contnouy
vo
(voiee outs
me |
iw
rao
prorsorser
(woot enances
Yom ic ute
a
if g
oe
‘berter
iden
rome
out)
Fig. 8 Control unit block diagtam

€
€
CIRCUIT DESCRIPTION
@ MPU interface circuits
Fig.
9
shows
how
the
three
MPUs
are
interfaced.
To
exchange
data
between
the
MPUs,
three
clock
and
data
W/O
lines
(SCK,
SI
and
SO)
and
two
each
of
contro!
lines
SCK,
SOR,
DCK,
and
DRQ
are
provided
FRONT PANEL
(X$3-1460-XX) (8/6)
© Reset backup circuit
Fig.
9
also
shows
the
reset
backup
circuit.
When
the
transceiver
power
is
turned
on,
an
approx.
20ms
H
level
Pulse
is
sent
from
the
reset
circuit
using
a
dedicated
reset
IC
(IC201)
to
the
RES
line.
Since
the
RES
line
is
connect-
ed
to
all
MPUs
(MPU-I,
MPU-II,
MPU-III),
the
MPUs
begin
operation
at
the
same
time.
When
the
power
is
turned
off,
1C202
recognizes
that
the
voltage
of
the
5V
line
fell
to
4.5V
or
less,
and
sets
the
low
voltage
fallen
detect
line
(VFD)
to
a
low
level.
The
VFD
signal
is
sent
to
MPU-I
POO
and
MPU
enters
the
backup
mode.
Output
voltage
from
the
lithium
battery
for
backup
is
supplied
to
MPU-I
and
MPU-II
providing
backup
for
two
MPUs.
I MAIN CHASSIS.
) (X53-1460-XX) (A/6)
a
SV LINE
RESET CIRCUIT
5 L LOW VOLTAGE OeTecT |
im — 83 oureut
IC 202 :pstsz3c & (% when the SV line falls )
EQUIVALENT 3 | Ito 4.5v oF less during power on.
CIRCUIT
3
qu
LITHIUM BATTER’
Fig.
9
Intertace
between
MPUs
and
reset
backup
circuit

TR-751A/E
CIRCUIT
DESCRIPTION
@
Key,
switch
and
encoder
circuits
MIC
Pin
6
Fig.
10
shows
the
key,
switch,
and
encoder
input
cir-
Port
bit
0
cuits.
The
front
panel
keys
are
arranged
in
a
matrix
and
key
‘Switch\
Port
[ur
signals
are
sent
to
MPU-II,
using
a
key
scan
technique.
The
UP+DWN
|
0
0
ry
microphone
switch
lines
(PTT,
UP,
DOWN,
etc.)
are
con-
f
RES
0
0
1
nected
to
MPU-II
through
the
protection
diodes,
CR
time
DOWN
0
7
0
constant
circuit,
and
chatter
absorption
circuits.
The
CHL
To
lq
1
encoder
is
also
connected
to
MPU-II
through
the
CR
time
[up
1110
0
Constant
Circuit
and
the
inverter
of
the
Schmitt
trigger
in-
MR
1
|o
1
puts
(1C201)
for
chattering
absorption.
1
0
1 1
[_Ps2
P51
P50
Pag
lv
cK
|
COM/TOME|
VOICE/TONE
7
4
-
RIT
FUNC.
_cso_
|
res
|
CHL
FM/LS8
[3]
US8/CWTa]
REV
tS
SCAN
fg]
_M_
[o]OFFSET
To
wey
hie
R214 072)
0207
4}
0206 (22)
Kt
x
ee ‘
| “eh” pd| ahd
oo bP P| ee
Fig.
10
Key,
switch
and
encoder
input
circuit