Laird SSD50NBT User manual

A
User Guide
SSD50NBT
Version 1.0

SSD50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
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REVISION HISTORY
Version
Date
Notes
Approver
1.0
22 Feb 2016
Preliminary Release
Connie Lin

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CONTENTS
Scope ..........................................................................................................................................................................4
SSD50NBT Features Summary....................................................................................................................................4
Specifications..............................................................................................................................................................5
WLAN Functional Description.................................................................................................................................. 10
Bluetooth Functional Description............................................................................................................................ 14
Electrical Characteristics.......................................................................................................................................... 15
Absolute Maximum Ratings ................................................................................................................................ 15
Recommended Operating Conditions ................................................................................................................. 15
DC Electrical Characteristics ................................................................................................................................ 16
WLAN Radio Receiver Characteristics ................................................................................................................. 18
WLAN Transmitter Characteristics ...................................................................................................................... 19
Bluetooth Radio Characteristics .............................................................................................................................. 21
SDIO Timing Requirements...................................................................................................................................... 22
Pin Definitions ......................................................................................................................................................... 24
Boot Straps Options for Wi-Fi Interface .................................................................................................................. 27
Mechanical Specifications ....................................................................................................................................... 28
RF Layout Design Guidelines ................................................................................................................................... 29
Recommended Storage, Handling, Baking, and Reflow Profile............................................................................... 30
Required Storage Conditions............................................................................................................................... 30
Baking Conditions................................................................................................................................................ 31
Surface Mount Conditions................................................................................................................................... 31
Soldering.......................................................................................................................................................... 31
Cautions When Removing the SIP from the Platform for RMA....................................................................... 32
Precautions for Use ......................................................................................................................................... 34
Regulatory ............................................................................................................................................................... 34
Certified Antennas............................................................................................................................................... 34
FCC and IC Regulatory ............................................................................................................................................. 34
FCC....................................................................................................................................................................... 35
Federal Communication Commission Interference Statement....................................................................... 35
End Product Labeling....................................................................................................................................... 36
Manual Information to the End User .............................................................................................................. 36
Industry Canada................................................................................................................................................... 36
European Union Regulatory .................................................................................................................................... 39
EU Declarations of Conformity................................................................................................................................ 39
SSD50NBT ............................................................................................................................................................ 39
Ordering Information .............................................................................................................................................. 40
General Comments.............................................................................................................................................. 40
Labeling Requirements.................................................................................................................................... 41

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Scope
This document describes key hardware aspects of the Laird SSD50NBT system in
package (SIP) modules providing either SDIO or USB bus interface for WLAN
connection and UART/PCM for Bluetooth connection. This document is intended
to assist device manufacturers and related parties with the integration of this
radio into their host devices. Data in this document is drawn from a number of
sources and includes information found in the Qualcomm Atheros (QCA)
QCA6004 and Cambridge Silicon Radio Ltd. (CSR) CSR8811 A08 data sheets issued
in July 2011, along with other documents provided from QCA and CSR.
The Laird 50-series SIP is currently in development stage and this document is
preliminary. The information in this document is subject to change. Please contact Laird to obtain the most
recent version of this document.
SSD50NBT FEATURES SUMMARY
The Laird SSD50NBT device features are described in Table 1.
Table 1: SSD50NBT features
Feature
Description
Radio Front End
Integrates the complete transmit/receive RF paths including baluns, coexistence band pass filter,
diplexer, switches, power amplifier, low noise amplifier, and reference crystal oscillator.
Enhanced WLAN/BT
Coexistence
Algorithms
Enhanced important use cases including:
PCM/I2S digital audio interface
BT stereo audio (A2DP)
BT data transfer profiles (such as OPP and FTP)
BT2.1+EDR
BT-LE
Flexible radio architecture ensures simple customization for future use cases.
Power Management
Uses power-saving techniques including:
Gating clocks to idle or inactive blocks
Fast start and settling circuits to reduce Tx power
Active duty cycles
CPU frequency scaling
Pre-Calibration
RF system tested and calibrated in production.
Internal Sleep Clock
Integrated on-chip low power sleep clock to regulate internal timing.
Multiple Interface
Support
SDIO 2.0 (50 MHz, 4-bit and 1-bit) or USB for WLAN
HS-UART for Bluetooth HCI (compatible with any upper layer Bluetooth stack)
Advanced 802.11n
Half Guard Interval and Frame Aggregation for high throughput
Space Time Block Coding (STBC) Rx for improved downlink robustness over range
Low Density Parity Check (LDPC) for improved uplink and downlink robustness over range
Reference
Frequency
Incorporates a 26 MHz reference frequency source in package
Sleep regulated and gated to enable the internal crystal to be powered down when the device is in
sleep mode
BT shares the clock from the Wi-Fi chip.
Wi-Fi cannot be turned off or in reset when running BT.

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Feature
Description
Advanced WLAN
Includes the following advanced WLAN features:
IEEE 802.11e QoS, Wi-Fi Alliance
WMM Power Save, and 802.11n
power saving compliance
AES, AES-CCMP, TKIP engines for
faster data encryption
Cisco CCXv4 ASD, WPS support
Standard WEP/WPA/WPA2 for
personal and enterprise environments
support
WWR, 802.11d, 802.11h support
Wi-Fi Direct (Peer-to-Peer)
RTT for indoor positioning
Statistics and events for monitoring
Self-managed power state handling
Self-contained beacon processing
Shared authentication
Ad-hoc power save
Multiple PMK ID support
Simulated UAPSD
T-Spec support
Production flow diagnostics
3-wire scheme for Wi-Fi and BT
coexistence.
Host Offloading
(WLAN)
Integrates extensive hardware signal processing and an embedded on-chip CPU to offload complete
11n MAC/BB/PHY processing to minimize host processor loading and support application specific
customization.
Advanced Bluetooth
High-speed UART port (up to 4 Mbps)
HFP v1.6 wide-band speech supported on-chip
On-chip encoding of SBC and aptX® codecs for A2DP music streaming
PCM/I2S digital audio interface
Support for IEEE 802.11 coexistence
The flexible RAM/ROM based architecture enables custom or future profiles to be easily added.
SPECIFICATIONS
Table 2: Specifications
Feature
Description
Physical Interface
64-pin LGA package
Wi-Fi Interface
1-bit or 4-bit Secure Digital I/O or USB 2.0
Bluetooth Interface
Host Controller Interface (HCI) using High Speed UART
Main Chip
Wi-Fi: Qualcomm Atheros QCA6004.
BT: Cambridge Silicon Radio Ltd. (CSR) CSR8811 A08
Input Voltage Requirements
3.3 VDC (3.20 V min to 3.46V max)
I/O Signaling Voltage
3.3 VDC ± 5% or 1.8 VDC ± 5%
Average Current Consumption,
VDDIO = 3.3 volts
(At maximum transmit power
setting)
Note: Standby refers to the radio
operating in PM1 power saving
mode.
Note: MIMO measurements are
generally higher than Single
Stream.
Single Stream
802.11a (with BT in standby)
@ 18 dBm 6 Mbps
Transmit: 600 mA
Receive: 260 mA
Standby: 130 mA
802.11b (with BT in standby)
@ 18 dBm 1 Mbps
Transmit: 460 mA
Receive: 250 mA
Standby: 130 mA
MIMO
802.11a (with BT in standby)
@ 18 dBm 6 Mbps
Transmit: 900 mA
Receive: 140 mA
Standby: 130 mA
802.11b (with BT in standby)
@ 18 dBm 1 Mbps
Transmit: 680 mA
Receive: 140 mA
Standby: 130 mA

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Feature
Description
802.11g (with BT in standby)
@ 18 dBm 6 Mbps
Transmit: 450 mA
Receive: 250 mA
Standby: 130 mA
802.11n (2.4 GHz) (with BT in standby)
@ 14 dBm MCS7
Transmit: 340 mA
Receive: 250mA
Standby: 130 mA
802.11n (5 GHz) (with BT in standby)
@ 14 dBm MCS7
Transmit: 490 mA
Receive: 260 mA
Standby: 130 mA
Bluetooth (with Wi-Fi in standby)
Transmit: 85 mA
Receive: 70 mA
Standby: 130 mA
802.11g (with BT in standby)
@ 18 dBm 6 Mbps
Transmit: 710 mA
Receive: 140 mA
Standby: 130 mA
802.11n (2.4 GHz) (with BT in standby)
@ 14 dBm MCS7
Transmit: 460 mA
Receive: 140 mA
Standby: 130 mA
802.11n (5 GHz) (with BT in standby)
@ 14 dBm MCS7
Transmit: 720 mA
Receive: 140 mA
Standby: 130 mA
Bluetooth (with Wi-Fi in standby)
Transmit: TBD mA
Receive: TBD mA
Standby: 130 mA
Operating Temperature
-30° to 85°C (-22° to 185°F)
Operating Humidity
10 to 90% (non-condensing)
Storage Temperature
-40° to 85°C (-40° to 185°F)
Storage Humidity
10 to 90% (non-condensing)
Maximum Electrostatic Discharge
Conductive 4KV; Air coupled 8KV
Size
16 mm (length) x 16 mm (width) x 2.5 mm (thickness)
Weight
1.20 g
Mounting
Please see the mounting and handling guide.
Wi-Fi Media
Direct Sequence-Spread Spectrum (DSSS)
Complementary Code Keying (CCK)
Orthogonal Frequency Divisional Multiplexing (OFDM)
Bluetooth Media
Frequency Hopping Spread Spectrum (FHSS)
Wi-Fi Media Access Protocol
Carrier sense multiple access with collision avoidance (CSMA/CA)
Network Architecture Types
Infrastructure and ad-hoc
Wi-Fi Standards
IEEE 802.11a, 802.11b, 802.11d, 802.11e, 802.11g, 802.11h, 802.11i, 802.11n,
802.11r
Bluetooth Standards
Bluetooth version 2.1 with Enhanced Data Rate
Bluetooth 4.0 (Bluetooth Low Energy or BLE)

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Feature
Description
Wi-Fi Data Rates Supported
11a (OFDM) 6, 9, 12, 18, 24, 36, 48, 54 Mbps
802.11b (DSSS, CCK) 1, 2, 5.5, 11 Mbps
802.11g (OFDM) 6, 9, 12, 18, 24, 36, 48, 54 Mbps
802.11n (OFDM, MCS 0-15)
Full Guard Interval: 6.5,13.0, 19.5, 26.0,39.0,52.0,58.5,65.0, 13.0,26.0,39.0, 52.0,
78.0,104.0,117.0 Mbps
Short Guard Interval: 1.2,14.4,21.7,29.9,43.3,57.8,65.0,72.2, 14.4,28.9,43.3,57.8,
86.7,115.6,130.0,144.4 Mbps
Modulation
BPSK @ 1, 6,9, 6.5, 7.2,13 and 14.4 Mbps
QPSK @ 2, 12, 18, 13, 14.4,19.5, 21.7, 26, 28.9, 39,43.3 Mbps
CCK @ 5.5 and 11 Mbps
16-QAM @ 24, 36,26, 29.9,39,43.3,52,57.8,78,86.7 Mbps
64-QAM @ 48,54,52, 57.8, 58.5, 65,72.2,104.0,115.6,117.0,130.0,144.4 Mbps
802.11n Spatial Streams
2 (2x2 MIMO)
Bluetooth Data Rates Supported
1, 2, 3 Mbps
Bluetooth Modulation
GFSK@ 1 Mbps
Pi/4-DQPSK@ 2 Mbps
8-DPSK@ 3 Mbps
Regulatory Domain Support
FCC (Americas, Parts of Asia, and Middle East)
ETSI (Europe, Middle East, Africa, and Parts of Asia)
IC (Industry Canada )
MIC (Japan) (formerly TELEC) –Option
KC (Korea) (formerly KCC) –Option
2.4 GHz Frequency Bands
ETSI: 2.4 GHz to 2.483 GHz
FCC: 2.4 GHz to 2.473 GHz
MIC: 2.4 GHz to 2.495 GHz
KC: 2.4 GHz to 2.483 GHz
2.4 GHz Operating Channels
(Wi-Fi)
ETSI: 13 (3 non-overlapping)
FCC: 11 (3 non-overlapping)
MIC: 14 (4 non-overlapping)
KC: 13 (3 non-overlapping)

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Feature
Description
5 GHz Frequency Bands
ETSI
5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64)
5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124/128/132/136/140)
FCC
5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64)
5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124/128/132/136/140
5.725 GHz to 5.825 GHz(Ch 149/153/157/161/165)
MIC (Japan)
5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64)
5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124/128/132/136/140)
KC
5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64)
5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124)
5.725 GHz to 5.825 GHz (Ch 149/153/157/161)
5 GHz Operating Channels
(Wi-Fi)
ETSI: 19 non-overlapping
FCC: 24 non-overlapping
MIC: (Japan): 19 non-overlapping
KC: 19 non-overlapping
Transmit Power
Note: Transmit power on each
channels varies according to
individual country regulations. All
values for lowest data rate is
nominal, +/-2 dBm.
Others are +/-2.5dBm.
Note:
HT40 –40 Mhz-wide channels
HT20 –20 MHz-wide channels
802.11a
6 Mbps
18 dBm (63 mW)
54 Mbps
15 dBm (32 mW)
802.11b
1 Mbps
18 dBm (63 mW)
11 Mbps
18 dBm (63 mW)
802.11g
6 Mbps
18 dBm (63 mW)
54 Mbps
15 dBm (32 mW)
802.11n (2.4 GHz)
6.5 Mbps (MCS0)
18 dBm (63 mW)
65 Mbps (MCS7)
14 dBm (25 mW)
802.11n (5 GHz)
6.5 Mbps (MCS0;HT20)
18 dBm (63 mW)
65 Mbps (MCS7;HT20)
(MCS0;HT40)
(MCS7; HT40)
14 dBm (25 mW)
15 dBm (32 mW)
12 dBm (16 mW)
Bluetooth
1 Mbps
6 dBm (4 mW)
2 Mbps
6 dBm (4 mW)
3 Mbps
3 dBm (2 mW)

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Feature
Description
Typical Receiver Sensitivity
Note: All values nominal, +/-3 dBm.
802.11a:
6 Mbps
-93 dBm
54 Mbps
-75 dBm (PER <= 10%)
802.11b:
1 Mbps
-95 dBm
11 Mbps
-88 dBm (PER <= 10%)
802.11g:
6 Mbps
-92 dBm
54 Mbps
-75 dBm (PER <= 10%)
802.11n (2.4 GHz)
MCS0 Mbps
-92 dBm
MCS7 Mbps
-72 dBm
802.11n (5 GHz)
MCS0 Mbps
MCS7 Mbps
-93 dBm
-72 dBm
Bluetooth:
1 Mbps
-84 dBm
(1DH1)
3 Mbps
-76 dBm
(3DH5)
BLE
-87 dBm
Operating Systems Supported
Windows Mobile 5.0, 6.0, 6.1, 6.5
Windows Embedded Compact (CE) 5.0, 6.0, 7.0, 2013
Windows 7, 8, 8.1
Linux 2.6.x, 3.x.x, 4.0.x kernel
Android 4.1.2 (Jellybean) and forward
Security
Standards
Wireless Equivalent Privacy (WEP)
Wi-Fi Protected Access (WPA)
IEEE 802.11i (WPA2)
Encryption
Wireless Equivalent Privacy (WEP, RC4 Algorithm)
Temporal Key Integrity Protocol (TKIP, RC4 Algorithm)
Advanced Encryption Standard (AES, Rijndael Algorithm)
Encryption Key Provisioning
Static (40-bit and 128-bit lengths)
Pre-Shared (PSK)
Dynamic
802.1X Extensible Authentication Protocol Types
EAP-FAST
EAP-TLS
EAP-TTLS
PEAP-GTC
PEAP-MSCHAPv2
PEAP-TLS
LEAP

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Feature
Description
Compliance
ETSI Regulatory Domain
EN 300 328 (Wi-Fi®)
EN 300 328 v1.8.1 (BT 2.1)
EN 301 489-1
EN 301 489-17
EN 301 893
EN 60950-1
EU 2002/95/EC (RoHS)
FCC Regulatory Domain
FCC 15.247 DTS –802.11b/g (Wi-Fi) –2.4 GHz
FCC 15.407 UNII –802.11a (Wi-Fi) –5 GHz
FCC 15.247 DSS –BT 2.1
Industry Canada
RSS-247 –802.11a/b/g/n (Wi-Fi) –2.4 GHz, 5.8 GHz, 5.2 GHz, and 5.4 GHz
RSS-247 –BT 2.1
Certifications
Wi-Fi Alliance
802.11a, 802.11b, 802.11g , 802.11n
WPA Enterprise
WPA2 Enterprise
Cisco Compatible Extensions (Version 4)
Bluetooth SIG Qualification
Warranty
Five Year Limited Lifetime
All specifications are subject to change without notice
WLAN FUNCTIONAL DESCRIPTION
Overview
The SSD50NBT WLAN block is based on the Qualcomm-Atheros AR6004 802.11a/b/g/n chipset. It is optimized
for low power embedded applications and is configured to operate in dual-band, two-stream (2x2 MIMO) mode.
Its functionality includes:
Improved throughput on the link due to frame aggregation, RIFS (reduced inter-frame spacing), and half
guard intervals.
Support for STBC (space time block codes) and LDPC (Low Density Parity Check) codes.
Improved 11n performance due to features such as 11n frame aggregation (A-MPDU and A-MSDU) and
low-overhead host-assisted buffering (RX A-MSDU and RX A-MPDU). These techniques can improve
performance and efficiency of applications involving large bulk data transfers such as file transfers or high-
resolution video streaming.
Other functionality includes the following:

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Feature
Description
Reset Control
WLAN_PWD_L and BT_PWD_L pins must be asserted low to reset Wi-Fi and Bluetooth. After these
signals are de-asserted, the radio waits for host communication. Until then, all modules except the
host interface are held in reset.
Once the host has initiated communication, the radio turns on its crystal and then the PLL. After all
clocks are stable and running, the block resets are automatically de-asserted.
Note: Because it derives its clock from WLAN, the Bluetooth function should be powered down/reset
whenever WLAN is reset.
Reset Sequence
After a COLD_RESET event, the SSD50NBT enters the HOST_OFF state and awaits communication from
the host. From that point, the typical COLD_RESET sequence is shown below:
When the host is ready to use the radio, it initiates communication via the SDIO.
The radio enters the WAKEUP state and then the ON state. Embedded software configures the
radio functions and interfaces. When the radio is ready to receive commands from the host, it
sets an internal function ready bit.
The host reads the ready bit and sends function commands to the radio.
The embedded CPU may continue to be held in reset under some circumstances until its reset is
cleared by an external pin or when the host clears a register.
Power Transition
Integrated power management and control functions and low power operation for maximum battery
life across all operational states by:
Gating clocks for logic when not needed
Shutting down unneeded high speed clock sources
Reducing voltage levels to specific blocks in some states
See Error! Reference source not found..
Figure 1: Power state transition

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Feature
Description
Hardware Power
States
The SSD50NBT hardware has five top level hardware power states managed by the RTC block.
State
Description
OFF
CHIP_PWD_L pin assertion immediately brings the chip to the OFF state.
Sleep clock is disabled.
No state is preserved.
HOST_OFF
WLAN is turned off. The Bluetooth clock is off but should also be powered
down through BT_PWD_L.
Only the host interface is powered on. The rest of the chip is power gated
(off).
The host instructs the SSD50NBT to transition to WAKEUP by writing a register
in the host interface domain.
The embedded CPU and WLAN do not retain state (separate entry).
For USB, this state can be bypassed by asserting FORCE_HOST_ON_L during
CHIP_PWD_L de-assertion.
SLEEP
Only the sleep clock is operating.
The crystal or oscillator is disabled.
Any wakeup events force a transition from this state to the WAKEUP state.
All internal states are maintained.
WAKEUP
The system transitions from sleep states to ON.
The high frequency clock is gated off as the crystal or oscillator is brought up
and the PLL is enabled.
WAKEUP duration is programmable.
ON
The high speed clock is operational and sent to each block enabled by the
clock control register.
Lower level clock gating is implemented at the block level, including the CPU,
which can be gated off using the WAITI instruction while the System is on.
No CPU, host, and WLAN activities transition to sleep states. WLAN must be
initialized prior to Bluetooth initialization and use.
Sleep State
Management
Sleep state minimizes power consumption while saving system states. In sleep state, all high speed
clocks are gated off and the external reference clock source is powered off.
The system remains in sleep state until a WAKEUP event causes the system to enter WAKEUP state,
waits for the reference clock source to stabilize, and then un-gates all enabled clock trees. The
embedded CPU wakes up only when an interrupt arrives, which may have also generated the system
WAKEUP event.

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Feature
Description
System Clocking
(RTC Block)
The SSD50NBT has an RTC block which controls the clocks and power going to other internal modules.
Its inputs consist of sleep requests from these modules and its outputs consists of clock enable and
power signals which are used to gate the clocks going to these modules. The RTC block also manages
esets goig to othe odules ith the deie. The ““DNBT’s lokig is gouped ito to tpes:
high-speed and low-speed.
High Speed Clocking
The reference 26 MHz clock source inside the SSD50NBT drives the PLL and RF synthesizer of Wi-Fi and
Bluetooth. To minimize power consumption, the reference clock source is powered off in SLEEP,
HOST_OFF, and OFF states.
Low Speed Clocking
On WiFi operation, SSD50NBT do not need an external sleep clock source. Instead, an internal ring
oscillator is used to generate a low frequency sleep clock. It is also used to run the state machines and
counters related to low power states. The SSD50NBT has an internal calibration module which
produces a 32.768 KHz output with minimal variation. For this, it uses the reference clock source as
the golden clock. As a result, the calibration module adjusts for process and temperature variations in
the ring oscillator when the system is in ON state.
The BT section sharing clock from wifi chip. It will not able to get into deep sleep mode without 32KHz
present at pin-24. Without get into deep sleep mode, it will consume 3.3mA at VDD_BT supply. In
order to have BT get into deep sleep mode, a 32.768KHz slow clock is must on pin-24. When
32.768KHz present on pin-24, BT chip can go into deep sleep mode with 0.08mA current consume on
VDD_BT supply.
Interface Clock
The host interface clock represents another clock domain for the SSD50NBT. This clock comes from the
SDIO and is independent from the other internal clocks. It drives the host interface logic as well as
certain registers which can be accessed by the host in HOST_OFF and SLEEP states.
MAC/BB/RF Block
The SSD50NBT Wireless MAC consists of five major blocks:
Host interface unit (HIU) for bridging to the AHB for bulk data accesses and APB for register
accesses
Ten queue control units (QCU) for transferring TX data
Ten DCF control units (DCU) for managing channel access
Protocol control unit (PCU) for interfacing to baseband
DMA receive unit (DRU) for transferring RX data
Baseband Block
The SSD50NBT baseband module (BB) is the physical layer controller for the 802.11b/g/n air interface.
It is responsible for modulating data packets in the transmit direction and detecting and demodulating
data packets in the receive direction. It has a direct control interface to the radio to enable hardware
to adjust analog gains and modes dynamically.
Clock Sharing
Clock sharing is implemented on the SSD50NBT. The Bluetooth chip (CSR8811) receives a reference
clock from Wi-Fi chip (QCA6004). When Wi-Fi is in power off/reset state, Bluetooth is also off.
32.768KHz slow clock is needed for BT to get into deep sleep mode.

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BLUETOOTH FUNCTIONAL DESCRIPTION
The SSD50NBT Bluetooth (BT) block is based on CSR8811A08 and described in the table below:
Table 3: Bluetooth functions
Feature
Description
HCI-UART Interface
The UART Interface is a standard high-speed UART interface. It operates up to 4 Mbps,
supporting Bluetooth HCI UART interface.
PCM or I2S Interface
Continuous PCM encoded audio data transmission and reception over Bluetooth.
Processor overhead reduction through hardware support for continual transmission and
reception of PCM data.
A bidirectional digital audio interface that routes directly into the baseband layer of the
firmware. It does not pass through the HCI protocol layer.
Hardware on CSR8811 for sending data to and from a SCO connection.
Up to three SCO connections on the PCM interface at any one time.
PCM interface master, generating PCM_SYNC and PCM_CLK.
PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK.
Various clock formats including:
*Long Frame Sync
*Short Frame Sync
GCI timing environments
13-bit or 16-bit linear, 8-it μ-law or A-law companded sample formats.
Receives and transmits on any selection of three of the first four slots following
PCM_SYNC.
The PCM configuration options are enabled by setting SKEY_PCM_CONFIG32.
CPU and Memory
The CSR8811 uses a 16-bit RISC MCU for low power consumption and efficient use of memory.
The MCU, interrupt controller, and event timer run the Bluetooth software stack and control
the Bluetooth radio and host interfaces.
56 KB of on-chip RAM is provided to support the RISC MCU and is shared between the ring
buffers used to hold voice/data for each active connection and the general-purpose memory
required by the Bluetooth stack.
5 Mb of Internal ROM memory is available on the CSR8811. This memory is provided for system
firmware, storing CSR8811 settings and program code.
Build-in Standard WLAN
Coexistence
The SSD50NBT supports internally the standard WLAN coexistence interface through the
WLAN_ACTIVE, BT_PRIORITY, and BT_ACTIVE pins.
Reference Clock
The BT block is configured for 26 MHz reference clock frequency. The clock source is provided to
BT internally from the WLAN block on demand from BT_CLK_REQ.
Note: The WLAN block must be initialized prior before BT clock sharing is enabled.
BT Low Energy
The SSD50NBT supports Low Energy specification which allows for connection to devices with
single mode LE function (such as a watch, sensor, and HID). The implementation is optimized for
coexistence with WLAN.
Reset
The pin BT_PWD_L resets and powers down the BT block.
Holding the BT_PWD_L pin at GND turns off the entire BT block; all state information is lost. To
ensure a full reset, the reset signal should be asserted for a period greater than
5 ms.

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Feature
Description
Radio
The BT radio shares the single antenna port with the WLAN through an internal 3-way RF
switch. The SSD50NBT implements WLAN/BT coexistence internally.
VDDIO is to set the I/O voltage internally with either 1.8 V or 3.3 V to ensure same voltage level
for the internal Wi-Fi and BT coexistence signal. Refer to the reference design specifications for
details.
BT wake up Host
PIO-3 is reserved for BT to wake host from deep sleep mode.
SDIO_IOVDD
WLAN Host IO (SDIO) power supply input 1.8V or 3.3V.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 4 summarizes the absolute maximum ratings and Table 5 lists the recommended operating conditions for
the SSD50NBT. Absolute maximum ratings are those values beyond which damage to the device can occur.
Functional operation under these conditions, or at any other condition beyond those indicated in the
operational sections of this document, is not recommended.
Note: Maximum rating for signals follows the supply domain of the signals.
Table 4: Absolute Maximum Ratings
Symbol (Domain)
Parameter
Max Rating
Unit
SDIO_IOVDD
WLAN host SDIO interface I/O supply
-0.3 to 4.0
V
VDDIO (Wi-Fi and BT)
WLAN and BT I/O configuration power supply
-0.3 to 4.0
V
VDD33;VDD33_FEM
External 3.3V power supply
-0.3 to 4.0
V
BT_VDD
BT Power core supply
3.6
V
VDD12_USB, DVDD12,
AVDD12
WLAN 1.2V power supply
-0.3 to 1.32
V
Storage
Storage Temperature
-40 to +85
°C
ANT1; ANT2
Maximum RF input (reference to 50-Ωinput)
+10
dBm
ESD
Electrostatic discharge tolerance
2000
V
Recommended Operating Conditions
Table 5: Recommended Operating Conditions
Symbol (Domain)
Parameter
Min
Typ
Max
Unit
SDIO_IOVDD
WLAN host interface I/O supply
1.71/3.2
1.8/3.3
1.89/3.46
V
VDDIO (Wi-Fi and BT)
WLAN and BT GPIO I/O power
supply
1.71/3.2
1.8/3.3
1.89/3.46
V
VDD33
External 3.3V power supply
3.2
3.30
3.46
V
BT_VDD
BT core supply
3.2
3.30
3.46
V
VDD12_USB, DVDD12,
AVDD12
WLAN 1.2V power supply
1.20
1.26
1.32
V
T-ambient
Ambient temperature
-30
25
85
°C

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DC Electrical Characteristics
Table 6 and Table 7 list the general DC electrical characteristics over recommended operating conditions (unless
otherwise specified).
Table 6: General DC Electrical Characteristics (For 3.3V I/O Operation)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High Level Input Voltage
0.7 x VDD
V
VIL
Low Level Input Voltage
0.3 x VDD
V
IIL
Input
Leakage
Current
Without Pull-
up or Pull-
down
0V < VIN < VDD
0V < VOUT< VDD
0
-3
nA
With Pull-up
0 V < VIN < VDD
0V < VOUT < VDD
16
48
µA
With Pull-down
0V < VIN < VDD
0V < VOUT < VDD
-14
-47
µA
VOH
High Level Output Voltage
IOH = -4mA
0.9 x VDD
V
IOH = -12mA
0.9 x VDD
V
VOL
Low Level Output Voltage
IOH = 4mA
0.1 x VDD
V
IOH = 12mA
0.1 x VDD
V
Table 7: General DC Electrical Characteristics (For 1.8V I/O Operation)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High Level Input Voltage
0.7 x VDD
V
VIL
Low Level Input Voltage
0.3 x VDD
V
IIL
Input
Leakage
Current
Without Pull-up
or Pull-down
0V < VIN < VDD
0V < VOUT < VDD
0
-3
nA
With Pull-up
0V < VIN < VDD
0V < VOUT < VDD
3.5
13
µA
With Pull-down
0V < VIN < VDD
0V < VOUT < VDD
-6.2
-23
µA
VOH
High Level Output Voltage
IOH = -4mA
0.9 x VDD
V
IOH = -12mA
0.9 x VDD
V
VOL
Low Level Output Voltage
IOH = 4mA
0.1 x VDD
V
IOH = 12mA
0.1 x VDD
V

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Figure 2: Power On/Off Timing
Figure 3: Wi-Fi and BT reset Timing

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Table 8: Timing Diagram Definitions
Timing
Description
Min
Unit
Ta
Time between 3.3V (VDD33/BT_VDD/VDD_FEM/VDD_USB) and
VDDIO/SDIO_IOVDD supplies
0
µsec
Tb
Time between VDDIO/SDIO_IOVDD supplies valid and WLAN_PWD_L
negation.
Note: there are 10K ohm internal Pull-up on SD_D0, SD_D1 and SD_D3.
5
µsec
Tc
Time between VDDIO/SDIO_IOVDD supplies valid and
BT_PWD_L negation
5
msec
Td
Time between WLAN_PWD_L assertion and VDDIO/SDIO_IOVDD invalid, or
time between BT_PWD_L negation and VDDIO/SDIO_IOVDD invalid.
0
µsec
Te
Time between VDDIO/SDIO_IOVDD invalid and 3.3V
(VDD33/BT_VDD/VDD_FEM/VDD_USB) invalid.
No requirement
Tf
Time of WLAN_PWD_L assertion during reset or power down period. Both
3.3V (VDD33/BT_VDD/VDD_FEM/VDD_USB) and VDDIO/SDIO_IOVDD should
keep ON.
5
µsec
Tg
Time of BT_PWD_L assertion during reset or power down period. Both 3.3V
(VDD33/BT_VDD/VDD_FEM/VDD_USB) and VDDIO/SDIO_IOVDD should keep
ON.
5
msec
Important: SSD50NBT requires SDIO interface lines SD_CMD, SD_D1, and SD_D2 to be high prior to negation
of WLAN_PWD_L. Designs should drive these lines high or, if necessary, add external pull-ups to
insure proper SDIO configuration on WLAN boot-up. Failure to pull these lines high results in non-
functional SDIO interface. These are boot-mode straps interpreted by the WLAN CPU on power-
on. There is 10K ohm pull high resistor already implemented on SD_D0, SD_D1, and SD_D3. No
external pull-up is required for those three lines.
We suggest that Tb and Tf timing is greater than 5µsec but no longer than 100 msec.
WLAN Radio Receiver Characteristics
Table 9 and Table 10 summarize the WLAN SSD50NBT receiver characteristics.
Table 9: WLAN Receiver Characteristics for 2.4 GHz Signal Chain Operation
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Frx
Receive input frequency range
2.412
2.484
GHz
Srf
Sensitivity
CCK, 1 Mbps
See Note3
-95
dBm
CCK, 11 Mbps
-88
OFDM, 6 Mbps
-92
OFDM, 54 Mbps
-75
HT20, MCS0
-92
HT20, MCS7
-72
Radj
Adjacent channel rejection
OFDM, 6 Mbps
See Note4
32
dB

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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
OFDM, 54 Mbps
16
HT20, MCS0
31
HT20, MCS7
14
3Performance data are measured under signal chain operation.
4Performance data are measured under signal chain operation.
Table 10: WLAN Receiver Characteristics for 5 GHz Dual Chain Operation
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Frx
Receive input frequency
range
5.15
5.825
GHz
Srf
Sensitivity
OFDM, 6 Mbps
See Note5
-93
dBm
OFDM, 54 Mbps
-75
HT20, MCS0
-93
HT20, MCS7
-72
HT40, MCS0
-87
HT40, MCS7
-67
Radj
Adjacent channel rejection
OFDM, 6 Mbps
See Note6
22
dB
OFDM, 54 Mbps
9
HT20, MCS0
20
HT20, MCS7
19
5Performance data are measured under dual chain operation.
6Performance data are measured under dual chain operation.
WLAN Transmitter Characteristics
Table 11: WLAN Transmitter Characteristics for 2.4 GHz Per Chain Operation
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ftx
Transmit output frequency range
2.412
2.484
GHz
Pout
Output power
See Note7
11b mask compliant
1Mbps
18
dBm
11g mask compliant
6Mbps
18
11g EVM compliant
54Mbps
15
11n HT20 mask compliant
MCS0
18
11n HT20 EVM compliant
MCS7
14
11n HT20 EVM compliant
MCS15
14
ATx
Transmit power accuracy at 18 dBm
-
-
+ 2.0
dB

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Freq.
Mode/Rate (Mbps)
Output Power Per
Chain (dBm)
Typical Current
Consumption Single
Chain (mA)8
Max. Current
Consumption Single
Chain (mA)8
2412MHz
1 Mbps
18dBm
420
560
54 Mbps
15dBm
350
450
HT20 MCS7
14dBm
340
420
2442MHz
1 Mbps
18dBm
420
560
54 Mbps
15dBm
350
450
HT20 MCS7
14dBm
340
420
2472MHz
1 Mbps
18dBm
420
560
54 Mbps
15dBm
350
450
HT20 MCS7
14dBm
340
420
Table 12: WLAN Transmitter Characteristics for 5 GHz Per Chain Operation
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ftx
Transmit output frequency range
5.15
5.925
GHz
Pout
Output power
See Note3
11a mask compliant
6Mbps
18
dBm
11a EVM compliant
54Mbps
15
11n HT20 mask compliant
MCS0
18
11n HT20 EVM compliant
MCS7
14
11n HT20 EVM compliant
MCS15
14
11n HT40 mask compliant
MCS0
15
11n HT40 EVM compliant
MCS7
12
11n HT40 EVM compliant
MCS15
12
ATx
Transmit power accuracy at 18dBm
-
-
+ 2.0
dB
Freq.
Mode/Rate
[Mbps]
Output Power Per
Chain [dBm]
Typical Current
Consumption Single
Chain (mA)8
Max. Current
Consumption Single
Chain (mA)8
5180MHz
54 Mbps
15 dBm
490
590
HT20 MCS7
14 dBm
450
560
HT40 MCS7
12 dBm
470
540
5500MHz
54 Mbps
15 dBm
490
590
HT20 MCS7
14 dBm
450
560
HT40 MCS7
12 dBm
470
540
5825MHz
54 Mbps
15 dBm
490
590
HT20 MCS7
14 dBm
450
560
HT40 MCS7
12 dBm
470
540
7Performance data are measured under single chain operation.
Note: Final TX power values on each channels are limited by the regulatory certification test limit.