Lattice Semiconductor LatticeXP2 User manual

June 2010
Revision: EB53_01.1

LatticeXP2 Brevia Development Kit

User’s Guide
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
Introduction
Thank you for choosing the Lattice Semiconductor LatticeXP2™ Brevia Development Kit!
This user’s guide describes how to start using the LatticeXP2 Brevia Development Kit, an easy-to-use platform for
evaluating and designing with LatticeXP2 FPGAs. Along with the evaluation board and accessories, this kit
includes a pre-loaded Brevia System-on-Chip (SoC) demonstration design based on the LatticeMico8™ microcon-
troller.
Note: Static electricity can severely shorten the life span of electronic components.
Features
The LatticeXP2 Brevia Development Kit includes:
•LatticeXP2 Brevia Evaluation Board – This is a small board (about the size of a business card) with the follow-
ing on-board components and circuits:
– LatticeXP2-5E 6TN144C
– 2-Mbit SPI Flash memory
– 128K by 8-bit SRAM
– RS232 DB9 connector
– 2x20 expansion header for general I/O
– 2x5 expansion header for general I/O
– Four general purpose pushbuttons
– One reset pushbutton
– 4-bit DIP switch
– Eight status LEDs
•Pre-loaded Demo – The kit includes a pre-loaded demo design that integrates several Lattice reference designs
including the LatticeMico8 microcontroller, SRAM controller, SPI Flash memory controller, and a UART periph-
eral.
• One RS232 DB9
•One Parallel Port Download Cable – The parallel port download cable permits reconfiguration of the FPGA. It
also permits the use of the Reveal™ analysis tool. See Table 10 on page 17 for connection information.
• One International 6V DC Power Supply
•QuickSTART Guide – Provides information on connecting the LatticeXP2 Brevia Evaluation Board and running
the demo.
•LatticeXP2 Brevia Development Kit Web Page — The LatticeXP2 Brevia Development Kit web page on the
Lattice web site provides access to the latest documentation, demo designs and drivers for the kit.
The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of
the evaluation board, descriptions of the on-board connectors, switches and a complete set of schematics of the
LatticeXP2 Brevia Evaluation Board.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
Figure 1. LatticeXP2 Brevia Evaluation Board, Top Side
RS232
Power
LED
Power
Connector
3.5”
2”
2.5V Expansion
Header
JTAG Header20x20 Expansion Header
Status
LEDs
Push
Buttons
DIP
Switches
RESET
Button
LatticeXP2 Device
This board features a LatticeXP2 FPGA with a 1.2V core supply. It can accommodate all pin-compatible LatticeXP2
devices in the 144-pin TQFP (20x20 mm) package. A complete description of this device can be found in the
LatticeXP2 Family Data Sheet.
Demonstration Design
Lattice provides a demo that illustrates key applications of the LatticeXP2 device.
Demo_LatticeXP2_Brevia_SoC
The Demo_LatticeXP2_Brevia_SoC is pre-programmed into the non-volatile Flash memory of the LatticeXP2
FPGA and is operational upon power-up. The design provides the following features:
• Prints the ASCII representation of any characters received by the UART on the eight LEDS (D0-D7).
• Prints the SPI memory ID code on demand.
• Displays the current DIP switch setting on demand.
• Logs Read ID and Read Switch commands, along with their results, into the asynchronous SRAM.
• Stores the contents of the SRAM into the SPI ROM on demand.
• Restores the SRAM contents from the SPI ROM on demand.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
The demo design integrates the following Lattice reference designs:
• LatticeMico8 Microcontroller (RD1026)
•WISHBONE UART (RD1042)
• SPI WISHBONE Controller (RD1044)
• LatticeMico8 to WISHBONE Interface Adapter (RD1043)
Firmware running on the LatticeMico8 demonstrates control logic for the peripherals connected to a shared on-chip
WISHBONE bus and communication between the LatticeXP2 Brevia Evaluation Board and a host PC connected to
the RS232 cable.
Figure 2. Demo_LatticeXP2_Brevia_SoC Block Diagram
LatticeXP2 Brevia Evaluation Board
LED Bank
UART
SPI SRAM
RS-232
PC Host
SPI Memory
Controller
SRAM Memory
Controller
SPI 2-Mbit
Flash Memory
SRAM 1-Mbit
Memory
LatticeMico8
WISHBONE Bus
Switch Bank
LatticeXP2 FPGA
Set Up a VT100/ANSI Terminal Emulator
The Demo_LatticeXP2_Brevia_SoC preloaded in the LatticeXP2 Brevia Evaluation Board is operated by interact-
ing with a monitor program. The monitor program sends and receives data across the RS232 communications port
on the LatticeXP2 Brevia Evaluation Board. It is necessary to start and configure a VT100 or ANSI style terminal
emulator program like HyperTerminal (Windows) or Minicom (Linux).
The RS232 port on the LatticeXP2 Brevia Evaluation Board is configured to operate at 115.2Kbps, 8 data bits, 1
stop bit, and no parity, and no flow control. Once the terminal emulator is running on the host computer, and the
RS232 cable is attached between the host computer and the LatticeXP2 Brevia Evaluation Board you will see the
following banner displayed when the board is powered, or following a RESET button assertion.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
=========================================================================
Welcome to the LatticeXP2 Brevia Development Kit
SoC Demonstration Rev 1.0, April 2010
Main Menu
------------------------------------------------------------
0: Re-display Main Menu
1: Read SPI Flash Memory IDCode
2: Read DIP Switch Bank
3: Read Data History from SRAM
4: Copy Data History from SRAM to SPI Flash Memory
5: Read Data History from SPI Flash Memory
6: Write Data to SRAM (Specified Address and Data)
7: Read Data from SRAM (Specified Address)
8: Write Data to SPI (Specified Address and Data)
9: Read Data from SPI (Specified Address)
a: SRAM Auto-Test
b: SPI Auto-Test
Press 0-b to select an option.
=========================================================================
SoC Command Monitor Features
The LatticeXP2 Brevia Evaluation Board, after it powers up or is reset, begins running a command interpreter mon-
itor under the control of the LatticeMico8 microcontroller. The monitor code waits for a keypress and immediately
performs the requested function.
When the Read ID and Read Switch Bank commands are executed the ASCII output from the command is stored
into the SRAM. The LatticeMico8 stores the next address to write in three of its general purpose registers. After
power up the registers are cleared to 0x000000. Commands that have their results logged to the SRAM print out
the address of the next available SRAM location.
Read SPI Flash Memory IDCode Command
The SPI ROM device on the LatticeXP2 Brevia Evaluation Board can be queried and will return the ID code imple-
mented by the ROM manufacturer. The LatticeMico8 initiates memory transactions using the SPI Memory control-
ler to acquire the data.
To scan the SPI Flash Memory IDCode:
1. From the terminal Main Menu, press 1.
The LatticeMico8 performs the manufacturer specific SPI memory transactions to acquire the ID code. The ID
number is returned as a hex value. This command logs the result to the SRAM.
Example:
ID:0x44
(SRAM ADDR:0x00006)
Note: The ID for your board may differ.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
Read DIP Switch Bank
The LatticeMico8 has the ability to read the state of switches 1-4 on the DIP switch bank. The pushbutton switches
are can also be read. Each pushbutton press toggles the internal state of a register in the FPGA. The current state
of the register is displayed on the high nibble of the output. The hexadecimal representation of the switches is
printed and logged to the SRAM. A DIP switch that is set ON has a '0' value, and one that is OFF has a value of '1'.
To read the DIP switch:
1. From the terminal window press 2.
Example:
SW:0x00
(SRAM ADDR:0x0000C)
Read Data History from SRAM
Use the Read Data History from SRAM command to see the results from each command that is logged to the
SRAM memory. The output from this command does not get written into the SRAM.
To read data history from SRAM:
1. From the terminal window press 3. The transaction log is listed.
Example:
SRAM:
0x44
0x00
Copy Data History from SRAM to SPI Flash Memory
This command erases a portion of the SPI ROM, and stores the command results logged in the SRAM. The
LatticeMico8 starts writing from SRAM address 0x000000 and continues writing values into the SPI ROM until it
reaches the last valid entry in the SRAM.
To copy data history from SRAM to SPI Flash memory:
1. From the terminal window press 4. The data log is transferred and the terminal indicates “Done”.
Example:
SRAM => SPI:
0x44
0x00
Done.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
Read Data History From SPI Flash Memory
This command copies the Data History from the SPI ROM into the SRAM. After power is supplied, or RESET
asserted the SRAM Data History log information is no longer available. Running this command permits the history
to be restored from the non-volatile SPI ROM.
To read data history from the SPI ROM into SRAM:
1. From the terminal window press 5. The transaction log is listed.
Example:
SPI Flash:
0x44
0x00
Write Data to SRAM (Specified Address and Data)
This command allows you to write a single data value to any location in the SRAM memory space.
1. From the terminal window press 6.

Example:

Please Enter the Address(17 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:
10000
Please Enter the Data(8 bits,Hex), eg: b7, no Spaces, then Press ENTER:
93
SRAM Write Done.
Read Data from SRAM (Specified Address)
This command allows you to read the data value from any address in the SRAM.
1. From the terminal window press 7.

Example:

Please Enter the Address(17 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:
10000
Read Data: 93
SRAM Read Done.
Write Data to SPI (Specified Address and Data)
This command allows you to write a single data value to any location in the SPI memory space.
1. From the terminal window press 8.

Example:

Please Enter the Address(18 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:
10000
Please Enter the Data(8 bits,Hex), eg: b7, no Spaces, then Press ENTER:
93
SPI Write Done.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
Read Data from SPI (Specified Address)
This command allows you to read the data value from any address in the SPI.
1. From the terminal window press 9.

Example:

Please Enter the Address(18 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:
10000
Read Data: 93
SPI Read Done.
Perform SRAM Auto-test
This command automatically tests SRAM.
1. From the terminal window press a.

Example:

> a
Starting SRAM Auto-Test.........................................................
.......................................................................
SRAM Test Done: Successful.
Perform SPI Auto-test
This command automatically tests SPI.
1. From the terminal window press b.

Example:

>b
Starting SPI Auto-Test..........................................................
......................................................................
SPI Test Done: Successful.
Download Demo Designs
Lattice distributes source and programming files for a variety of demonstration designs compatible with the
LatticeXP2 Brevia Evaluation Board.
To download demo designs:
1. Browse to the LatticeXP2 Brevia Development Kit web page of the Lattice web site. Select the Demo Applica-
tions download and save the file.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
2. Extract the contents of Demo_LatticeXP2_Brevia_Soc_vhdl.zip and
Demo_LatticeXP2_Brevia_Soc_verilog.zip to an accessible location on your hard drive. One or more
designs will be extracted and each will follow the following basic form.
Demo Directories
Demo1 Demo1
.\project
.\source
.\LatticeMico8_Vx_y_Verilog
.\RD1042
.\project
.\source
.\RD1043
.\project
.\source
.\RD1044
.\project
.\source
.\RD1046
.\project
.\source
Where:
•\project – ispLEVER project (.syn), preferences (.lpf), and programming file (.jed). This directory may contain
intermediate results of the ispLEVER build process.
•\source – HDL source for the ispLEVER project.
•.\LatticeMico8_Vx_y_Verilog – LatticeMico8 Microcontroller Reference Design (RD1026).
• .\RDxxxx – Reference Designs integrated by the demo.
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LatticeXP2 Brevia Development Kit
Lattice Semiconductor User’s Guide
Programming Demo Design with ispVM
Demo_LatticeXP2_Brevia_SoC is pre-programmed into the LatticeXP2 Brevia Evaluation Board by Lattice. To
restore a LatticeXP2 Brevia Evaluation Board to factory settings, use the procedure described in this section.
To program a demo programming file:
1. Power off the LatticeXP2 Brevia Evaluation Board.
2. Connect the Parallel Port download cable to the PC
3. Connect opposite end of the Parallel Port download cable as shown in Table 9, leaving Pin 2 unconnected.
4. Apply power to the LatticeXP2 Brevia Evaluation Board.
5. Attach the download cable to Pin 2.
6. From the Start menu run ispVM System.
7. Choose Options > Cable and IO Port Setup... in order to configure the download cable.
8. Click Auto Detect. ispVM will detect Cable Type Lattice and Port Setting 0x0378.
9. Click OK.
10. Choose ispTools > Scan Chain. The New Scan Configuration Setup window appears. The LatticeXP2
appears in the device list as LFXP2-5E.
11. Right-click the LFXP2-5E entry and choose Edit Device... The Device Information dialog appears.
12. From the Data File section, click the Browse button. The Open Data File dialog appears.
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