Nuvoton NuMicro Family Product manual

Mini57
Apr. 06, 2017 Page 1 of 475 Rev.1.00
MINI57 SERIES TECHNICAL REFERENCE MANUAL
ARM Cortex®-M0
32-bit Microcontroller
NuMicro®Family
Mini57 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
1GENERAL DESCRIPTION...............................................................................12
2FEATURES ......................................................................................................13
3ABBREVIATIONS............................................................................................17
4PARTS INFORMATION LIST AND PIN CONFIGURATION............................18
4.1 NuMicro®Mini57 Naming Rule...................................................................................18
4.2 NuMicro®Mini57 Series Selection Guide...................................................................19
4.3 Pin Configuration........................................................................................................20
4.3.1 TSSOP 28-Pin................................................................................................................20
4.3.2 TSSOP 20-Pin................................................................................................................21
4.3.3 QFN 33-Pin ....................................................................................................................22
4.4 Pin Description ........................................................................................................... 24
4.4.1 Mini57 Series Pin Description.........................................................................................24
4.4.2 GPIO Multi-function Pin Summary..................................................................................36
5BLOCK DIAGRAM...........................................................................................39
5.1 NuMicro®Mini57 Block Diagram................................................................................39
6FUNCTIONAL DESCRIPTION.........................................................................40
6.1 ARM®Cortex®-M0 Core .............................................................................................40
6.1.1 Overview ........................................................................................................................40
6.1.2 Features .........................................................................................................................40
6.2 System Manager ........................................................................................................ 42
6.2.1 Overview ........................................................................................................................42
6.2.2 System Reset.................................................................................................................42
6.2.3 Power Modes and Wake-up Sources.............................................................................48
6.2.4 System Power Architecture ............................................................................................51
6.2.5 System Memory Mapping...............................................................................................52
6.2.6 Register Protection.........................................................................................................53
6.2.7 Memory Organization.....................................................................................................55
6.2.8 Register Map..................................................................................................................58
6.2.9 Register Description.......................................................................................................59
6.2.10 System Timer (SysTick) .................................................................................................79
6.2.11 Nested Vectored Interrupt Control (NVIC)......................................................................84
6.2.12 System Control Registers.............................................................................................104
6.3 Clock Controller........................................................................................................113
6.3.1 Overview ......................................................................................................................113
6.3.2 Auto Trim......................................................................................................................115
6.3.3 System Clock and SysTick Clock.................................................................................115
6.3.4 Peripherals Clock Source Selection .............................................................................116
6.3.5 Power-down Mode Clock..............................................................................................118
6.3.6 Frequency Divider Output.............................................................................................118
6.3.7 Register Map................................................................................................................120
6.3.8 Register Description.....................................................................................................121
6.4 Flash Memory Controller (FMC)...............................................................................133

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6.4.1 Overview ......................................................................................................................133
6.4.2 Features .......................................................................................................................133
6.4.3 Block Diagram..............................................................................................................133
6.4.4 Functional Description..................................................................................................135
6.4.5 Register Map................................................................................................................150
6.4.6 Register Description.....................................................................................................151
6.5 General Purpose I/O (GPIO).................................................................................... 162
6.5.1 Overview ......................................................................................................................162
6.5.2 Features .......................................................................................................................162
6.5.3 Block Diagram..............................................................................................................163
6.5.4 Basic Configuration ......................................................................................................163
6.5.5 Functional Description..................................................................................................163
6.5.6 GPIO Interrupt and Wake-up Function.........................................................................166
6.5.7 Register Map................................................................................................................167
6.5.8 Register Description.....................................................................................................170
6.6 Timer Controller (TIMER).........................................................................................187
6.6.1 Overview ......................................................................................................................187
6.6.2 Features.......................................................................................................................187
6.6.3 Block Diagram..............................................................................................................188
6.6.4 Basic Configuration ......................................................................................................189
6.6.5 Functional Description..................................................................................................189
6.6.6 Register Map................................................................................................................196
6.6.7 Register Description.....................................................................................................197
6.7 Enhanced Input Capture Timer (ECAP)...................................................................209
6.7.1 Overview ......................................................................................................................209
6.7.2 Features.......................................................................................................................209
6.7.3 Block Diagram..............................................................................................................209
6.7.4 Input Noise Filter ..........................................................................................................210
6.7.5 Operation of Input Capture Timer/Counter...................................................................211
6.7.6 Input Capture Timer/Counter Interrupt Architecture......................................................213
6.7.7 Register Map................................................................................................................214
6.7.8 Register Description.....................................................................................................215
6.8 Enhanced PWM Generator (EPWM) ....................................................................... 225
6.8.1 Overview ......................................................................................................................225
6.8.2 Features .......................................................................................................................225
6.8.3 Block Diagram..............................................................................................................226
6.8.4 Basic Configuration ......................................................................................................228
6.8.5 Functional Description..................................................................................................228
6.8.6 Register Map................................................................................................................247
6.8.7 Register Description.....................................................................................................248
6.9 Basic PWM Generator (BPWM)............................................................................... 275
6.9.1 Overview ......................................................................................................................275
6.9.2 Features .......................................................................................................................275
6.9.3 Block Diagram..............................................................................................................275
6.9.4 PWM-Timer Operation..................................................................................................276
6.9.5 Register Map................................................................................................................284

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6.9.6 Register Description.....................................................................................................285
6.10 Watchdog Timer (WDT) ...........................................................................................295
6.10.1 Overview ......................................................................................................................295
6.10.2 Features .......................................................................................................................295
6.10.3 Block Diagram..............................................................................................................295
6.10.4 Clock Control................................................................................................................296
6.10.5 Basic Configuration ......................................................................................................296
6.10.6 Functional Description..................................................................................................296
6.10.7 Registers Map ..............................................................................................................298
6.10.8 Register Description.....................................................................................................299
6.11 USCI –Universal Serial Control Interface Controller............................................... 301
6.11.1 Overview ......................................................................................................................301
6.11.2 Features.......................................................................................................................301
6.11.3 Block Diagram..............................................................................................................301
6.11.4 Functional Description..................................................................................................302
6.12 USCI –UART Mode................................................................................................. 313
6.12.1 Overview ......................................................................................................................313
6.12.2 Features.......................................................................................................................313
6.12.3 Block Diagram..............................................................................................................313
6.12.4 Basic Configuration ......................................................................................................314
6.12.5 Functional Description..................................................................................................314
6.12.6 Register Map................................................................................................................324
6.12.7 Register Description.....................................................................................................325
6.13 USCI –SPI Mode..................................................................................................... 346
6.13.1 Overview ......................................................................................................................346
6.13.2 Features.......................................................................................................................346
6.13.3 Block Diagram..............................................................................................................347
6.13.4 Basic Configuration ......................................................................................................347
6.13.5 Functional Description..................................................................................................348
6.13.6 Register Map................................................................................................................361
6.13.7 Register Description.....................................................................................................362
6.14 USCI –I2C Mode...................................................................................................... 384
6.14.1 Overview ......................................................................................................................384
6.14.2 Features .......................................................................................................................384
6.14.3 Block Diagram..............................................................................................................385
6.14.4 Basic Configuration ......................................................................................................385
6.14.5 Functional Description..................................................................................................385
6.14.6 Register Map................................................................................................................403
6.14.7 Register Description.....................................................................................................404
6.15 Hardware Divider (HDIV).......................................................................................... 422
6.15.1 Overview ......................................................................................................................422
6.15.2 Features .......................................................................................................................422
6.15.3 Basic Configuration ......................................................................................................422
6.15.4 Functional Description..................................................................................................423
6.15.5 Register Map................................................................................................................424

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6.15.6 Register Description.....................................................................................................425
6.16 Analog to Digital Converter (ADC) ...........................................................................430
1.1.1 Overview ......................................................................................................................430
1.1.2 Features .......................................................................................................................430
1.1.3 Block Diagram..............................................................................................................430
6.16.1 Basic Configuration ......................................................................................................431
6.16.2 Functional Description..................................................................................................431
6.16.3 Register Map................................................................................................................435
6.16.4 Register Description.....................................................................................................436
6.17 Analog Comparator (ACMP) .................................................................................... 452
6.17.1 Overview ......................................................................................................................452
6.17.2 Features.......................................................................................................................452
6.17.3 Block Diagram..............................................................................................................453
6.17.4 Basic Configuration ......................................................................................................453
6.17.5 Functional Description..................................................................................................454
6.17.6 Comparator Reference Voltage (CRV).........................................................................455
6.17.7 Register Map................................................................................................................456
6.17.8 Register Description.....................................................................................................457
6.18 Programmable Gain Amplifier (PGA).......................................................................467
6.18.1 Overview ......................................................................................................................467
1.1.4 Features .......................................................................................................................467
1.1.5 Block Diagram..............................................................................................................467
1.1.6 Register Map................................................................................................................467
6.18.2 Register Description.....................................................................................................468
7APPLICATION CIRCUIT................................................................................469
8ELECTRICAL CHARACTERISTICS..............................................................470
9PACKAGE DIMENSIONS..............................................................................471
1.2 28-Pin TSSOP (4.4x9.7x1.0 mm)............................................................................. 471
1.3 20-Pin TSSOP (4.4x6.5x0.9 mm)............................................................................. 472
9.1 33-pin *QFN33 (4x4x0.8 mm) ..................................................................................473
10 REVISION HISTORY.................................................................................474

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List of Figures
Figure 4.1-1 NuMicro®Mini57 Series Selection Code ................................................................... 18
Figure 4.3-1 NuMicro®Mini57 Series TSSOP 28-pin Diagram......................................................20
Figure 4.3-2 NuMicro®Mini57 Series TSSOP 28-pin Multi-function Diagram ............................... 20
Figure 4.3-3 NuMicro®Mini57 Series TSSOP 20-pin Diagram......................................................21
Figure 4.3-4 NuMicro®Mini57 Series TSSOP 20-pin Multi-function Diagram ............................... 21
Figure 4.3-5 NuMicro®Mini57 Series QFN 33-pin Diagram .......................................................... 22
Figure 4.3-6 NuMicro®Mini57 Series QFN 33-pin Multi-function Diagram.................................... 23
Figure 5.1-1 NuMicro®Mini57 Block Diagram ...............................................................................39
Figure 6.1-1 Functional Block Diagram.......................................................................................... 40
Figure 6.2-1 System Reset Resources.......................................................................................... 43
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 45
Figure 6.2-3 Power-on Reset (POR) Waveform............................................................................ 45
Figure 6.2-4 Low Voltage Reset (LVR) Waveform.........................................................................46
Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 47
Figure 6.2-6 Power Mode State Machine ...................................................................................... 48
Figure 6.2-7 NuMicro®Mini57 Series Power Architecture Diagram ..............................................51
Figure 6.2-8 NuMicro®Mini57 Flash, Security and Configuration Map .........................................55
Figure 6.2-9 SRAM Block Diagram................................................................................................ 57
Figure 6.3-1 Clock Generator Block Diagram.............................................................................. 113
Figure 6.3-2 Clock Generator Global View Diagram....................................................................114
Figure 6.3-3 System Clock Block Diagram .................................................................................. 115
Figure 6.3-4 SysTick Clock Control Block Diagram.....................................................................116
Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK ................................................. 117
Figure 6.3-6 Clock Source of Frequency Divider......................................................................... 119
Figure 6.3-7 Block Diagram of Frequency Divider....................................................................... 119
Figure 6.4-1 Flash Memory Control Block Diagram.....................................................................134
Figure 6.4-2 Flash Memory Organization ....................................................................................136
Figure 6.4-3 Data Flash Shared with APROM.............................................................................137
Figure 6.4-4 SPROM Security Mode............................................................................................ 139
Figure 6.4-5 Boot Select (BS) for Power-on Action .....................................................................144
Figure 6.4-6 Flash Memory Mapping of CBS in CONFIG0.......................................................... 145
Figure 6.4-7 Executable Range of Code with IAP Function Enabled..........................................146
Figure 6.4-8 Example Flow of Boot Selection by BS Bit when CBS[0] = 1..................................147
Figure 6.4-9 ISP Flow Example ...................................................................................................149
Figure 6.5-1 I/O Pin Block Diagram ............................................................................................. 162

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Figure 6.5-2 GPIO Controller Block Diagram...............................................................................163
Figure 6.5-3 Push-Pull Output...................................................................................................... 164
Figure 6.5-4 Open-Drain Output ..................................................................................................165
Figure 6.5-5 Quasi-Bidirectional I/O Mode...................................................................................165
Figure 6.6-1 Timer Controller Block Diagram ..............................................................................188
Figure 6.6-2 Clock Source of Timer Controller ............................................................................188
Figure 6.6-3 Continuous Counting Mode..................................................................................... 190
Figure 6.6-4 Free-Counting Capture Mode..................................................................................191
Figure 6.6-5 External Reset Counter Mode ................................................................................. 192
Figure 6.6-6 Continuous Capture Mode Block............................................................................. 194
Figure 6.6-7 Continuous Capture Mode Behavior ....................................................................... 195
Figure 6.7-1 Enhanced Input Capture Timer/Counter Architecture.............................................209
Figure 6.7-2 Enhanced Input Capture Timer/Counter Clock Source Control ..............................210
Figure 6.7-3 Noise Filter Sampling Clock Selection.....................................................................210
Figure 6.7-4 Noise Filter...............................................................................................................210
Figure 6.7-5 Enhanced Input Capture Timer/Counter Functions Block....................................... 212
Figure 6.7-6 Enhanced Input Capture Timer/Counter Interrupt Architecture Diagram................ 213
Figure 6.8-1 EPWM Clock Source............................................................................................... 226
Figure 6.8-2 EPWM Block Diagram............................................................................................. 227
Figure 6.8-3 EPWM Generator 0/1 Architecture Diagram ...........................................................227
Figure 6.8-4 EPWM Generator 2/3 Architecture Diagram ...........................................................227
Figure 6.8-5 EPWM Generator 4/5 Architecture Diagram ...........................................................228
Figure 6.8-6 EPWM Edge-aligned Waveform Output..................................................................229
Figure 6.8-7 EPWM Edge-aligned Mode Operation Timing ........................................................230
Figure 6.8-8 EPWM Edge-aligned Interrupt Diagram..................................................................231
Figure 6.8-9 EPWM Edge-aligned Flow Diagram........................................................................ 232
Figure 6.8-10 EPWM Legend of Internal Comparator Output of PWM-Timer.............................233
Figure 6.8-11 EPWM-Timer Operation Timing ............................................................................233
Figure 6.8-12 EPWM Center-aligned Type..................................................................................234
Figure 6.8-13 EPWM Center-aligned Mode Operation Timing.................................................... 235
Figure 6.8-14 EPWM Center-aligned Waveform Output.............................................................. 236
Figure 6.8-15 EPWM Center-aligned Interrupt Diagram.............................................................. 236
Figure 6.8-16 EPWM Center-aligned Flow Diagram.................................................................... 237
Figure 6.8-17 EPWM Dead-time Insertion................................................................................... 239
Figure 6.8-18 EPWM Asymmetric Mode Timing Diagram........................................................... 240
Figure 6.8-19 EPWM One-Shot Mode Architecture..................................................................... 240

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Figure 6.8-20 EPWM Initial State and Polarity Control with Rising Edge Dead-time Insertion ... 241
Figure 6.8-21 EPWM Interrupt Architecture.................................................................................242
Figure 6.8-22 EPWM Brake Architecture.....................................................................................243
Figure 6.8-23 EPWM 3-phase Motor Mask Diagram................................................................... 244
Figure 6.8-24 EPWM 3-phase Motor Mask Example 1................................................................ 245
Figure 6.8-25 EPWM 3-phase Motor Mask Example 2................................................................ 245
Figure 6.9-1 PWM Clock Source Control.....................................................................................276
Figure 6.9-2 PWM Architecture Diagram..................................................................................... 276
Figure 6.9-3 Legend of Internal Comparator Output of PWM-Timer ...........................................277
Figure 6.9-4 PWM-Timer Operation Timing.................................................................................278
Figure 6.9-5 PWM Edge-aligned Interrupt Generate Timing Waveform...................................... 278
Figure 6.9-6 Center-aligned Type Output Waveform...................................................................279
Figure 6.9-7 PWM Center-aligned Interrupt Generate Timing Waveform ...................................280
Figure 6.9-8 PWM Double Buffering Illustration........................................................................... 281
Figure 6.9-9 PWM Controller Output Duty Ratio.......................................................................... 281
Figure 6.9-10 Paired-PWM Output with Dead-zone Generation Operation.................................282
Figure 6.9-11 PWM Interrupt Architecture Diagram..................................................................... 282
Figure 6.10-1 Watchdog Timer Block Diagram............................................................................ 295
Figure 6.10-2 Watchdog Timer Clock Control Diagram............................................................... 296
Figure 6.10-3 Watchdog Timer Time-out Interval and Reset Period Timing ...............................297
Figure 6.11-1 USCI Block Diagram.............................................................................................. 301
Figure 6.11-2 Input Conditioning for USCIx_DAT[1:0] and USCIx_CTL[1:0] ..............................303
Figure 6.11-3 Input Conditioning for USCIx_CLK........................................................................ 303
Figure 6.11-4 Block Diagram of Data Buffering ........................................................................... 305
Figure 6.11-5 Data Access Structure........................................................................................... 305
Figure 6.11-6 Transmit Data Path................................................................................................ 306
Figure 6.11-7 Receive Data Path................................................................................................. 307
Figure 6.11-8 Protocol-Relative Clock Generator........................................................................ 308
Figure 6.11-9 Basic Clock Divider Counter..................................................................................309
Figure 6.11-10 Block of Timing Measurement Counter............................................................... 309
Figure 6.11-11 Sample Time Counter.......................................................................................... 310
Figure 6.11-12 Event and Interrupt Structure ..............................................................................311
Figure 6.12-1 USCI - UART Mode Block Diagram....................................................................... 313
Figure 6.12-2 UART Signal Connection for Full-Duplex Communication.................................... 314
Figure 6.12-3 UART Standard Frame Format .............................................................................316
Figure 6.12-4 UART Bit Timing (Data Sample Time)................................................................... 318

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Figure 6.12-5 UART Auto Baud Rate Control.............................................................................. 320
Figure 6.12-6 Incoming Data Wake-Up .......................................................................................321
Figure 6.13-1 SPI Master Mode Application Block Diagram (x=0, 1) ..........................................346
Figure 6.13-2 SPI Slave Mode Application Block Diagram (x=0, 1) ............................................346
Figure 6.13-3 USCI - SPI Mode Block Diagram........................................................................... 347
Figure 6.13-4 4-Wire Full-Duplex SPI Communication Signals (Master Mode) ......................... 348
Figure 6.13-5 4-Wire Full-Duplex SPI Communication Signals (Slave Mode) ............................349
Figure 6.13-6 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x0)..350
Figure 6.13-7 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x1)..350
Figure 6.13-8 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x2)..351
Figure 6.13-9 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x3)..351
Figure 6.13-10 16-bit data Length in One Word Transaction with MSB First Format................. 352
Figure 6.13-11 Word Suspend Interval between Two Transaction Words..................................353
Figure 6.13-12 Auto Slave Select (SUSPITV ≧0x3)..................................................................354
Figure 6.13-13 Auto Slave Select (SUSPITV < 0x3) ................................................................... 354
Figure 6.13-14 SPI Timing in Master Mode ................................................................................. 357
Figure 6.13-15 SPI Timing in Master Mode (Alternate Phase of Serial Bus Clock) ....................357
Figure 6.13-16 SPI Timing in Slave Mode ................................................................................... 358
Figure 6.13-17 SPI Timing in Slave Mode (Alternate Phase of Serial Bus Clock) ......................358
Figure 6.14-1 I2C Bus Timing....................................................................................................... 384
Figure 6.14-2 USCI - I²C Mode Block Diagram............................................................................ 385
Figure 6.14-3 I2C Protocol............................................................................................................ 386
Figure 6.14-4 START and STOP Conditions............................................................................... 386
Figure 6.14-5 Bit Transfer on I2C Bus.......................................................................................... 388
Figure 6.14-6 Acknowledge on I2C Bus....................................................................................... 388
Figure 6.14-7 Arbitration Lost....................................................................................................... 390
Figure 6.14-8 Control I2C Bus according to Current I2C Status................................................... 392
Figure 6.14-9 Master Transmits Data to Slave with a 7-bit Address ...........................................393
Figure 6.14-10 Master Reads Data from Slave with a 7-bit Address........................................... 393
Figure 6.14-11 Master Transmits Data to Slave by 10-bit Address............................................. 393
Figure 6.14-12 Master Reads Data from Slave by 10-bit Address ..............................................394
Figure 6.14-13 Master Transmitter Mode Control Flow with 7-bit Address .................................394
Figure 6.14-14 Master Receiver Mode Control Flow with 7-bit Address .....................................395
Figure 6.14-15 Save Mode Control Flow with 7-bit Address .......................................................396
Figure 6.14-16 GC Mode with 7-bit Address................................................................................398
Figure 6.14-17 Setup Time Wrong Adjustment............................................................................399

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Figure 6.14-18 Hold Time Wrong Adjustment.............................................................................. 400
Figure 6.14-19 I2C Time-out Count Block Diagram .....................................................................400
Figure 6.14-20 EEPROM Random Read..................................................................................... 401
Figure 6.14-21 Protocol of EEPROM Random Read...................................................................402
Figure 6.15-1 Hardware Divider Operation Flow .........................................................................423
Figure 6.16-1 ADC Control Block Diagram.................................................................................. 430
Figure 6.16-2 ADC Peripheral Clock Control............................................................................... 431
Figure 6.16-3 Single Mode Conversion Timing Diagram............................................................. 432
Figure 6.16-4 ADC Hardware Trigger Source.............................................................................. 433
Figure 6.16-5 Independent Sample Mode Conversion Timing Diagram...................................... 433
Figure 6.16-6 Simultaneous Simple Mode Conversion Timing Diagram.....................................434
Figure 6.16-7 Simultaneous Sequential 4R Mode Conversion Timing Diagram ......................... 434
Figure 6.17-1 Analog Comparator Block Diagram....................................................................... 453
Figure 6.17-2 Analog Comparator Controller Interrupt Sources.................................................. 454
Figure 6.17-3 Comparator Hysteresis Function........................................................................... 454
Figure 6.17-4 Comparator Reference Voltage Block Diagram .................................................... 455
Figure 6.18-1 OP Amplifier Block Diagram.................................................................................. 467

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List of Tables
Table 3-1 List of Abbreviations....................................................................................................... 17
Table 4.2-1 NuMicro®Mini57 Series Selection Guide ...................................................................19
Table 4.4-1 TSSOP28 Pin Description ..........................................................................................27
Table 4.4-2 TSSOP20 Pin Description .......................................................................................... 31
Table 4.4-3 QFN33 Pin Description...............................................................................................35
Table 4.4-4 TSSOP20 Multi-function Pin Summary.......................................................................38
Table 6.2-1 Reset Value of Registers............................................................................................ 44
Table 6.2-2 Power Mode Difference Table .................................................................................... 48
Table 6.2-3 Clocks in Power Modes .............................................................................................. 49
Table 6.2-4 Condition of Entering Power-down Mode Again.........................................................50
Table 6.2-5 Memory Mapping Table.............................................................................................. 52
Table 6.2-6 Protected Registers ....................................................................................................54
Table 6.2-7 Address Space Assignments for On-Chip Modules ...................................................56
Table 6.2-8 Exception Model .........................................................................................................85
Table 6.2-9 System Interrupt Map Vector Table............................................................................ 86
Table 6.2-10 Vector Table Format.................................................................................................86
Table 6.3-1 Peripheral Clock Source Selection Table.................................................................118
Table 6.3-2 Power-down Mode Control Table ............................................................................. 123
Table 6.4-1 Flash Memory Address Map.....................................................................................135
Table 6.4-2 Data Flash Table....................................................................................................... 136
Table 6.4-3 Boot Selection........................................................................................................... 145
Table 6.4-4 Boot Selection and Supports Function .....................................................................145
Table 6.4-5 ISP Command Table................................................................................................. 149
Table 6.6-1 Input Capture Mode Operation ................................................................................. 193
Table 6.10-1 Watchdog Timer Time-out Interval Period Selection..............................................297
Table 6.11-1 Input Signals for Different Protocols ....................................................................... 302
Table 6.11-2 Output Signals for Different Protocols ....................................................................304
Table 6.11-3 Data Transfer Events and Interrupt Handling......................................................... 311
Table 6.11-4 Protocol-specific Events and Interrupt Handling.....................................................312
Table 6.12-1 Input Signals for UART Protocols........................................................................... 315
Table 6.12-2 Output Signals for Different Protocols ....................................................................315
Table 6.12-3 Baud rate Relationship ...........................................................................................319
Table 6.13-1 SPI Communication Signals (x=0, 1)...................................................................... 348
Table 6.13-2 Serial Bus Clock Configuration...............................................................................349
Table 6.14-1 Relationship between I2C Baud Rate and PCLK....................................................399

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1 GENERAL DESCRIPTION
The NuMicro® Mini57 series 32-bit microcontrollers are embedded with ARM®Cortex®-M0 core for
industrial applications which need high performance, high integration, and low cost. The Cortex®-
M0 is the newest ARM®embedded processor with 32-bit performance at a cost equivalent to the
traditional 8-bit microcontroller.
The Mini57 series can run up to 48 MHz and operate at 2.1V ~ 5.5V, -40℃~ 105℃, and thus can
support a variety of industrial control applications which need high CPU performance. The Mini57
offers 29.5 Kbytes embedded program Flash, size configurable Data Flash (shared with program
Flash), 2 Kbytes Flash for the ISP, 1.5 Kbytes SPROM for security, and 4 Kbytes SRAM.
Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM, ADC,
Watchdog Timer, Analog Comparator and Brown-out Detector, have been incorporated into the
Mini57 to reduce component count, board space and system cost. These useful functions make
the Mini57 powerful for a wide range of applications.
Additionally, the Mini57 series is equipped with ISP (In-System Programming) and ICP (In-Circuit
Programming) functions, which allow the user to update program memory without removing the
chip from the actual end product.

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2 FEATURES
Core
- ARM® Cortex® -M0 core running up to 48 MHz
- One 24-bit system timer
- Supports low power Idle mode
- A single-cycle 32-bit hardware multiplier
- NVIC for the 32 interrupt inputs, each with 4-level of priority
- Supports Serial Wire Debug (SWD) interface and two watchpoints/four
breakpoints
Built-in LDO for wide operating voltage ranged: 2.1V to 5.5V
Memory
- 29.5 Kbytes Flash memory for program memory (APROM)
- Configurable Flash memory for data memory (Data Flash)
- 2 KB Flash memory for loader (LDROM)
- Three 0.5 KB Flash memory for security protection (SPROM)
- 4 KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
- Programmable system clock source
Switch clock sources on-the-fly
- 4 ~ 24 MHz external crystal input (HXT)
- 32.768 kHz external crystal input (LXT) for idle wake-up and system operation
clock
- 48 MHz internal oscillator (HIRC) (±1% accuracy at 250C, 5V)
Dynamically calibrating the HIRC OSC to 48 MHz ±1% from -40℃to 105℃
by external 32.768K crystal oscillator (LXT)
- 10 kHz internal low-power oscillator (LIRC) for Watchdog Timer and idle wake-
up
I/O Port
- Up to 22 general-purpose I/O (GPIO) pins and 1 Reset pin for QFN-33 package
- Four I/O modes:
Quasi-bidirectional input/output
Push-Pull output
Open-Drain output
Input only with high impendence
- Optional TTL/Schmitt trigger input
- I/O pin can be configured as interrupt source with edge/level setting
- Supports high driver and high sink I/O mode

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MINI57 SERIES TECHNICAL REFERENCE MANUAL
- Supports software selectable slew rate control
- GPIO built-in Pull-up/Pull-low resistor for selection.
Timer
- Provides two channel 32-bit Timers; one 8-bit pre-scalar counter with 24-bit up-
timer for each timer
- Independent clock source for each timer
- Provides One-shot, Periodic, Toggle and Continuous operation modes
- 24-bit up counter value is readable through CNT (Timer Data Register)
- Provides trigger counting/free counting/counter reset function triggered by
external capture pin or internal comparator signal
- Supports event counter function
- Supports Toggle Output mode
- Supports wake-up from Idle or Power-down mode
- Timer0, Timer1 and Systick provided with Continuous capture function to
capture at most 4 edges continuously on one signal
Continuous Capture
- Timer0, Timer1 and Systick have support Continuous capture function can
Continuous Capture 4 edge on one signal
Enhanced Input Capture
- One unit of 24-bit input capture counter
- Capture surce:
I/O inputs: ECAP0, ECAP1 and ECAP2
PWM Trigger
ADC Trigger
WDT (Watchdog Timer)
- Programmable clock source and time-out period
- Supports wake-up function in Power-down mode and Idle mode
- Interrupt or reset selectable on watchdog time-out
PWM
- Supports a built-in 16-bit PWM clock generators, providing six PWM outputs or
three complementary paired PWM outputs
- Shared same as clock source, clock divider, period and dead-zone generator
- Supports group/synchronous/independent/ complementary modes
- Supports One-shot or Auto-reload mode
- Supports Edge-aligned and Center-aligned type
- Supports Asymmetric mode
- Programmable dead-zone insertion between complementary channels
- Each output has independent polarity setting control

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- Hardware fault brake and software brake protections
- Supports rising, falling, central, period, and fault break interrupts
- Supports duty/period trigger A/D conversion
- Timer comparing matching event trigger PWM to do phase change
- Supports comparator event trigger PWM to force PWM output low for current
period
- Provides interrupt accumulation function
USCI (Universal Serial Control Interface Controller)
- Two USCI devices
- Supports to be configured as UART, SPI or I²C individually
- Supports programmable baud-rate generator
ADC (Analog-to-Digital Converter)
- 12-bit ADC with 700 kSPS
- Supports 2 sample/hold
- Up to 8-ch single-end input from I/O and one internal input from band-gap.
- Conversion started either by software trigger, PWM trigger, ACMP trigger or
external pin trigger
- Supports temperature sensor for measurement chip temperature
- Supports Simultaneous and Sequential function to continuous conversion 4
channels maximum.
Programmable Gain Amplifier (PGA)
- Supports 8 level gain selects from 1, 2, 3, 5, 7, 9, 11 and 13
- Unity gain frequency up to 8 MHz
Analog Comparator
- Two analog comparators with programmable 16-level internal voltage reference
- Built-in CRV (comparator reference voltage)
- Supports Hysteresis function
- Interrupt when compared results changed
Hardware Divider
- Signed (two’s complement) integer calculation
- 32-bit dividend with 16-bit divisor calculation capacity
- 32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends
to 32-bit)
- Divided by zero warning flag
- 6 HCLK clocks taken for one cycle calculation
- Waiting for calculation ready automatically when reading quotient and remainder
ISP (In-System Programming) and ICP (In-Circuit Programming)

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MINI57 SERIES TECHNICAL REFERENCE MANUAL
BOD (Brown-out Detector)
- 8 programmable threshold levels: 4.3V/4.0V/3.7V/3.0V/2.7V/2.4V/2.2V/2.0V
- Supports Brown-out interrupt and reset option
96-bit unique ID
LVR (Low Voltage Reset)
Operating Temperature: -40℃~105℃
Reliability: EFT > ± 4KV, ESD HBM pass 4KV
Packages:
- Green package (RoHS)
- 20-pin TSSOP, 28-pin TSSOP, 33-pin QFN

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MINI57 SERIES TECHNICAL REFERENCE MANUAL
3 ABBREVIATIONS
Acronym
Description
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AHB
Advanced High-Performance Bus
APB
Advanced Peripheral Bus
BOD
Brown-out Detection
BPWM
Basic Pulse Width Modulation
DAP
Debug Access Port
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
48 MHz Internal High Speed RC Oscillator
HXT
4~24 MHz External High Speed Crystal Oscillator
ICP
In Circuit Programming
ISP
In System Programming
ISR
Interrupt Service Routine
LDO
Low Dropout Regulator
LIRC
10 kHz internal low speed RC oscillator (LIRC)
LXT
32.768 kHz External Low Speed Crystal Oscillator
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PWM
Pulse Width Modulation
SPI
Serial Peripheral Interface
SPS
Samples per Second
TMR
Timer Controller
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
WDT
Watchdog Timer
Table 3-1 List of Abbreviations

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MINI57 SERIES TECHNICAL REFERENCE MANUAL
4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro®Mini57 Naming Rule
Mini57-X X X
ARM–Based
32-bit Microcontroller
CPU Core
Corte®-M0
Flash ROM
57 : 29.5 KB Flash ROM
Temperature
Reserved
Package Type
F: TSSOP 20
E: TSSOP 28
T: QFN 33 4x4mm
E: -40oC ~ +105oC
Figure 4.1-1 NuMicro®Mini57 Series Selection Code

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4.2 NuMicro®Mini57 Series Selection Guide
*USCI can be set to UART, SPI or I2C
Part
Number
APROM
RAM
Data Flash
ISP
Loader
ROM
I/O
Timer
Connectivity
Comp.
PWM
ADC
PGA
ISP
ICP
IAP
IRC
10 kHz
48 MHz
Package
USCI*
Mini57TDE
29.5 KB
4 KB
Configurable
2.5 KB
up to 22
2x32-bit
2
2
8
8x12-bit
v
v
v
QFN33(4x4)
Mini57EDE
29.5 KB
4 KB
Configurable
2.5 KB
up to 22
2x32-bit
2
2
8
8x12-bit
v
v
v
TSSOP28
Mini57FDE
29.5 KB
4 KB
Configurable
2.5 KB
up to 18
2x32-bit
2
2
8
8x12-bit
v
v
v
TSSOP20
Table 4.2-1 NuMicro®Mini57 Series Selection Guide

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MINI57 SERIES TECHNICAL REFERENCE MANUAL
4.3 Pin Configuration
4.3.1 TSSOP 28-Pin
PC.0
VDD VSS 1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA.0
PA.1
PA.2
PA.3
PB.1
PB.2
PB.3
PB.4
PC.1
PC.3
nRESET
PD.1
PD.2
PA.4
PA.5
PB.0
PC.2
NC
28
27
26
25
24
23
22
21
PD.6
PD.3
PC.4
LDO_CAP
PD.5
PD.4NC
Figure 4.3-1 NuMicro®Mini57 Series TSSOP 28-pin Diagram
PC.0/ADC0_CH3/BPWM_CH0/ACMP1_P0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
VDD VSS 1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA.0/CLKO/EPWM_CH0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PA.1/EPWM_CH1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1
PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2
PB.3/ACMP1_N/PGA_I/TM0
PB.4/ADC1_CH0/ACMP0_N/TM1
PC.1/ADC0_CH4/STADC/ACMP0_P3/ACMP1_P1/SPI0_MOSI/SPI1_MISO
PC.3/ACMP1_O/PGA_O/SPI0_CLK/SPI1_SS
nRESET
PD.1/ICE_CLK/ACMP1_P2/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
PD.2/ICE_DAT/ADC1_CH1/CCAP_P0/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PA.4/XT_IN/EPWM_CH4
PA.5/XT_OUT/EPWM_CH5/ACMP0_O
PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0
PC.2/ADC1_CH2/BRAKE/CCAP_P1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
NC
28
27
26
25
24
23
22
21
PD.6/UART0_RXD
PD.3/BPWM_CH1/UART1_TXD
PC.4/ECAP_P3
LDO_CAP
PD.5/UART0_TXD
PD.4/BPWM_CH0/UART1_RXDNC
Figure 4.3-2 NuMicro®Mini57 Series TSSOP 28-pin Multi-function Diagram