SONIX SN32F280 Series User manual

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version 1.1
SN32F280 Series
USER’S MANUAL
SN32F289
SN32F288
SN32F287
SONiX 32-Bit Cortex-M0 Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the
part.

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version 1.1
AMENDENT HISTORY
Version
Date
Description
1.0
2020/03/25
First version released.
1.1
2020/06/01
1. Fix typing errors.
2. Update the CMP and OPA block diagram.
3. Add I2C0PRE and I2C1PRE bits in 3.4.3 SYS1_APBCP1 register.
4. Fix 3.3V Regulator Output voltage.

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 1.1
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW....................................................................................................................... 16
1.1 FEATURES...................................................................................................................................... 16
1.2 SYSTEM BLOCK DIAGRAM........................................................................................................ 18
1.3 CLOCK GENERATION BLOCK DIAGRAM................................................................................ 19
1.4 PIN ASSIGNMENT......................................................................................................................... 20
1.5 PIN ALLOCATION TABLE............................................................................................................ 23
1.6 PIN DESCRIPTIONS....................................................................................................................... 26
1.7 PIN CIRCUIT DIAGRAMS............................................................................................................. 34
1.8 PIN CHARACTERISTICS............................................................................................................... 36
2
2
2
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 38
2.1 MEMORY MAP............................................................................................................................... 38
2.2 SYSTEM TICK TIMER................................................................................................................... 39
2.2.1 OPERATION ............................................................................................................................ 39
2.2.2 SYSTICK USAGE HINTS AND TIPS ....................................................................................... 40
2.2.3 SYSTICK REGISTERS.............................................................................................................. 40
2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL)................................... 40
2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD)........................................... 40
2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL)............................................ 41
2.2.3.4 System Tick Timer Calibration Value register (SYSTICK_CALIB) .................................. 41
2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC) ..................................................... 42
2.3.1 INTERRUPT AND EXCEPTION VECTORS ........................................................................... 42
2.3.2 NVIC REGISTERS.................................................................................................................... 43
2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER)....................................................... 43
2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)................................................... 43
2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR) ..................................................... 44
2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR) ................................................. 44
2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)............................................... 44
2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC).................................................. 45
2.5 CODE OPTION TABLE.................................................................................................................. 46
2.6 UNIQUE NUMBER......................................................................................................................... 46
2.7 CORE REGISTER OVERVIEW ..................................................................................................... 47
3
3
3
SYSTEM CONTROL............................................................................................................................. 48
3.1 RESET.............................................................................................................................................. 48
3.1.1 POWER-ON RESET (POR)...................................................................................................... 48

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
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3.1.2 WATCHDOG RESET (WDT RESET)....................................................................................... 49
3.1.3 BROWN-OUT RESET............................................................................................................... 49
3.1.3.1 BROWN OUT DESCRIPTION........................................................................................... 49
3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION............................................... 50
3.1.3.3 BROWN-OUT RESET IMPROVEMENT.......................................................................... 50
3.1.4 EXTERNAL RESET .................................................................................................................. 51
3.1.4.1 SIMPLY RC RESET CIRCUIT........................................................................................... 52
3.1.4.2 DIODE & RC RESET CIRCUIT......................................................................................... 52
3.1.4.3 ZENER DIODE RESET CIRCUIT...................................................................................... 53
3.1.4.4 VOLTAGE BIAS RESET CIRCUIT................................................................................... 53
3.1.4.5 EXTERNAL RESET IC....................................................................................................... 54
3.1.5 SOFTWARE RESET ................................................................................................................. 54
3.2 SYSTEM CLOCK............................................................................................................................ 55
3.2.1 INTERNAL RC CLOCK SOURCE ........................................................................................... 55
3.2.1.1 Internal High-speed RC Oscillator (IHRC).......................................................................... 55
3.2.1.2 Internal Low-speed RC Oscillator (ILRC)........................................................................... 55
3.2.2 PLL ........................................................................................................................................... 56
3.2.2.1 PLL Frequency selection...................................................................................................... 56
3.2.3 EXTERNAL CLOCK SOURCE ................................................................................................ 57
3.2.3.1 External High-speed (EHS) Clock ....................................................................................... 57
3.2.3.2 CRYSTAL/CERAMIC......................................................................................................... 57
3.2.3.3 External Low-speed (ELS) Clock......................................................................................... 58
3.2.3.4 CRYSTAL............................................................................................................................ 58
3.2.3.5 Bypass Mode ........................................................................................................................ 59
3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION............................................................................... 59
3.2.5 CLOCK-OUT CAPABITITY..................................................................................................... 59
3.3 SYSTEM CONTROL REGISTERS 0.............................................................................................. 60
3.3.1 Analog Block Control register (SYS0_ANBCTRL)................................................................... 60
3.3.2 PLL control register (SYS0_PLLCTRL)................................................................................... 60
3.3.2.1 RECOMMEND FREQUENCY SETTING.......................................................................... 61
3.3.3 Clock Source Status register (SYS0_CSST).............................................................................. 61
3.3.4 System Clock Configuration register (SYS0_CLKCFG).......................................................... 61
3.3.5 AHB Clock Prescale register (SYS0_AHBCP)......................................................................... 62
3.3.6 System Reset Status register (SYS0_RSTST) ............................................................................ 62
3.3.7 LVD Control register (SYS0_LVDCTRL)................................................................................. 63
3.3.8 External RESET Pin Control register (SYS0_EXRSTCTRL) ................................................... 63
3.3.9 SWD Pin Control register (SYS0_SWDCTRL)......................................................................... 64
3.3.10 Interrupt Vector Table Mapping register (SYS0_IVTM).......................................................... 64
3.3.11 Noise Detect Control register (SYS0_NDTCTRL).................................................................... 64
3.3.12 Noise Detect Status register (SYS0_NDTSTS).......................................................................... 65

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 Version 1.1
3.3.13 Anti-EFT Ability Control register (SYS0_ANTIEFT)............................................................... 65
3.3.14 IHRC Frequency Adjustment register (SYS0_IHRCADJ)........................................................ 65
3.4 SYSTEM CONTROL REGISTERS 1.............................................................................................. 66
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN).................................................................... 66
3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0)..................................................................... 67
3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1)..................................................................... 68
3.4.4 Peripheral Reset register (SYS1_PRST)................................................................................... 69
4
4
4
SYSTEM OPERATION MODE........................................................................................................... 71
4.1 OVERVIEW..................................................................................................................................... 71
4.2 NORMAL MODE ............................................................................................................................ 71
4.3 LOW-POWER MODES................................................................................................................... 71
4.3.1 SLEEP MODE.......................................................................................................................... 71
4.3.2 DEEP-SLEEP MODE............................................................................................................... 72
4.4 WAKEUP......................................................................................................................................... 73
4.4.1 OVERVIEW .............................................................................................................................. 73
4.4.2 WAKEUP TIME........................................................................................................................ 73
4.5 STATE MACHINE OF PMU........................................................................................................... 74
4.6 OPERATION MODE COMPARSION TABLE .............................................................................. 75
4.7 PMU REGISTERS ........................................................................................................................... 76
4.7.1 Power Control register (PMU_CTRL)..................................................................................... 76
5
5
5
GENERAL PURPOSE I/O PORT (GPIO).......................................................................................... 77
5.1 OVERVIEW..................................................................................................................................... 77
5.2 GPIO MODE .................................................................................................................................... 77
5.3 GPIO REGISTERS........................................................................................................................... 78
5.3.1 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)......................................................... 78
5.3.2 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3)...................................................... 78
5.3.3 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3)............................................ 78
5.3.4 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3)............................................... 80
5.3.5 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3)........................... 80
5.3.6 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3)............................................ 80
5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3)............................................ 80
5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3) ................................... 81
5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3).............................................. 81
5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3).................................... 81
5.3.11 Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3) ......................................... 81
5.3.12 GPIO Port n Configuration register 1 (GPIOn_CFG1) (n=0,1,3).......................................... 82
6
6
6
PERIPHERAL FUNCTION PIN ASSIGNMENT (PFPA)................................................................ 83
6.1 OVERVIEW..................................................................................................................................... 83

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version 1.1
6.2 FEATURES...................................................................................................................................... 83
6.3 PIN ASSIGNMENT LIST................................................................................................................ 83
6.4 PFPA REGISTERS........................................................................................................................... 85
6.4.1 PFPA for CT16B0 register (PFPA_CT16B0).......................................................................... 85
6.4.2 PFPA for CT16B1 register (PFPA_CT16B1).......................................................................... 85
6.4.3 PFPA for UART register (PFPA_UART)................................................................................. 86
6.4.4 PFPA for I2S register (PFPA_I2C).......................................................................................... 87
6.4.5 PFPA for SPI register (PFPA_SPI) ......................................................................................... 87
6.4.6 PFPA for I2S register (PFPA_I2S).......................................................................................... 88
6.4.7 PFPA for CT16B2 register (PFPA_CT16B2).......................................................................... 89
6.4.8 PFPA for CT16B3 register (PFPA_CT16B3).......................................................................... 89
6.4.9 PFPA for CT16B4 register (PFPA_CT16B4).......................................................................... 90
6.4.10 PFPA for CT16B5 register (PFPA_CT16B5).......................................................................... 90
7
7
7
16+3 CHANNEL ANALOG TO DIGITAL CONVERTOR (ADC).................................................. 92
7.1 OVERVIEW..................................................................................................................................... 92
7.2 ADC CONVERTING TIME ............................................................................................................ 93
7.3 ADC CONTROL NOTICE............................................................................................................... 94
7.3.1 ADC SIGNAL............................................................................................................................ 94
7.3.2 ADC PROGRAM ...................................................................................................................... 94
7.3.3 ADC PIN CONFIGURATION.................................................................................................. 94
7.4 ADC CIRCUIT................................................................................................................................. 95
7.5 ADC REGISTERS............................................................................................................................ 96
7.5.1 ADC Management register (ADC_ADM)................................................................................. 96
7.5.2 ADC Data register (ADC_ADB) .............................................................................................. 97
7.5.3 ADC Interrupt Enable register (ADC_IE)................................................................................ 97
7.5.4 ADC Raw Interrupt Status register (ADC_RIS)....................................................................... 98
8
8
8
RAIL TO RAIL ANALOG COMPARATOR ..................................................................................... 99
8.1 OVERVIEW..................................................................................................................................... 99
8.2 NORMAL COMPARATOR MODE.............................................................................................. 101
8.2.1 COMPARATOR ENABLE ...................................................................................................... 101
8.2.2 CMnOUT, CMnG AND CMnIF.............................................................................................. 102
8.2.3 COMPARATOR OUTPUT DEBOUNCE TIME CONTROL.................................................. 103
8.3 COMPARATOR APPLICATION NOTICE.................................................................................. 103
8.4 CMP REGISTERS.......................................................................................................................... 104
8.4.1 CMP Control register (CMP_CTRL)..................................................................................... 104
8.4.2 CMP Control register 1 (CMP_CTRL1)................................................................................ 105
8.4.3 CMP Internal Reference Voltage Source register (CMP_VIREF)......................................... 105
8.4.4 CMP Output Status register (CMP_OS) ................................................................................ 105

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version 1.1
8.4.5 CMP Interrupt Enable register (CMP_IE)............................................................................. 106
8.4.6 CMP Raw Interrupt Status register (CMP_RIS).................................................................... 106
8.4.7 CMP Interrupt Clear register (CMP_IC)............................................................................... 107
8.4.8 CMP Output Debounce register (CMP_DB).......................................................................... 107
9
9
9
OPERATIONAL-AMPLIFIER (OPA).............................................................................................. 108
9.1 OVERVIEW................................................................................................................................... 108
9.2 CONFIGURATION OF OPERATION.......................................................................................... 108
9.3 OPA REGISTERS.......................................................................................................................... 110
9.3.1 OPA Control register (OPA_CTRL)....................................................................................... 110
1
1
10
0
0
16-BIT TIMER WITH CAPTURE FUNCTION .......................................................................... 111
10.1 OVERVIEW................................................................................................................................... 111
10.2 FEATURES.................................................................................................................................... 111
10.3 PIN DESCRIPTION....................................................................................................................... 112
10.4 BLOCK DIAGRAM....................................................................................................................... 112
10.5 TIMER OPERATION .................................................................................................................... 113
10.5.1 Edge-aligned Up-counting Mode ........................................................................................... 113
10.5.2 Edge-aligned Down-counting Mode....................................................................................... 114
10.5.3 Center-aligned Counting Mode.............................................................................................. 114
10.6 PWM............................................................................................................................................... 115
10.6.1 PWM Mode 1.......................................................................................................................... 115
10.6.2 PWM Mode 2.......................................................................................................................... 116
10.8 CT16BN REGISTERS.................................................................................................................... 120
10.8.1 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,2) ........................................... 120
10.8.2 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=1,3,4) ........................................ 121
10.8.3 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=5) .............................................. 121
10.8.4 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1,2,3,4,5) ........................................... 122
10.8.5 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1,2,3,4,5)................................................... 122
10.8.6 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1,2,3,4,5)....................................... 122
10.8.7 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0,1,2,3,4,5)................................ 122
10.8.8 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,2,5) ............................................ 123
10.8.9 CT16Bn Match Control register (CT16Bn_MCTRL) (n=3,4) ............................................... 124
10.8.10 CT16Bn Match Control register (CT16Bn_MCTRL) (n=1) .............................................. 125
10.8.11 CT16Bn Match Control register 2 (CT16Bn_MCTRL2) (n=1) ......................................... 127
10.8.12 CT16Bn Match register 0~1 (CT16Bn_MR0~1) (n=0,2,3,4,5).......................................... 128
10.8.13 CT16Bn Match register 2~3 (CT16Bn_MR2~3) (n=0,2,5)................................................ 128
10.8.14 CT16Bn Match register 9 (CT16Bn_MR9) (n=0,2,3,4,5).................................................. 128
10.8.15 CT16Bn Match register 0~11 (CT16Bn_MR0~11) (n=1).................................................. 128
10.8.16 CT16Bn Match register 12 (CT16Bn_MR12) (n=1).......................................................... 129

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
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10.8.17 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0,1,2,3,4,5) ........................ 129
10.8.18 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0,1,2,3,4,5) .......................................... 130
10.8.19 CT16Bn External Match register (CT16Bn_EM) (n=0,2,5) .............................................. 131
10.8.20 CT16Bn External Match register (CT16Bn_EM) (n=3,4) ................................................. 132
10.8.21 CT16Bn External Match register (CT16Bn_EM) (n=1) .................................................... 132
10.8.22 CT16Bn External Match Control register (CT16Bn_EMC) (n=1) .................................... 133
10.8.23 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=0,2,5).................................... 135
10.8.24 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=3,4)....................................... 136
10.8.25 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=1).......................................... 137
10.8.26 CT16Bn PWM Enable register (CT16Bn_PWMENB) (n=1)............................................. 138
10.8.27 CT16Bn PWM IO Enable register (CT16Bn_PWMIOENB) (n=1) ................................... 139
10.8.28 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0,2,5) ........................... 140
10.8.29 T16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=3,4)................................. 141
10.8.30 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=1) ................................. 141
10.8.31 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,2,5)...................................... 142
10.8.32 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=1)............................................ 143
10.8.33 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=3,4)......................................... 143
10.8.34 CT16Bn PWMmN IO Control register (CT16Bn_PWMmNIOCTRL) (n=0) ..................... 144
10.8.35 CT16Bn PWMmN IO Control register (CT16Bn_PWMmNIOCTRL) (n=3,4) .................. 144
10.8.36 CT16Bn PWMmN Dead-band Period register (CT16Bn_PWMmNDB) (n=0).................. 145
10.8.37 CT16Bn PWMmN Dead-band Period register (CT16Bn_PWMmNDB) (n=3,4)............... 145
1
1
11
1
1
WATCHDOG TIMER (WDT)........................................................................................................ 146
11.1 OVERVIEW................................................................................................................................... 146
11.2 BLOCK DIAGRAM....................................................................................................................... 147
11.3 WDT REGISTERS......................................................................................................................... 148
11.3.1 Watchdog Configuration register (WDT_CFG)..................................................................... 148
11.3.2 Watchdog Timer Constant register (WDT_TC)...................................................................... 148
11.3.3 Watchdog Feed register (WDT_FEED)................................................................................. 149
1
1
12
2
2
REAL-TIME CLOCK (RTC) ......................................................................................................... 150
12.1 OVERVIEW................................................................................................................................... 150
12.2 FEATURES.................................................................................................................................... 150
12.3 FUNCTIONAL DESCRIPTION.................................................................................................... 150
12.3.1 INTRODUCTION................................................................................................................... 150
12.3.2 RESET RTC REGISTERS....................................................................................................... 150
12.3.3 RTC FLAG ASSERTION ........................................................................................................ 150
12.3.4 RTC OPERATION.................................................................................................................. 150
12.4 BLOCK DIAGRAM....................................................................................................................... 151
12.5 RTC REGISTERS .......................................................................................................................... 152

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
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12.5.1 RTC Control register (RTC_CTRL) ....................................................................................... 152
12.5.2 RTC Clock Source Select register (RTC_CLKS).................................................................... 152
12.5.3 RTC Interrupt Enable register (RTC_IE)............................................................................... 152
12.5.4 RTC Raw Interrupt Status register (RTC_RIS) ...................................................................... 152
12.5.5 RTC Interrupt Clear register (RTC_IC)................................................................................. 152
12.5.6 RTC Second Counter Reload Value register (RTC_SECCNTV)............................................ 153
12.5.7 RTC Second Count register (RTC_SECCNT) ........................................................................ 153
1
1
13
3
3
SPI...................................................................................................................................................... 154
13.1 OVERVIEW................................................................................................................................... 154
13.2 FEATURES.................................................................................................................................... 154
13.3 PIN DESCRIPTION....................................................................................................................... 154
13.4 INTERFACE DESCRIPTION ....................................................................................................... 155
13.4.1 SPI .......................................................................................................................................... 155
13.4.2 COMMUNICATION FLOW................................................................................................... 156
13.4.2.1 SINGLE-FRAME........................................................................................................... 156
13.4.2.2 MULTI-FRAME ............................................................................................................ 156
13.5 AUTO-SEL..................................................................................................................................... 156
13.6 SPI REGISTERS ............................................................................................................................ 157
13.6.1 SPI n Control register 0 (SPIn_CTRL0) (n=0,1)................................................................... 157
13.6.2 SPI n Control register 1 (SPIn_CTRL1) (n=0,1)................................................................... 158
13.6.3 SPI n Clock Divider register (SPIn_CLKDIV) (n=0,1) ......................................................... 158
13.6.4 SPI n Status register (SPIn_STAT) (n=0,1)............................................................................ 158
13.6.5 SPI n Interrupt Enable register (SPIn_IE) (n=0,1)................................................................ 159
13.6.6 SPI n Raw Interrupt Status register (SPIn_RIS) (n=0,1)....................................................... 159
13.6.7 SPI n Interrupt Clear register (SPIn_IC) (n=0,1).................................................................. 160
13.6.8 SPI n Data register (SPIn_DATA) (n=0,1)............................................................................ 160
13.6.9 SPI n Data Fetch register (SPIn_DF) (n=0,1)....................................................................... 161
13.6.10 SPI n DMA Control register (SPIn_DMACTRL) (n=0)..................................................... 161
13.6.11 SPI n DMA Number of Data Transfer register (SPIn_DMACNT) (n=0)........................... 161
13.6.12 SPI n DMA Number of Half Data Transfer register (SPIn_DMAHTCNT) (n=0) ............. 161
13.6.13 SPI n DMA Current Transfer Data Counter register (SPIn_CURCNT) (n=0) ................. 162
1
1
14
4
4
I2C...................................................................................................................................................... 163
14.1 OVERVIEW................................................................................................................................... 163
14.2 FEATURES.................................................................................................................................... 163
14.3 PIN DESCRIPTION....................................................................................................................... 163
14.4 WAVE CHARACTERISTICS....................................................................................................... 164
14.5 I2C MASTER MODES .................................................................................................................. 165
14.5.1 MASTER TRANSMITTER MODE.......................................................................................... 165

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
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14.5.2 MASTER RECEIVER MODE................................................................................................. 165
14.5.3 ARBITRATION ....................................................................................................................... 165
14.6 I2C SLAVE MODES...................................................................................................................... 166
14.6.1 SLAVE TRANSMITTER MODE ............................................................................................. 166
14.6.2 SLAVE RECEIVER MODE .................................................................................................... 166
14.7 I2C REGISTERS............................................................................................................................ 167
14.7.1 I2C n Control register (I2Cn_CTRL) (n=0,1)........................................................................ 167
14.7.2 I2C n Status register (I2Cn_STAT) (n=0,1)........................................................................... 168
14.7.3 I2C n TX Data register (I2Cn_TXDATA) (n=0,1) ................................................................. 169
14.7.4 I2C n RX Data register (I2Cn_RXDATA) (n=0,1)................................................................. 169
14.7.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0,1)................................................. 169
14.7.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0,1) ........................................ 169
14.7.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0,1)......................................................... 169
14.7.8 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0,1)........................................................... 170
14.7.9 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0,1) .................................................... 170
1
1
15
5
5
UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART).................... 171
15.1 OVERVIEW................................................................................................................................... 171
15.2 FEATURES.................................................................................................................................... 171
15.3 PIN DESCRIPTION....................................................................................................................... 171
15.4 BLOCK DIAGRAM....................................................................................................................... 172
15.5 BAUD RATE CALCULATION .................................................................................................... 173
15.6 AUTO-BAUD FLOW .................................................................................................................... 174
15.6.1 AUTO-BAUD.......................................................................................................................... 174
15.6.2 AUTO-BAUD MODES ........................................................................................................... 175
15.7 UART REGISTERS....................................................................................................................... 177
15.7.1 UART n Receiver Buffer register (UARTn_RB) (n=0,1,2,3).................................................. 177
15.7.2 UART n Transmitter Holding register (UARTn_TH) (n=0,1,2,3).......................................... 177
15.7.3 UART n Divisor Latch LSB registers (UARTn_DLL) (n =0,1,2,3)........................................ 177
15.7.4 UART n Divisor Latch MSB register (UARTn_DLM) (n=0,1,2,3) ........................................ 178
15.7.5 UART n Interrupt Enable register (UARTn_IE) (n=0,1,2,3) ................................................. 178
15.7.6 UART n Interrupt Identification register (UARTn_II) (n=0,1,2,3)........................................ 178
15.7.7 UART n Line Control register (UARTn_LC) (n=0,1,2,3) ...................................................... 179
15.7.8 UART n Line Status register (UARTn_LS) (n=0,1,2,3).......................................................... 180
15.7.9 UART n Scratch Pad register (UARTn_SP) (n=0,1,2,3)........................................................ 181
15.7.10 UART n Auto-baud Control register (UARTn_ABCTRL) (n=0,1,2,3)............................... 181
15.7.11 UART n Fractional Divider register (UARTn_FD) (n=0,1,2,3)........................................ 182
15.7.12 UART n Control register (UARTn_CTRL) (n=0,1,2,3)...................................................... 182
1
1
16
6
6
I2S ...................................................................................................................................................... 184

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version 1.1
16.1 OVERVIEW................................................................................................................................... 184
16.2 FEATURES.................................................................................................................................... 184
16.3 PIN DESCRIPTION....................................................................................................................... 184
16.4 BLOCK DIAGRAM....................................................................................................................... 185
16.4.1 I2S CLCOK CONTROL.......................................................................................................... 185
16.4.2 I2S BLOCK DIAGRAM .......................................................................................................... 185
16.5 FUNCTIONAL DESCRIPTION.................................................................................................... 186
16.5.1 I2S OPERATION.................................................................................................................... 186
16.5.2 I2S FIFO OPERAION............................................................................................................ 188
16.5.2.1 MONO............................................................................................................................ 188
16.5.2.2 STEREO......................................................................................................................... 188
16.6 I2S REGISTERS............................................................................................................................. 189
16.6.1 I2S n Control register (I2Sn_CTRL) (n=0,1)......................................................................... 189
16.6.2 I2S n Clock register (I2Sn_CLK) (n=0,1).............................................................................. 190
16.6.3 I2S n Status register (I2Sn_STATUS) (n=0,1) ....................................................................... 190
16.6.4 I2S n Interrupt Enable register (I2S_IE) (n=0,1)................................................................... 191
16.6.5 I2S n Raw Interrupt Status register (I2S_RIS) (n=0,1).......................................................... 191
16.6.6 I2S n Interrupt Clear register (I2S_IC) (n=0,1) .................................................................... 192
16.6.7 I2S n RXFIFO register (I2S_RXFIFO) (n=0,1)..................................................................... 192
16.6.8 I2S n TXFIFO register (I2S_TXFIFO) (n=0,1)...................................................................... 192
1
1
17
7
7
4X40/6X38/7X37/8X36 LCD DRIVER........................................................................................... 193
17.1 OVERVIEW................................................................................................................................... 193
17.2 FEATURES.................................................................................................................................... 194
17.3 PIN DESCRIPTION....................................................................................................................... 194
17.4 LCD CHANNEL CONTROL......................................................................................................... 195
17.5 LCD BIAS GENERATOR ............................................................................................................. 196
17.6 LCD INTERRUPT ......................................................................................................................... 196
17.7 LCD TIMING CONTROL ............................................................................................................. 197
17.8 LCD WAVEFORM........................................................................................................................ 198
17.9 SINGLE LCDFRAME FUNCTION.............................................................................................. 203
17.10 LCD DISPLAY MEMORY MAP .............................................................................................. 204
17.11 LCD REGISTERS...................................................................................................................... 205
17.11.1 LCD Control register (LCD_CTRL)................................................................................... 205
17.11.2 LCD Frame Counter Control register (LCD_FCC)........................................................... 206
17.11.3 LCD Raw Interrupt Status register (LCD_RIS) ................................................................. 207
17.11.4 LCD SEG Select register (LCD_SEGSEL1)....................................................................... 207
17.11.5 LCD SEG Select register (LCD_SEGSEL2)....................................................................... 207
17.11.6 LCD SEG Memory register 0 (LCD_SEGM0)................................................................... 208
17.11.7 LCD SEG Memory register 1 (LCD_SEGM1)................................................................... 208

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 Version 1.1
17.11.8 LCD SEG Memory register 2 (LCD_SEGM2)................................................................... 208
17.11.9 LCD SEG Memory register 3 (LCD_SEGM3)................................................................... 208
17.11.10 LCD SEG Memory register 3 (LCD_SEGM4)................................................................... 209
17.11.11 LCD SEG Memory register 3 (LCD_SEGM5)................................................................... 209
17.11.12 LCD SEG Memory register 3 (LCD_SEGM6)................................................................... 209
17.11.13 LCD SEG Memory register 3 (LCD_SEGM7)................................................................... 209
17.11.14 LCD SEG Memory register 3 (LCD_SEGM8)................................................................... 210
17.11.15 LCD SEG Memory register 3 (LCD_SEGM9)................................................................... 210
1
1
18
8
8
EXTERNAL BUS INTERFACE (EBI).......................................................................................... 211
18.1 OVERVIEW................................................................................................................................... 211
18.2 FEATURES.................................................................................................................................... 211
18.3 PIN DESCRIPTION....................................................................................................................... 211
18.4 BLOCK DIAGRAM....................................................................................................................... 212
18.5 INTERFACE DESCRIPTION ....................................................................................................... 213
18.5.1 Non-multiplexed N-bit Address 8-bit Data Mode (AND8)...................................................... 213
18.5.2 Non-multiplexed N-bit Address 16-bit Data Mode (AND16).................................................. 214
18.5.3 Multiplexed N-bit Address 16-bit Data Mode (AND16ALE) .................................................. 215
18.5.4 Write Buffer and EBI Status ................................................................................................... 216
18.5.5 Bus Turn-around and Idle Cycles........................................................................................... 216
18.5.6 AHB Transaction Width Conversion...................................................................................... 217
18.5.7 EBI Bank Access..................................................................................................................... 219
18.5.8 EBI Ready............................................................................................................................... 219
18.6 8080 MODE DMA-CONTROLLED TFT-LCD ............................................................................ 219
18.6.1 DMA TIMING FLOW............................................................................................................. 220
18.6.2 DMA DATA FORMAT............................................................................................................ 221
18.7 EBI REGISTERS............................................................................................................................ 223
18.7.1 EBI Control register (EBI_CTRL).......................................................................................... 223
18.7.2 EBI Address Length Control register (EBI_ALCTRL)........................................................... 224
18.7.3 EBI Status register (EBI_STATUS)........................................................................................ 224
18.7.4 EBI Address Timing register n (EBI_TADDRn) n=0~3......................................................... 225
18.7.5 EBI Read Timing register n (EBI_TREADn) n=0~3.............................................................. 225
18.7.6 EBI Write Timing register n (EBI_TWRITEn) n=0~3............................................................ 225
18.7.7 EBI Polarity register n (EBI_PRn) n=0~3............................................................................. 226
18.7.8 EBI Interrupt Enable register (EBI_IE)................................................................................. 226
18.7.9 EBI Interrupt Flag register (EBI_RIS)................................................................................... 227
18.7.10 EBI Interrupt Clear register (EBI_IC)............................................................................... 227
18.7.11 EBI DMA Control register (EBI_DMACTRL) ................................................................... 228
18.7.12 EBI DMA Number of Data Transfer register (EBI_DMACNT)......................................... 228
18.7.13 EBI DMA Number of Half Data Transfer register (EBI_DMAHTCNT)............................ 228

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version 1.1
18.7.14 EBI DMA Current Transfer Data Counter register (EBI_CURCNT)................................ 229
1
1
19
9
9
CYCLIC REDUNDANCY CHECK (CRC)................................................................................... 230
19.1 OVERVIEW................................................................................................................................... 230
19.2 FEATURES.................................................................................................................................... 230
19.3 CRC REGISTERS.......................................................................................................................... 231
19.3.1 CRC Control register (CRC_CTRL)....................................................................................... 231
19.3.2 CRC Data register (CRC_DATA)........................................................................................... 231
2
2
20
0
0
USB FS DEVICE INTERFACE...................................................................................................... 232
20.1 OVERVIEW................................................................................................................................... 232
20.2 FEATURES.................................................................................................................................... 232
20.3 PIN DESCRIPTION....................................................................................................................... 232
20.4 BLOCK DIAGRAM....................................................................................................................... 233
20.5 USB SRAM ACCESS .................................................................................................................... 233
20.6 USB MACHINE............................................................................................................................. 233
20.7 USB INTERRUPT.......................................................................................................................... 234
20.8 USB ENUMERATION .................................................................................................................. 235
20.9 USB REGISTERS .......................................................................................................................... 236
20.9.1 USB Interrupt Enable Register (USB_INTEN) ...................................................................... 236
20.9.2 USB Interrupt Event Status Register (USB_INSTS)............................................................... 237
20.9.3 USB Interrupt Event Status Clear Register (USB_INSTSC).................................................. 239
20.9.4 USB Device Address Register (USB_ADDR)......................................................................... 240
20.9.5 USB Configuration Register (USB_CFG).............................................................................. 240
20.9.6 USB Signal Control Register (USB_SGCTL)......................................................................... 241
20.9.7 USB Endpoint 0 Control Register (USB_EP0CTL) ............................................................... 241
20.9.8 USB Endpoint n Control Register (USB_EPnCTL, n = 1 ~ 6)............................................... 242
20.9.9 USB Endpoint Data Toggle Register (USB_EPTOGGLE) .................................................... 242
20.9.10 USB Endpoint n Buffer Offset Register (USB_EPnBUFOS, n = 1 ~ 6)............................. 242
20.9.11 USB Frame Number Register (USB_FRMNO).................................................................. 243
20.9.12 USB PHY Parameter Register (USB_PHYPRM)............................................................... 243
20.9.13 USB PHY Parameter Register 2(USB_PHYPRM2)........................................................... 243
20.9.14 PS/2 Control Register (USB_PS2CTL) .............................................................................. 243
20.9.15 USB Read/Write Address Register (USB_RWADDR)........................................................ 244
20.9.16 USB Read/Write Data Register (USB_RWDATA).............................................................. 244
20.9.17 USB Read/Write Status Register (USB_RWSTATUS)........................................................ 244
20.9.18 USB Read/Write Address Register2 (USB_RWADDR2).................................................... 245
20.9.19 USB Read/Write Data Register2 (USB_RWDATA2).......................................................... 245
20.9.20 USB Read/Write Status Register 2(USB_RWSTATUS2).................................................... 245
2
2
21
1
1
FLASH............................................................................................................................................... 246

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 Version 1.1
21.1 OVERVIEW................................................................................................................................... 246
21.2 EMBEDDED FLASH MEMORY.................................................................................................. 246
21.3 FEATURES.................................................................................................................................... 246
21.4 ORGANIZATION.......................................................................................................................... 247
21.5 READ ............................................................................................................................................. 247
21.6 PROGRAM/ERASE....................................................................................................................... 247
21.7 EMBEDDED BOOT LOADER ..................................................................................................... 247
21.8 FLASH MEMORY CONTROLLER (FMC).................................................................................. 248
21.8.1 CODE SECURITY (CS).......................................................................................................... 248
21.8.2 PROGRAM FLASH MEMORY............................................................................................... 249
21.8.3 ERASE .................................................................................................................................... 249
21.8.3.1 PAGE ERASE................................................................................................................ 249
21.8.3.2 MASS ERASE................................................................................................................ 249
21.9 READ PROTECTION.................................................................................................................... 249
21.10 HW CHECKSUM....................................................................................................................... 249
21.11 FMC REGISTERS...................................................................................................................... 250
21.11.1 Flash Low Power Control register (FLASH_LPCTRL)..................................................... 250
21.11.2 Flash Status register (FLASH_STATUS) ........................................................................... 250
21.11.3 Flash Control register (FLASH_CTRL)............................................................................. 250
21.11.4 Flash Data register (FLASH_DATA)................................................................................. 251
21.11.5 Flash Address register (FLASH_ADDR) ........................................................................... 251
21.11.6 Flash Checksum register (FLASH_CHKSUM).................................................................. 251
21.11.7 Flash Checksum register 1 (FLASH_CHKSUM1)............................................................. 251
2
2
22
2
2
SERIAL-WIRE DEBUG (SWD)..................................................................................................... 253
22.1 OVERVIEW................................................................................................................................... 253
22.2 FEATURES.................................................................................................................................... 253
22.3 PIN DESCRIPTION....................................................................................................................... 253
22.4 DEBUG NOTE............................................................................................................................... 253
22.4.1 LIMITATIONS........................................................................................................................ 253
22.4.2 DEBUG RECOVERY.............................................................................................................. 253
22.4.3 INTERNAL PULL-UP/DOWN RESISTORS on SWD PINS................................................... 254
2
2
23
3
3
DEVELOPMENT TOOL ................................................................................................................ 255
23.1 SN-LINK-V3.................................................................................................................................. 256
23.2 SN32F280 STARTER-KIT ............................................................................................................ 257
2
2
24
4
4
ELECTRICAL CHARACTERISTIC............................................................................................ 258
24.1 ABSOLUTE MAXIMUM RATING.............................................................................................. 258
24.2 ELECTRICAL CHARACTERISTIC............................................................................................. 258
24.3 CHARACTERISTIC GRAPHS ..................................................................................................... 260

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 Version 1.1
2
2
25
5
5
FLASH ROM PROGRAMMING PIN........................................................................................... 261
2
2
26
6
6
PACKAGE INFORMATION ......................................................................................................... 262
26.1 LQFP 80 PIN .................................................................................................................................. 262
26.2 LQFP 64 PIN .................................................................................................................................. 263
26.3 LQFP 48 PIN .................................................................................................................................. 264
2
2
27
7
7
MARKING DEFINITION............................................................................................................... 265
27.1 INTRODUCTION.......................................................................................................................... 265
27.2 MARKING INDETIFICATION SYSTEM.................................................................................... 265
27.3 MARKING EXAMPLE ................................................................................................................. 266
27.4 DATECODE SYSTEM.................................................................................................................. 267

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 Version 1.1
1
1
1
PRODUCT OVERVIEW
1.1 FEATURES

Memory configuration

Timer
128KB on-chip Flash programming memory.
3 16-bit timer support up-counting, down-counting, and
32KB SRAM.
center-aligned mode.
4KB Boot ROM
3 16-bit timers support up-counting mode.
28 sets PWM

Operation Frequency up to 48MHz
8 sets inverse PWM with programmable dead-band
PCLK up to 96MHz

Interrupt sources
ARM Cortex-M0 built-in Nested Vectored Interrupt

Working voltage 2.5V ~ 5.5V
Controller (NVIC).

12-bit SAR ADC with 12 external and 3 internal

I/O pin configuration
channels, and 4-level Int. Ref. Voltage
Up to 74 General Purpose I/O (GPIO) pins with
16 external ADC input
configurable pull-up resistors.
1 internal battery measurement
GPIO pins can be used as edge and level sensitive
2 internal channels from OPA0 and OPA1 outputs.
interrupt sources.
4-level internal reference voltage source (VDD, 4.5V,
Up to 6 High-current (100 mA) output sink pins: P0.0,
3V, 2V)
P0.1, P0.2, P0.3, P1.12, P1.13
All IO 20mA driving/sinking current

3 Rail to Rail Comparators
4 GPIO pins with configurable pull-down resistors:
Internal reference voltage source 3V/2V/1.5V
P3.10, P3.11, P3.12, P3.13
Programmable 16-level internal ref. voltage divider
3 external negative inputs

Programmable Watchdog Timer (WDT)
3 external positive inputs
Programmable watchdog frequency with watchdog
clock source and divider.

2 OPA
Internal reference voltage source 3V/2V/1.5V shared

System tick timer
with CMP
The 24-bit SysTick timer clock source is fixed to the
system clock, and is intended to generate a fixed 10-

Interface
ms interrupt.
-Two I2C controllers supporting I2C-bus specification
with multiple address recognition.

Real-Time Clock (RTC)
-Four UART controllers with fractional baud rate
generation.

LVD with separate thresholds
-Two SPI controllers.
Reset: 1.35V for VCORE 1.5V
- EBI (8080 included) interface
Reset: 2.7V/3.0V/3.6V for VDD
- Two I2S controllers with mono and stereo audio data
Interrupt: 2.7V/3.0V/3.6V for VDD
supported, MSB justified data format supported, and
can operate as either master or slave.

Fcpu (Instruction cycle)
FCPU = FHCLK = FSYSCLK/1, FSYSCLK /2, FSYSCLK /4, …,

System clocks
FSYSCLK /128
-External high clock: Crystal type 10MHz~25MHz
-External low clock: Crystal type 32.768 KHz

Operating modes
-Internal high clock: RC type 12 MHz
Normal, Sleep, Deep-sleep
-Internal low clock: RC type 32 KHz
-PLL allows CPU operation up to the maximum CPU

Cyclic Redundancy Check (CRC)
rate without the need for a high-frequency crystal.
CRC-16
-Clock output function which can reflect the internal
CRC-16-CCCITT
high/low RC oscillator, HCLK, PLL output, and
CRC-32
external low clock.

Serial Wire Debug (SWD)

In-Circuit Programming (ICP) supported

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 Version 1.1
Features Selection Table
Chip
ROM
RAM
FCPU
(Max
MHz)
USB
16-Bit
Timer
UART
SPI
I2C
I2S
PWM
12-bit
ADC
CMP
OPA
LCD
TK
EBI
GPIO
Package
SN32F289F
128KB
32KB
48
V
6
4
2
2
2
28+8
16+3
3
2
4x40
6x38
7x37
8x36
22
V
74
LQFP80
SN32F288F
128KB
32KB
48
V
6
4
2
2
2
28+8
16+3
3
2
4x35
6x33
7x32
8x31
22
V
58
LQFP64
SN32F287F
128KB
32KB
48
V
6
4
2
2
2
28+8
10+3
3
2
4x21
22
V
42
LQFP48

LCD driver

22 Capacitive Touch Keys
Support R-type
Up to 8 com

3.3V Regulator output
4x40 or 6x38 or 7x37 or 8x36 dots
Driving current 60mA
1/3 bias voltage
Power for USB D+ internal pull-up resistor.
Adjustable VLCD Voltage: 0.5xVcc~Vcc
Can be IO power for P0.12~P0.15, P3.0~P3.6,
Support 1/4 duty, 1/6 duty, 1/7 duty, and 1/8 duty
P1.6~P1.11. (3.3V IOs)
LCD pin shared with I/O

Package (Chip form support)

Full Speed USB 2.0
LQFP80/64/48 pin
3.3v regulator output for D+ internal 1.5k pull-up
resistor.
Supports one Full speed USB device address.
Supports PS/2 mode.
One control EP and 6 configurable INT/BULK
Endpoints.
EP0 supports 64-byte FIFO depth.
Programmable EP1~EP6 FIFO depth.
Total 7 endpoints share 512-byte USB RAM.

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 18 Version 1.1
1.2 SYSTEM BLOCK DIAGRAM
TEST/DEBUG
INTERFACE
PIO0_0~19
PIO1_0~19
PIO2_0~15
PIO3_0~19
SWDIO
SWCLK
CT16B5_PWM[3:0]
CT16B5_CAP0
URXD0
UTXD0
URXD2
UTXD2
SCL0
SDA0
URXD3
UTXD3
/RESET
ARM
CORTEX-M0
FLASH ROM
128KB SRAM 32KB
SYS
POWER CONTROL/
SYSTEM FUNCTIONS
UART 3
I2C 0
UART 0
UART 2
UART 1
POWER
REGULATOR 1
LVD
Controls
AHB-LITE BUS
AHB TO APB
BRIDGE
APB BUS
RTC
GPIO
VCORE
VDD 2.5V~5.5V
I2C 1
SCL1
SDA1
URXD1
UTXD1
SPI 0
SCK10
SEL0
SDI0
SDO0
FLASH ROM
(BOOT LOADER)
4KB
AIN0~AIN15
PMU
COM0~COM7
SEG0~SEG39 LCD
WDT
16-bit TIMER 5 with PWM
ADC
CT16B4_PWM[1:0]
CT16B4_PWM[1:0]N
CT16B4_CAP0
16-bit TIMER 4 with PWM
CT16B3_PWM[1:0]
CT16B3_PWM[1:0]N
CT16B3_CAP0
16-bit TIMER 3 with PWM
CT16B2_PWM[3:0]
CT16B2_CAP0
16-bit TIMER 2 with PWM
CT16B1_PWM[11:0]
CT16B1_CAP0
16-bit TIMER 1 with PWM
CT16B0_PWM[3:0]
CT16B0_PWM[3:0]N
CT16B0_CAP0
16-bit TIMER 0 with PWM
I2SBCLK1
I2SWS1
I2SDIN1
I2SDOUT1
I2SMCLK1
I2SBCLK0
I2SWS0
I2SDIN0
I2SDOUT0
I2SMCLK0
I2S0
SCK1
SEL1
SDI1
SDO1 SPI 1
CMP 0
CMP 1
CM1P[2:0]
CM1N[2:0]
CM1O
CMP 2
CM2P[2:0]
CM2N[2:0]
CM2O
CM0P[2:0]
CM0N[2:0]
CM0O I2S1
OP0P
OP0N
OP0O
OP1P
OP1N
OP1O
OPA0
OPA1
HXTALOUT,
LXTALOUT
HXTALIN,
LXTALIN
CLKOUT
CLOCK GENERATION
ILRC
32KHz IHRC 12MHz
Clocks
USB D+
D-

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 19 Version 1.1
1.3 CLOCK GENERATION BLOCK DIAGRAM
CLKOUT
PLL
IHRC
12MHz
ILRC
32KHz
IHRC
ILRC
PLLCLKout
SYSCLKSEL
CLKOUTSEL
WDT
Clock Prescaler
/1, 2, 4, 8, 16, 32
WDT_PCLK
SPIn_PCLK
HCLK
AHB clock for SPIn
SPInCLKEN
n=0, 1
WDT
register block
WDT
clock source
SPIn
register block
SPIn
clock source
AHB clock for WDT
AHB clock for AHB to APB bridge, to AHB
matrix, to Cortex-M0 FCLK, HCLK, and
System Timer, to SYS, and to PMU
AHB clock for GPIO
LXTALOUT
LXTALIN Low speed
Crystal
oscillator
32.768KHz
32.768KHz
GPIO block
PLLCLKout
RTCCLKSEL
ILRC
32.768KHz
ADC
Clock Prescaler
/1,2,4,8,16
ADC_PCLK
AHB clock for ADC
ADCCLKEN ADC
register block
ADC
clock source
I2Sn
Clock Prescaler
/1,2, 3, 4,8,16
I2Sn_PCLK
AHB clock for I2Sn
I2SnCLKEN
n=0,1 I2Sn
register block
I2Sn
clock source
I2Cn_PCLK
AHB clock for I2Cn
I2CnCLKEN
n=0,1
I2Cn
register block
I2Cn
clock source
UARTn_PCLK
AHB clock for UARTn
UARTnCLKEN
n=0,1,2,3
UARTn
register block
UARTn
clock source
AHB clock for SRAM SRAM block
AHB clock for FLASH
FLASH block
Max 16MHz
CLKOUT
Prescaler
/1,2,4,…,128
WDTCLKEN
HCLK
IHRC
ILRC
32.768KHz
RTC_PCLK RTC
register block
RTC
clock source
AHB clock for RTC
RTCCLKEN
LCDCLK
ILRC
32.768KHz
LCD_PCLK LCD
register block
LCD
clock source
AHB clock for LCD
LCDCLKEN
PFPA blcok AHB clock for PFPA
CMP_PCLK
AHB clock for CMP
CMP
register block
CMP
clock source
CMPCLKEN
OPA_PCLK
AHB clock for OPA
OPA
register block
OPA
clock source
OPACLKEN
EBI_PCLK
AHB clock for EBI
EBI
register block
EBI
clock source
EBICLKEN
CT16Bn_PCLK
AHB clock for CT16Bn
CT16BnCLKEN
n=5 CT16Bn
register block
CT16Bn
clock source
CT16BnCLKSEL
n=5
SYSCLK AHB Prescaler
/1,2,4,…,128 HCLK
AHBCP
SYS
Prescaler
/1 or /1.5
DIV1P5
PLL_VCO
CT16Bn_PCLK
AHB clock for CT16Bn
CT16BnCLKEN
n=0,1,2,3,4 CT16Bn
register block
CT16Bn
clock source
CT16BnCLKSEL
n=0,1,2,3,4
PLL_VCO
32.768KHz
CRC_PCLK
AHB clock for CRC
CRC
register block
CRC
clock source
CRCCLKEN
HXTALOUT
HXTALIN HXTAL
1MHz~25MHz
EHS Oscillator
PLLCLKSEL
PLL_VCO USB SIE
USB
clock source
USB
register block USBCLKEN
AHB clock for USB
USB_PCLK = 48MHz
48MHz if USB is enabled

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 20 Version 1.1
1.4 PIN ASSIGNMENT
SN32F289F (LQFP 80 pins)
VDD
VSS
P0.9/16B2_CAP0/A25
P0.8/A24
P1.5/COM3/OP0O/A23
P1.4/SEG16/OP0P/A22
P1.3/SEG39/OP0N/BOOT/A21
P0.11/SEG38/OP1O/CT23/A20
P0.10/SEG37/OP1P/CT22/A19
P1.2/SEG9/OP1N/A18
P1.1/SEG8/CT21/A17
P1.0/SEG7/CT20/A16
P1.18/SEG36/A15
P1.17/SEG35/A14
P1.16/SEG34/A13
P3.15/SEG33/A12
P3.14/SEG32/A11
P1.11/COM7/SEG31/A10
P1.10/COM6/SEG30/A9
P1.6/COM5/SEG29/A8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
CS0/16B1_CAP0/P3.8
1
●
60
P1.7/COM4/SEG28/A7
CS1/16B0_CAP0/P3.9
2
59
P1.8/SEG17/CSOUT/A6
LXIN/P3.10
3
58
P3.6/SWCLK
LXOUT/P3.11
4
57
VDDIO1
WE/XIN/P3.12
5
56
P1.9/A5
OE/XOUT/P3.13
6
55
P3.5/SWDIO
RESET/P3.7
7
54
D+
CS2/P3.16
8
53
D-
CS3/P3.17
9
SN32F289F
52
P3.2/COM2/CT17/A2
ARDY/P3.18
10
51
P3.1/COM1/CT16/A1
CM0N0/SEG18/AIN10/P2.10
11
50
P3.0/COM0/CLKOUT/A0
CM0N1/SEG19/AIN11/P2.11
12
49
P0.12/SEG27
CM2N0/SEG20/AIN12/P2.12
13
48
P0.13/SEG26/16B4_CAP0
CM2P0/SEG21/AIN13/P2.13
14
47
P0.14/SEG25
AD8/16B3_CAP0/CM2P2/P0.4
15
46
P0.15/SEG24
AD9/CM2N2/P0.5
16
45
P0.16/16B5_CAP0
CT0/CM0N2/AIN0/P2.0
17
44
P0.17/UB
CT1/CM0P0/SEG0/AIN1/P2.1
18
43
P0.18/LB
CT2/CM1N2/SEG1/AIN2/P2.2
19
42
P0.19
CT3/CM1P0/SEG2/AIN3/P2.3
20
41
P3.19
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P0.6
CM1P2/P0.7
AD10/CT4/CM1N0/AIN4/P2.4
AD11/CT5/CM1N1/AIN5/P2.5
AD12/CT6/CM1P1/SEG3/AIN6/P2.6
AD13/CT7/CM2N1/SEG4/AIN7/P2.7
CM0P1/SEG22/AIN14/P2.14
CT8/CM0P2/SEG23/AIN15/P2.15
AD14/CT9/CM2P1/SEG5/AIN8/P2.8
AD15/CT10/SEG6/AIN9/P2.9
AD0/CT11/P0.0
AD1/SEG10/P0.1
AD2/CT12/SEG11/P0.2
AD3/P0.3
VREG33
AD4/CT13/SEG12/P1.12
AD5/CT14/SEG13/P1.13
AD6/CT15/SEG14/P1.14
AD7/CSCAP/SEG15/P1.15
ALE/P1.19
Note: SONiX provide Boot loader to check the status of P1.3 (BOOT pin) during boot procedure. If BOOT
pin is Low during Boot procedure, MCU will execute code in Boot loader instead of User code. We
strongly recommended NOT using BOOT pin as output pin to drive the LED, otherwise, the BOOT pin
status may be low during boot procedure.