Holtek HT46R003B User manual

Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Revision: V1.00 Date: June 19, 2014June 19, 2014

Rev. 1.00 2 June 19, 2014 Rev. 1.00 3 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Table of Contents
Features............................................................................................................ 5
CPU Features ......................................................................................................................... 5
Peripheral Features................................................................................................................. 5
General Description ........................................................................................ 6
Block Diagram.................................................................................................. 6
Pin Assignment................................................................................................ 6
Pin Description ................................................................................................ 7
Absolute Maximum Ratings............................................................................ 8
D.C. Characteristics......................................................................................... 8
A.C. Characteristics......................................................................................... 9
A/D Converter Characteristics........................................................................ 9
Power-on Reset Characteristics................................................................... 10
System Architecture...................................................................................... 10
Clocking and Pipelining......................................................................................................... 10
Program Counter – PC...........................................................................................................11
Stack ..................................................................................................................................... 12
Arithmetic and Logic Unit – ALU ........................................................................................... 12
Program Memory ........................................................................................... 13
Structure................................................................................................................................ 13
Special Vectors ..................................................................................................................... 13
Look-up Table........................................................................................................................ 13
Table Program Example........................................................................................................ 14
RAM Data Memory ......................................................................................... 15
Structure................................................................................................................................ 15
Special Purpose Data Memory ............................................................................................. 15
Special Function Registers........................................................................... 17
Indirect Addressing Registers – IAR0, IAR1 ......................................................................... 17
Memory Pointers – MP0, MP1 .............................................................................................. 17
Accumulator – ACC............................................................................................................... 18
Program Counter Low Register – PCL.................................................................................. 18
Status Register – STATUS.................................................................................................... 18
System Control Registers – CTRL0, CTRL1......................................................................... 20
Oscillator ........................................................................................................ 21
System Oscillator Overview .................................................................................................. 21
System Clock Congurations ................................................................................................ 21
Internal RC Oscillator – HIRC ............................................................................................... 21
Internal 12kHz Oscillator – LIRC........................................................................................... 21

Rev. 1.00 2 June 19, 2014 Rev. 1.00 3 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Power Down Mode and Wake-up.................................................................. 22
Power Down Mode................................................................................................................ 22
Standby Current Considerations ........................................................................................... 22
Wake-up................................................................................................................................ 22
Watchdog Timer............................................................................................. 24
Watchdog Timer Clock Source.............................................................................................. 24
Watchdog Timer Control Registers ....................................................................................... 24
Watchdog Timer Operation ................................................................................................... 25
Reset and Initialization.................................................................................. 26
Reset Functions .................................................................................................................... 26
Reset Initial Conditions ......................................................................................................... 28
Input/Output Ports ......................................................................................... 30
Port A Wake-up ..................................................................................................................... 31
I/O Port Control Registers ..................................................................................................... 31
Pin-shared Functions ............................................................................................................ 32
I/O Pin Structures.................................................................................................................. 33
Programming Considerations................................................................................................ 34
Timer/Event Counter ..................................................................................... 35
Conguring the Timer/Event Counter Input Clock Source .................................................... 35
Timer Register – TMR........................................................................................................... 36
Timer Control Register – TMRC............................................................................................ 36
Timer Mode ........................................................................................................................... 37
Event Counter Mode ............................................................................................................. 38
Pulse Width Capture Mode ................................................................................................... 38
Prescaler ............................................................................................................................... 39
PFD Function ........................................................................................................................ 40
I/O Interfacing........................................................................................................................ 40
Programming Considerations................................................................................................ 40
Timer Program Example ....................................................................................................... 41
Time Base ............................................................................................................................. 42
Pulse Width Modulator.................................................................................. 42
PWM Operation..................................................................................................................... 42
6+2 PWM Mode .................................................................................................................... 42
7+1 PWM Mode .................................................................................................................... 43
PWM Output Control ............................................................................................................. 44
Analog to Digital Converter ......................................................................... 45
A/D Overview ........................................................................................................................ 45
A/D Converter Data Registers – ADRL, ADRH ..................................................................... 45
A/D Converter Control Registers – ADCR, ACSR, ADPCR .................................................. 46
A/D Operation ....................................................................................................................... 48
A/D Input Pins ....................................................................................................................... 49
Summary of A/D Conversion Steps....................................................................................... 49

Rev. 1.00 4 June 19, 2014 Rev. 1.00 5 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Programming Considerations................................................................................................ 50
A/D Transfer Function ........................................................................................................... 50
A/D Programming Example................................................................................................... 51
Interrupts ........................................................................................................ 53
Interrupt Register .................................................................................................................. 53
Interrupt Operation ................................................................................................................ 54
Interrupt Priority..................................................................................................................... 55
External Interrupt................................................................................................................... 56
Timer/Event Counter Interrupt............................................................................................... 56
A/D Converter Interrupt ......................................................................................................... 56
Time Base Interrupt............................................................................................................... 57
Interrupt Wake-up Function................................................................................................... 57
Programming Considerations................................................................................................ 57
Application Circuits....................................................................................... 58
Instruction Set................................................................................................ 59
Introduction ........................................................................................................................... 59
Instruction Timing .................................................................................................................. 59
Moving and Transferring Data............................................................................................... 59
Arithmetic Operations............................................................................................................ 59
Logical and Rotate Operation ............................................................................................... 60
Branches and Control Transfer ............................................................................................. 60
Bit Operations ....................................................................................................................... 60
Table Read Operations ......................................................................................................... 60
Other Operations................................................................................................................... 60
Instruction Set Summary .............................................................................. 61
Table Conventions................................................................................................................. 61
Instruction Denition..................................................................................... 63
Package Information ..................................................................................... 72
16-pin DIP (300mil) Outline Dimensions ............................................................................... 73
16-pin NSOP (150mil) Outline Dimensions........................................................................... 75

Rev. 1.00 4 June 19, 2014 Rev. 1.00 5 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Features
CPU Features
• Operatingvoltage:fSYS=8MHz:2.3V~5.5V
• Upto0.5μsinstructioncyclewith8MHzsystemclockatVDD=5V
• Powerdownandwake-upfunctionstoreducepowerconsumption
• Twooscillators

♦InternalhighspeedRC–HIRC

♦Internal12kHzRC–LIRC
• Fullyintegratedinternal8MHzoscillatorrequiresnoexternalcomponents
• Allinstructionsexecutedinoneortwoinstructioncycles
• Tablereadinstruction
• 63powerfulinstructions
• 4-levelsubroutinenesting
• Bitmanipulationinstruction
Peripheral Features
• ProgramMemory:1K×14
• RAMDataMemory:64×8
• WatchdogTimerfunction
• Upto14bidirectionalI/Olines
• 5-channel12-bitA/DConverter
• 1-channel8-bitPWM
• ExternalinterruptpinsharedwithI/Opin
• One8-bitprogrammableTimer/EventCounterwithoverowinterruptandprescaler
• Time-Basefunction
• Lowvoltageresetfunction
• ProgrammableFrequencyDivider–PFD
• Packagetypes:16-pinNSOP/DIP

Rev. 1.00 6 June 19, 2014 Rev. 1.00 7 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
General Description
Thedeviceis8-bithighperformanceRISCarchitecturemicrocontrollerdevicespecicallydesigned
forawiderangeofapplications.Theadvantagesoflowpowerconsumption,I/Oexibility,timer
functions,oscillatoroptions,HALTandwake-upfunctions,watchdogtimer,aswellaslowcost,
enhancetheversatilityofthedevicetosuitforawiderangeoftheI/OandA/Dcontrolapplication
possibilitiessuchasindustrialcontrol,consumerproductsandsubsystemcontrollers,etc.
Block Diagram
8-bit
RISC
MCU
Core
Time
Base
A/D
Converter
I/O
Ports
Interrupt
Controller
Reset
Circuit
Internal RC
Oscillators
8-bit
Timer
Watchdog
Timer
Low Voltage
Reset
RAM
Data
Memory
PWM
Driver
PFD
Driver
OTP
Program
Memory
Pin Assignment
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
HT46R003B
16 NSOP-A/DIP-A
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
VSS
PB0
PB1
PB2
PA4/PWM
PA5/AN4
PA6/INT
PA7/RES
VDD
PB5/PFD
PB4/TMR
PB3

Rev. 1.00 6 June 19, 2014 Rev. 1.00 7 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Pin Description
Pin Name Function OPT I/T O/T Description
PA0/AN0 PA0 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN0 ADPCR AN — Analog input channel 0
PA1/AN1 PA1 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN1 ADPCR AN — Analog input channel 1
PA2/AN2 PA2 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN2 ADPCR AN — Analog input channel 2
PA3/AN3 PA3 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN3 ADPCR AN — Analog input channel 3
PA4/PWM PA4 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.
PWM CTRL0 — CMOS PWM output
PA5/AN4 PA5 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN4 ADPCR AN — Analog input channel 4
PA6/INT
PA6 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.
INT INTC0
CTRL1 ST — External interrupt input
PA7/RES PA7 PAWU
EXTRESB ST NMOS General purpose I/O. Register enabled wake-up.
RES EXTRESB ST — Reset input
PB0~PB3 PB0~PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up.
PB4/TMR PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-up.
TMR TMRC ST — Timer/Event counter input
PB5/PFD PB5 PBPU ST CMOS General purpose I/O. Register enabled pull-up.
PFD CTRL0 — CMOS PFD output
VDD VDD — PWR — Power supply
VSS VSS — PWR — Ground
Note:I/T:Inputtype;  O/T:Outputtype;
OPT:Optionalbyregisteroption;
PWR:Power;  AN:Analogsignal;
ST:SchmittTriggerinput;
CMOS:CMOSoutput;
NMOS:NMOSoutput

Rev. 1.00 8 June 19, 2014 Rev. 1.00 9 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Absolute Maximum Ratings
SupplyVoltage................................................................................................VSS-0.3VtoVSS+6.0V
InputVoltage.................................................................................................. VSS-0.3VtoVDD+0.3V
StorageTemperature.................................................................................................... -50°Cto125°C
OperatingTemperature.................................................................................................. -40°Cto85°C
Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder“Absolute
MaximumRatings”maycausesubstantialdamagetothedevice.Functionaloperationofthis
deviceatotherconditionsbeyondthoselistedinthespecicationisnotimpliedandprolonged
exposuretoextremeconditionsmayaffectdevicereliability.
D.C. Characteristics
Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating voltage — fSYS=8MHz 2.3 — 5.5 V
IDD
Operating current
(HIRC on)
3V No load, fSYS=8MHz
A/D Converter disable
—1.2 1.8 mA
5V — 2.4 3.6 mA
ISTB
Standby current
(LIRC on)
3V No load, System halt — — 5 μA
5V — — 10 μA
Standby current
(LIRC off)
3V No load, System halt — — 1 μA
5V — — 2μA
VIL
Input Low Voltage for I/O ports, TMR, INT 5V —0 — 1.5 V
— 0 — 0.2VDD V
Input low voltage for RES pin — — 0 — 0.4VDD V
VIH
Input High Voltage for I/O ports, TMR, INT 5V —3.5 — 5 V
— 0.8VDD — VDD V
Input high voltage for RES pin — — 0.9VDD — VDD V
VLVR Low Voltage Reset voltage — LVR enable,
voltage select 2.1V 2.0 2.1 2.2 V
IOH Source current for I/O ports 3V VOH=0.9VDD
-2.5 -5 — mA
5V -5 -11 — mA
IOL
Sink current for I/O ports 3V VOL=0.1VDD
7.5 15 — mA
5V 15 30 — mA
Sink current for PA7 pin 5V VOL=0.1VDD 2 3 — mA
RPH Pull-high resistance for I/O ports 3V — 20 60 100 kΩ
5V — 10 30 50 kΩ

Rev. 1.00 8 June 19, 2014 Rev. 1.00 9 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
A.C. Characteristics
Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
fSYS System clock 2.3V~5.5V — 8 MHz
fHIRC System clock (HIRC)
3V/5V Ta=25°C -2% 8 +2% MHz
3V/5V Ta=0°C~70°C -5% 8 +5% MHz
3.0V~5.5V Ta=0°C~70°C -8% 8 +8% MHz
3.0V~5.5V Ta=-40°C~85°C -12% 8 +12% MHz
fTIMER Timer I/P frequency (TMR) 3.3V~5.5V — 0 — 8 MHz
tWDTOSC Watchdog oscillator period 3V — 45 90 180 μs
5V — 32 65 130 μs
tRES External reset low pulse width — — 1 — — μs
tRESF External reset low pulse width (with lter) — — — 150 — ns
tSST System start-up timer period — Wake-up from halt — 16 — tSYS
tLVR Low Voltage Width to Reset — — 0.25 1 2 ms
tRSD System Reset Delay Time (All Reset) — — 25 50 100 ms
Note:1.tSYS=1/fSYS
2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshould
beconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.
A/D Converter Characteristics
Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
AVDD Analog operating voltage — VREF=VDD 2.7 — 5.5 V
VAD A/D Input Voltage — — 0 — AVDD /VREF V
DNL A/D Differential Non-linearity
2.7V
VREF=VDD=AVDD
tAD=0.5μs-2 — +2 LSB3V
5V
INL A/D Integral non-linearity
2.7V
VREF=VDD=AVDD
tAD=0.5μs-4 — +4 LSB3V
5V
IADC
Additional Power Consumption if
A/D Converter is used
3V No load (tAD=0.5μs) — 0.5 — mA
5V — 0.6 — mA
tAD A/D Converter Clock Period 2.7V~5.5V — 0.5 — 10 μs
tADC
A/D Conversion Time
(Include Sample and Hold Time) 2.7V~5.5V 12-bit A/D Converter — 16 — tAD
tON2ST A/D Converter On-to-Start Time 2.7V~5.5V — 2 — — μs
Note:A/Dconversiontime(tAD)=n(bitsADC)+4(samplingtime),theconversionforeachbitneedsoneADC
clock(tAD).

Rev. 1.00 10 June 19, 2014 Rev. 1.00 11 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Power-on Reset Characteristics
Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV
RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms
tPOR
Minimum Time for VDD Stays at VPOR to
Ensure Power-on Reset — — 1 — — ms
V
DD
t
POR
RR
VDD
V
POR
Time
System Architecture
Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed
totheinternalsystemarchitecture.Therangeofdevicetakeadvantageoftheusualfeaturesfound
withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.
Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction
executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe
exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyalloperations
oftheinstructionset.Itcarriesoutarithmeticoperations,logicoperations,rotation,increment,
decrement,branchdecisions,etc.Theinternaldatapathissimpliedbymovingdatathroughthe
AccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryand
canbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalong
withadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredto
provideafunctionalI/OandA/Dsystemwithmaximumreliabilityandexibility.
Clocking and Pipelining
Themainsystemclock,derivedfromHIRCoscillatorissubdividedintofourinternallygenerated
non-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1
clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthe
decodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.
Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles,the
pipeliningstructureofthemicrocontrollerensuresthatinstructionsareeffectivelyexecutedinone
instructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounter
arechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemore
instructioncycletoexecute.
Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twoinstructioncyclesare
requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone
cycletorstlyobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe
branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming
sensitiveapplications.

Rev. 1.00 10 June 19, 2014 Rev. 1.00 11 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
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
    

   



  
System Clocking and Pipelining
   
  
 





 
  
 
 



 
  
   
  
Instruction Fetching
Program Counter – PC
Duringprogramexecution,theProgramCounterisusedtokeeptrackoftheaddressofthenext
instructiontobeexecuted.Itisautomaticallyincrementedbyoneeachtimeaninstructionis
executedexceptforinstructions,suchas“JMP”or“CALL”thatdemandajumptoanon-consecutive
ProgramMemoryaddress.Itmustbenotedthatonlythelower8bits,knownastheProgram
CounterLowRegister,aredirectlyaddressablebyuser.
Whenexecutinginstructionsrequiringjumpingtonon-consecutiveaddressessuchasajump
instruction,asubroutinecall,interruptorreset,etc,themicrocontrollermanagesprogramcontrol
byloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,once
theconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresent
instructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionis
obtained.
Program Counter
High Byte of Program Low Byte of Program
PC9~PC8 PCL7~PCL0
ThelowerbyteoftheProgramCounter,knownastheProgramCounterLowregisterorPCL,is
availableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectly
intothisregister,ashortprogramjumpcanbeexecuteddirectly.However,asonlythislowbyte
isavailableformanipulation,thejumpsarelimitedinthepresentpageofmemory,whichhave
256locations.Whensuchprogramjumpsareexecuteditshouldalsobenotedthatadummycycle
willbeinserted.ThelowerbyteoftheProgramCounterisfullyaccessibleunderprogramcontrol.
ManipulatingthePCLmightcauseprogrambranching,soanextracycleisneededtopre-fetch.

Rev. 1.00 12 June 19, 2014 Rev. 1.00 13 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Stack
ThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.
Thedevicestackisorganizedinto4levelsandneitherpartofthedatanorpartoftheprogramspace,
andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andis
neitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsof
theProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,
signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvalue
fromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.
Program C ounter
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Program
Memory
Top of S ta ck
Stack
Poin te r
Bottom o f Stack
Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestagwillberecordedbut
theacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,
theinterruptwillbeserviced.Thisfeaturepreventsstackoverowallowingtheprogrammertouse
thestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstill
beexecutedwhichwillresultinastackoverow.Precautionsshouldbetakentoavoidsuchcases
whichmightcauseunpredictableprogrambranching.
Arithmetic and Logic Unit – ALU
Thearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmetic
andlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALU
receivesrelatedinstructioncodesandperformstherequiredarithmeticorlogicaloperationsafter
whichtheresultwillbeplacedinthespeciedregister.AstheseALUcalculationoroperationsmay
resultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedto
reectthesechanges.TheALUsupportsthefollowingfunctions:
• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA
• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA
• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC
• IncrementandDecrementINCA,INC,DECA,DEC
• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI.

Rev. 1.00 12 June 19, 2014 Rev. 1.00 13 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Program Memory
TheProgramMemoryisthelocationwheretheusercodeorprogramisstored.Thedeviceis
suppliedwithOne-TimeProgrammable,OTP,memorywhereuserscanprogramtheirapplication
codeintothedevice.Byusingtheappropriateprogrammingtools,OTPdeviceoffersusersthe
exibilitytofreelydeveloptheirapplicationswhichmaybeusefulduringdebugorforproducts
requiringfrequentupgradesorprogramchanges.
Structure
TheProgramMemoryhasacapacityof1K×14bits.TheProgramMemoryisaddressedbythe
ProgramCounterandalsocontainsdata,tableinformationandinterruptentriesinformation.Table
data,whichcanbesetinanylocationwithintheProgramMemory,isaddressedbyseparatetable
pointerregister.
000H Initialisation Vector
004H
3FFH 14 bits
Interrupt Vectors
010H
Look-up Table
n00H
nFFH
Program Memory Structure
Special Vectors
WithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation
000Hisreservedforusebythedeviceresetforprograminitialisation.Afteradeviceresetis
initiated,theprogramwilljumptothislocationandbeginexecution.
Look-up Table
AnylocationwithintheProgramMemorycanbedenedasalook-uptablewhereprogrammerscan
storexeddata.Tousethelook-uptable,thetablepointermustrstbesetbyplacingtheaddress
ofthelookupdatatoberetrievedinthetablepointerregister,TBLP.Thisregisterdenesthetotal
addressofthelook-uptable.
Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemory
usingthe“TABRDC[m]”or“TABRDL[m]”instructions,respectively.Whentheinstructionis
executed,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuser
denedDataMemoryregister[m]asspeciedintheinstruction.Thehigherordertabledatabyte
fromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthis
transferredhigherorderbytewillbereadas“0”.
Theaccompanyingdiagramillustratestheaddressingdataowofthelook-uptable.

Rev. 1.00 14 June 19, 2014 Rev. 1.00 15 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Register T BLHUser S electe d
Register
High B yteLow B yte
TBLP R egis te r
Data
Address
14 b its
 
Last p age o r
TBHP R egister
Table Program Example
Theaccompanyingexampleshowshowthetablepointerandtabledataisdenedandretrievedfrom
thedevice.Thisexampleusesrawtabledatalocatedinthelastpagewhichisstoredthereusingthe
ORGstatement.ThevalueatthisORGstatementis“0300H”whichreferstothestartaddressofthe
lastpagewithinthe1KProgramMemoryofthemicrocontroller.
Thetablepointerissetheretohaveaninitialvalueof“06H”.Thiswillensurethattherstdataread
fromthedatatablewillbeattheProgramMemoryaddress“0306H”or6locationsafterthestartof
thelastpage.Notethatthevalueforthetablepointerisreferencedtotherstaddressofthepresent
pageifthe“TABRDC[m]”instructionisbeingused.Thehighbyteofthetabledatawhichinthis
caseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRDL
[m]”instructionisexecuted.
BecausetheTBLHregisterisaread-onlyregisterandcannotberestored,careshouldbetaken
toensureitsprotectionifboththemainroutineandInterruptServiceRoutineusethetableread
instructions.Ifusingthetablereadinstructions,theInterruptServiceRoutinesmaychangethe
valueofTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitis
recommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However,in
situationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortothe
executionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequire
twoinstructioncyclestocompletetheiroperation.
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
mov a,06h ; initialize table pointer - note that this address
; is referenced
mov tblp, a ; to the last page or present page
:
tabrdl tempreg1 ; transfers value in table referenced by table pointer
; to tempreg1
; data at prog. memory address “0306H” transferred to tempreg1
; and TBLH
dec tblp ; reduce value of table pointer by one
tabrdl tempreg2 ; transfers value in table referenced by table pointer
; to tempreg2
; data at prog. memory address “0305H” transferred to
; tempreg2 and TBLH
; in this example the data “1AH” is transferred to tempreg1 and
; data “0FH” to register tempreg2
; the value “00H” will be transferred to the high byte
; register TBLH
:
org 0300h ; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:

Rev. 1.00 14 June 19, 2014 Rev. 1.00 15 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
RAM Data Memory
TheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwhere
temporaryinformationisstored.
Structure
Dividedintotwosections,therstoftheseisanareaofRAMwherespecialfunctionregistersare
located.Theseregistershavexedlocationsandarenecessaryforcorrectoperationofthedevice.
Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,
someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisreservedfor
generalpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogram
control.
ThetwosectionsofDataMemory,theSpecialPurposeandGeneralPurposeDataMemoryare
locatedatconsecutivelocations.AllareimplementedinRAMandare8bitswidebutthelengthof
eachmemorysectionisdictatedbythetypeofmicrocontrollerchosen.ThestartaddressoftheData
Memoryforthedeviceistheaddress“00H”.
Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbe
storedandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurpose
DataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramforbothreading
andwritingoperations.Byusingthe“SET[m].i”and“CLR[m].i”instructionsindividualbitscan
besetorresetunderprogramcontrolgivingtheuseralargerangeofexibilityforbitmanipulation
intheDataMemory.



 



 





 


 

Data Memory Structure
Note:MostoftheDataMemorybitscanbedirectlymanipulatedusingthe“SET[m].i”and“CLR
[m].i”withtheexceptionofafewdedicatedbits.TheDataMemorycanalsobeaccessed
viathememorypointerregisters.
Special Purpose Data Memory
ThisareaofDataMemoryiswhereregisters,necessaryforthecorrectoperationofthe
microcontroller,arestored.Mostoftheregistersarebothreadableandwriteablebutsomeare
protectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunction
Registersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswill
returnthevalue“00H”.

Rev. 1.00 16 June 19, 2014 Rev. 1.00 17 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
00H
01H
02H
03H
IAR0
MP0
IAR1
MP1
04H
ACC
05H
PCL
06H
TBLP
07H
TBLH
08H
WDTS
09H
STATUS
0AH
INTC0
0BH
TMR
0CH
TMRC
0DH
INTC1
0EH
0FH
PA
10H
PAC
11H
PAPU
12H
PAWU
13H
PB
14H
PBC
15H
PBPU
16H
17H
18H
19H
CTRL0
1AH
CTRL1
1BH
WDTC
1CH
1DH
ADPCR
1EH
PWM0
1FH
ADRL
20H
ADRH
21H
ADCR
22H
ACSR
23H
24H EXTRESB
25H
3FH
: unused, read as 00H
Special Purpose Data Memory

Rev. 1.00 16 June 19, 2014 Rev. 1.00 17 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Special Function Registers
Toensuresuccessfuloperationofthemicrocontroller,certaininternalregistersareimplementedin
theDataMemoryarea.Theseregistersensurecorrectoperationofinternalfunctionssuchastimer,
interrupts,etc.,aswellasexternalfunctionssuchasI/Odatacontrol.Thelocationsoftheseregisters
withintheDataMemorybeginattheaddressof“00H”.AnyunusedDataMemorylocations
betweenthesespecialfunctionregistersandthepointwheretheGeneralPurposeMemorybeginsis
reservedandattemptingtoreaddatafromtheselocationswillreturnavalueof“00H”.
Indirect Addressing Registers – IAR0, IAR1
TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAM
register,donotactuallyphysicallyexistasnormalregisters.Themethodofindirectaddressing
forRAMdatamanipulationisusingtheseIndirectAddressingRegistersandMemoryPointers,in
contrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.Actionson
theIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbut
rathertothememorylocationspeciedbytheircorrespondingMemoryPointers,MP0orMP1.As
theIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressing
Registersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultin
nooperation.
Memory Pointers – MP0, MP1
TwoMemoryPointers,knownasMP0andMP1areprovided.TheseMemoryPointersare
physicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormal
registersprovidingaconvenientwaywithwhichtoindirectlyaddressandtrackdata.Whenany
operationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddresswhichthe
microcontrollerisdirectedtoistheaddressspeciedbytherelatedMemoryPointer.Notethatfor
thisdevice,theMemoryPointers,MP0andMP1,areboth8-bitregistersandusedtoaccesstheData
MemorytogetherwiththeircorrespondingindirectaddressingregistersIAR0andIAR1.
ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydened
aslocationsadres1toadres4.
Indirect Addressing Program Example
data .section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code. section at 0 code
org 00h
start:
mov a,04h ; set size of block
mov block,a
mov a,offsetadres1   ;AccumulatorloadedwithrstRAMaddress
mov mp0,a      ;setmemorypointerwithrstRAMaddress
loop:
clr IAR0      ;clearthedataataddressdenedbyMP0
inc mp0 ; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecic
DataMemoryaddresses.

Rev. 1.00 18 June 19, 2014 Rev. 1.00 19 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Accumulator – ACC
TheAccumulatoriscentraltotheoperationofanymicrocontrollerandiscloselyrelatedwith
operationscarriedoutbytheALU.TheAccumulatoristheplacewhereallintermediateresults
fromtheALUarestored.WithouttheAccumulatoritwouldbenecessarytowritetheresultof
eachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc.,totheDataMemory
resultinginhigherprogrammingandtimingoverheads.Datatransferoperationsusuallyinvolve
thetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetween
oneuser-definedregisterandanother,itisnecessarytodothisbypassingthedatathroughthe
Accumulatorasnodirecttransferbetweentworegistersispermitted.
Program Counter Low Register – PCL
Toprovideadditionalprogramcontrolfunctions,thelowbyteoftheProgramCounterismade
accessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.By
manipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.Loading
avaluedirectlyintothisPCLregisterwillcauseajumptothespeciedProgramMemorylocation,
howeverastheregisterisonly8-bitwideonlyjumpswithinthecurrentProgramMemorypageare
permitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.
Status Register – STATUS
This8-bitregistercontainsthezeroag(Z),carryag(C),auxiliarycarryag(AC),overowag
(OV),powerdownag(PDF),andwatchdogtime-outag(TO).Thesearithmetic/logicaloperation
andsystemmanagementagsareusedtorecordthestatusandoperationofthemicrocontroller.
WiththeexceptionoftheTOandPDFags,bitsinthestatusregistercanbealteredbyinstructions
likemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFag.
Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferent
instructionoperations.TheTOagcanbeaffectedonlybyasystempower-up,aWDTtime-outor
byexecutingthe“CLRWDT”or“HALT”instruction.ThePDFagisaffectedonlybyexecuting
the“HALT”or“CLRWDT”instructionorduringasystempower-up.
TheZ,OV,ACandCagsgenerallyreectthestatusofthelatestoperations.
Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwill
notbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantand
ifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.Note
thatbits0~3oftheSTATUSregisterarebothreadableandwriteablebits.

Rev. 1.00 18 June 19, 2014 Rev. 1.00 19 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
STATUS Register
Bit76543210
Name — — TO PDF OV Z AC C
R/W — — R/W R/W R/W R/W R/W R/W
POR — — 0 0 x x x x
“x”: unknown
Bit7~6 Unimplemented,readas“0”
Bit5 TO:WatchdogTime-Outag
0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction
1:Awatchdogtime-outoccurred.
Bit4 PDF:Powerdownag
0:Afterpoweruporexecutingthe“CLRWDT”instruction
1:byexecutingthe“HALT”instruction
Bit3 OV:Overowag
0:Nooverow
1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthe
highest-orderbitorviceversa.
Bit2 Z:Zeroag
0:Theresultofanarithmeticorlogicaloperationisnotzero
1:Theresultofanarithmeticorlogicaloperationiszero
Bit1 AC:Auxiliaryag
0:Noauxiliarycarry
1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrow
fromthehighnibbleintothelownibbleinsubtraction
Bit0 C:Carryag
0:Nocarryout
1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoes
nottakeplaceduringasubtractionoperation
Cisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.00 20 June 19, 2014 Rev. 1.00 21 June 19, 2014
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
System Control Registers – CTRL0, CTRL1
TheseregistersareusedtoprovidecontrolinternalfunctionssuchasthePFDfunction,thePWM
function,externalinterruptedgetriggertypeselectionandTimeBasefunctiondivisionratio.
CTRL0 Register
Bit76543210
Name — — PWMSEL — PWMC PFDC — —
R/W — — R/W — R/W R/W — —
POR — — 0 — 0 0 — —
Bit7~6 Unimplemented,readas"0"
Bit5 PWMSEL:PWMtypeselection
0:6+2
1:7+1
Bit4 Unimplemented,readas"0"
Bit3 PWMC:I/OorPWMselection
0:PA4
1:PWM
Bit2 PFDC:I/OorPFDselection
0:PB5
1:PFD
Bit1~0 Unimplemented,readas"0"
CTRL1 Register
Bit76543210
Name INTES1 INTES0 TBSEL1 TBSEL0 — — — —
R/W R/W R/W R/W R/W — — — —
POR 1 0 0 0 — — — —
Bit7~6 INTES1~INTES0:Externalinterruptedgetypeselection
00:Disable
01:Risingedgetrigger
10:Fallingedgetrigger
11:Dualedgetrigger
Bit5~4 TBSEL1~TBSEL0:Timebaseperiodselection
00:210×(1/fS)
01:211×(1/fS)
10:212×(1/fS)
11:213×(1/fS)
Bit3~0 Unimplemented,readas"0"