Lauterbach Powerintegrator User manual

PowerIntegrator User’s Guide 1

PowerIntegrator User’s Guide

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PowerIntegrator User's Guide ................................................................................................... 1

Functional Units ...................................................................................................................... 3

PowerIntegrator 4

Support Package 5

Input/Output Lines 5

ITRIGGER OUT Connector 6

Probe Connector Assignments .............................................................................................. 7

Mictor Probe 7

Mictor Difference Probe 8

Standard Probe 8

SAMTEC Probe 9

General Functions ................................................................................................................... 10

Initialization .............................................................................................................................. 10

Signal Names 10

POD Threshold Levels and Signal Display 11

Sampling Modes 12

Sampling Mode Configurations 13

Sampling Clock Configuration 14

Analyzer Function ................................................................................................................... 15

Analyzer Control ...................................................................................................................... 16

Basic Trace Control 16

Operation Modes 18

Automatic Trace Control 18

Analyzer Display ...................................................................................................................... 19

Display Commands 19

Search and Compare 24

Tracking 25

Real-Time Displays 25

Saving Trace Buffers 26

Simple Trigger ......................................................................................................................... 27

PowerIntegrator User’s Guide 2

Function 27

Trigger Word 28

Trigger Combiner 28

Trigger PreDelay 29

Trigger Filter 29

Trigger Counter 29

Trigger Delay 29

Trigger Outputs 30

Trigger Setting 30

Using the Trigger Delay and Predelay 31

Complex Trigger ...................................................................................................................... 32

Universal Counter ................................................................................................................... 33

Function 33

Signal Selection 34

Level Display 34

Setup 35

PowerIntegrator User’s Guide 3

PowerIntegrator User’s Guide

Version 06-Nov-2019

Functional Units

The power integrator module consists of 2 parts: The timing/state analyzer and the optional support

package.

PODBUS

204

Timing Analyzer

Support

Package

(optional)

and/or

State Analyzer

PowerIntegrator User’s Guide 4

PowerIntegrator

The features of the Timing/State ANALYZER are:

Trace In timing mode the analyzer can trace

• up to 102 channels with 500 MHz sampling rate

• up to 204 channels with 25 0MHz sampling rate

In state mode the analyzer can trace

• up to 204 channels with 200 MHz sample rate

• up to 102 channels with 200 MHz sample rate, double data

rate

The trace depth is 512 K records.

For 500 MHz mode and Double Data Mode it is 1024 K records.

Transient Recording The sampling of the input lines is stored to the trace buffer by

changes of the input level only. The total recording time depends on

the occurrence of changes of the input signals. If the traced signals

only changes once per ms, the total sampling time will be 512 s. The

minimum trace time is 2 ms, which may appear if high-speed clock

signals are recorded.

Mixed Trace The input channels are split into two groups of 102 channels each.

Each group can be used for timing or state mode recording.

Timing mode: Fixed sample rate of 250/500 MHz.

State mode: For each group a 1of2 qualifier selects the sampling

clock out of the dedicated clock inputs (CLKA/B, CLKJ/K).

The sampled data are synchronized to the asynchronous trace

information.

Simple Triggering The simple trigger unit uses one trigger mask, which can include

level or edge detection, a trigger filter and a trigger counter for

generating a trigger event. Trigger programming can be done in the

data window as easy as setting trigger conditions on a scope.

Complex Triggering tbd.

PowerIntegrator User’s Guide 5

Support Package

This optional function gives the advantage of hardware based target specific add-ons like:

• Channel reordering

• Address reconstruction based on FlowTrace information

• Address demultiplexing (DRAM, SDRAM busses …)

• Protocol analysis (JTAG, Serial, CAN, USB …)

•…

This allows recording and triggering on a higher level like protocol level.

Input/Output Lines

The PowerIntegrator offers 12 connectors with 16-data + 1-data/clock channels.

For using a 16+1channel probe (standard probe) only one of this connectors is used. For using a

32+2channel probe (MICTOR/SAMTEC probe) two of this connectors are used.

D.00..D.15 12 times 16-data channels

CLKA/B,

CLKJ/K

4 times 1-data/clock channel

• timing mode: used as data channel

• state mode: used as data or clock channel

CLKC /D /E /F,

CLKL /M /N /O

8 times 1-data channel

TOUT0..TOUT3

OUTA..OUTD

Trigger Output

PowerIntegrator User’s Guide 6

ITRIGGER OUT Connector

Counting starts beside the power connector, bottom row at GND.

OUTA, OUTB, OUTC OUTD trigger outputs can be forced by the complex trigger unit

Signal Pin Pin Signal

TOUT0 1 2 GND

TOUT1 3 4 GND

TOUT2 5 6 GND

TOUT3 7 8 GND

OUTA 9 10 GND

OUTB 11 12 GND

OUTC 13 14 GND

OUTD 15 16 GND

Trigger Point

Stopped

TOUT3

ARM On

TOUT0

ARM Off

Trigger Point

TOUT1

TOUT2

Stopped

PowerIntegrator User’s Guide 7

Probe Connector Assignments

Mictor Probe

Mictor Difference Probe

Signal Pin Pin Signal

N/C 1 2 N/C

GND 3 4 N/C

CLK0 5 6 CLK1

D15 7 8 D31

D14 9 10 D30

D13 11 12 D29

D12 13 14 D28

D11 15 16 D27

D10 17 18 D26

D9 19 20 D25

D8 21 22 D24

D7 23 24 D23

D6 25 26 D22

D5 27 28 D21

D4 29 30 D20

D3 31 32 D19

D2 33 34 D18

D1 35 36 D17

D0 37 38 D16

Signal Pin Pin Signal

N/C 1 2 N/C

GND 3 4 N/C

CLK+ 5 6 CLK-

D15+ 7 8 D15-

D14+ 9 10 D14-

D13+ 11 12 D13-

D12+ 13 14 D12-

D11+ 15 16 D11-

D10+ 17 18 D10-

D9+ 19 20 D9-

D8+ 21 22 D8-

D7+ 23 24 D7-

D6+ 25 26 D6-

D5+ 27 28 D5-

D4+ 29 30 D4-

D3+ 31 32 D3-

D2+ 33 34 D2-

D1+ 35 36 D1-

D0+ 37 38 D0-

PowerIntegrator User’s Guide 8

Standard Probe

Signal Pin Pin Signal

N/C 1 2 N/C

CLK 3 4 D15

D14 5 6 D13

D12 7 8 D11

D10 9 10 D9

D8 11 12 D7

D6 13 14 D5

D4 15 16 D3

D2 17 18 D1

D0 19 20 GND

PowerIntegrator User’s Guide 9

SAMTEC Probe

Signal Pin Pin Signal

GND 1 2 GND

N/C 3 4 N/C

GND 5 6 GND

D16 7 8 D0

GND 9 10 GND

D17 11 12 D1

GND 13 14 GND

D18 15 16 D2

GND 17 18 GND

D19 19 20 D3

GND 21 22 GND

D20 23 24 D4

GND 25 26 GND

D21 27 28 D5

GND 29 30 GND

D22 31 32 D6

GND 33 34 GND

D23 35 36 D7

GND 37 38 GND

D24 39 40 D8

GND 41 42 GND

D25 43 44 D9

GND 45 46 GND

D26 47 48 D10

GND 49 50 GND

D27 51 52 D11

GND 53 54 GND

D28 55 56 D12

GND 57 58 GND

D29 59 60 D13

GND 61 62 GND

D30 63 64 D14

GND 65 66 GND

D31 67 68 D15

GND 69 70 GND

N/C 71 72 N/C

GND 73 74 GND

N/C 75 76 N/C

GND 77 78 GND

CLK1 79 80 CLK0

GND 81 82 GND

N/C 83 84 N/C

GND 85 86 GND

N/C 87 88 N/C

GND 89 90 GND

N/C 91 92 N/C

GND 93 94 GND

GND 95 96 GND

N/C 97 98 N/C

N/C 99 100 N/C

PowerIntegrator User’s Guide 1 0

General Functions

Initialization

Signal Names

The NAME function generates logical names for input lines and additionally the polarity of the signal. In the

trigger program of the integrator, logical definitions can be used instead of physical pin names.

The NAME function also configures the transient detection type. It can be set to NoTransient, Transient,

FallingTransient or RisingTransient.

RESet Initialize integrator

STOre Save setup

NAME.list Display logical names

NAME.RESet Erase logical names for input pins

NAME.Set Define logical names for input pins

NAME.Group Define logical names for input groups

NAME.Word Define logical names for busses

NAME.Delete Erase logical groups or words for input pins

PowerIntegrator User’s Guide 1 1

POD Threshold Levels and Signal Display

The POD function defines the threshold level for the input lines. Each probe (16 data+1 Clock) can be

configured for different threshold levels in a range of 0 to 5 V.

The POD window also displays the selected threshold levels, the current probe signal levels and the clock

frequency of the selected target state clock (StatePLL modes only).

POD.state Display threshold level

POD.Level Select threshold level

POD.RESet Set to default

PowerIntegrator User’s Guide 1 2

Sampling Modes

The PowerIntegrator supports four kinds of sampling modes:

1. Timing Mode

Probe signals are sampled with a fixed frequency of 250 MHz (204 channels) or 500 MHz (102

channels).

2. State ModePLL

Probe signals are sampled on the rising or falling edge of a target clock signal (CLKA, CLKB, CLKJ,

CLKK). The selected target clock feeds an PowerIntegrator internal PLL which gives the option to

vary the sampling time in a range of -3 … +6 ns in steps of 250 ps. To make the PLL circuit work the

target clock has to be active always and it has to run on a fixed frequency in the range of

6…200MHz.

3. State Mode Double Data Rate

like State ModePLL, but data is sampled on the rising and falling clock edge. Channel count is

reduced to 102.

4. State Mode

A kind of State Mode for pulsed clock signals. Probe signals are sampled on the rising or falling

edge of a target clock signal (CLKA, CLKB, CLKJ, CLKK). The selected clock is sampled with

500 MHz (2 ns resolution) to detect the clock edges. Probe signals are sampled with 250 MHz if a

clock edge was detected. This method works in the range of 0 … 133 MHz.

PowerIntegrator User’s Guide 1 3

Sampling Mode Configurations

The 204 input channels are split into two groups of 102 channels each. To give the maximum flexibility this

groups can be combined and configured in different modes.

Group ABCDEF Group

JKLMNO

Mode Probes Channels Number

500MHz Timing Mode 500 MHz ABCDEF 102

Fixed500MHz Fixed sampling with

500 MHz

ABCDEF 102 with 500 Mhz

250MHz 250MHz Timing Mode 250 MHz all 204

250MHz State Timing Mode 250 MHz

State Mode

ABCDEF

JKLMNO

102

State 250MHz State Mode

Timing Mode 250 MHz

ABCDEF

JKLMNO

102

State State State Mode

State Mode

ABCDEF

JKLMNO

102

StatePLL 250MHz State Mode PLL

Timing Mode 250 MHz

ABCDEF

JKLMNO

102

102 **

StatePLL State State Mode PLL

State Mode

ABCDEF

JKLMNO

102

102 **

StatePLL StatePLL State Mode PLL

State Mode PLL

ABCDEF

JKLMNO

102

StatePLL, DDR State Mode PLL ABCDEF 102, DDR

StatePLLBoth State Mode PLL all 204

PowerIntegrator User’s Guide 1 4

Sampling Clock Configuration

For State-Mode and State-PLL-Mode various clock settings are supported.

1. Clock Selection: For each group (ABCDEF, JKLMNO) a 1 of 2 qualifier selects the sampling clock

out of the dedicated clock inputs (CLKA/B, CLKJ/K).

2. Edge Selection: For each clock (CLKA/B, CLKJ/K) the rising or falling edge can be selected.

Additional both edges can be selected for clock CLKA/B to support Double Data Rate sampling

on the rising and falling clock edge.

3. State Mode PLL setting: For each clock (CLKA/B, CLKJ/K) the sampling clock delay can be

defined in a range of -3 … +6 ns in steps of 250 ps.

Integrator.ABCDEF 500MHZ Timing Mode 500 MHz, group ABCDEF only

Integrator.ABCDEF Fixed500MHZ Timing Mode, fixed sampling with 50 0MHz, group

ABCDEF only

Integrator.ABCDEF 250MHZ Timing Mode 250 MHz

Integrator.ABCDEF State State Mode

Integrator.ABCDEF StatePLL State Mode PLL

Integrator.ABCDEF StatePLLBoth State Mode PLL, group ABCDEF and JKLMNO sampled

with CLKA or CLKB

Integrator.JKLMNO 250MHZ Timing Mode 250MHz

Integrator.JKLMNO State State Mode

Integrator.JKLMNO StatePLL State Mode PLL

Integrator.ABCDEF CLKA clock A select

Integrator.ABCDEF CLKB clock B select

Integrator.ABCDEF Falling sample on falling clock edge

Integrator.ABCDEF Rising sample on rising clock edge

Integrator.ABCDEF DDR sample on rising and falling clock edge

Integrator.ABCDEF SAMPLE sampling delay of selected clock

Integrator.JKLMNO CLKJ clock J select

Integrator.JKLMNO CLKK clock K select

Integrator.JKLMNO Falling sample on falling clock edge

Integrator.JKLMNO Rising sample on rising clock edge

Integrator.JKLMNO SAMPLE sampling delay of selected clock (-3 … +6 ns in steps of

250 ps)

PowerIntegrator User’s Guide 1 5

Analyzer Function

Input Control

Support Package Target specific adaption (FlowTrace address reconstruction, SDRAM

address demultiplexing …)

Trace Memory The trace memory stores all data from the input line.

Timestamp As the trace memory samples only differences to the previous state,

a timestamp memory is needed to sample the time information.

Transient Detection The circuit detects all state changes of input lines.

Trace Control The trace control unit generates the control signals for the trace and

the timestamp memory, depending on the output of transient

detection circuit and complex trigger.

Simple Trigger The simple trigger system has one trigger pattern detection for 204

signals, a trigger filter and a trigger counter.

Complex Trigger Sequencer controlled trigger system, used for complex trigger

conditions and selective tracing.

204

Timing Analyzer Schematics

Input

Probes

Simple Trigger

Complex Trigger

Trans. Detector

Trace

Memory

Time

Stamp

Trace

Control

Trigger

Support

Package

(option)

PowerIntegrator User’s Guide 1 6

Analyzer Control

Basic Trace Control

The trace buffer can either sample information or display the results. In the Arm state the input lines are

sampled. The trace can be displayed in the Off or Break state.

Integrator.state Show the integrator state window

Integrator.OFF Turn off the integrator

Integrator.Arm Arm the integrator

Integrator.TRIGGER Trigger the integrator

Integrator.Init Clear the trace buffer and restart the trigger unit and the

counters.

Integrator.TEST Combination of Init and Arm

Integrator.RESet Restore all setting to the default values

Condition: OFF

Integrator.OFF

Analyzer disabled or break after

AutoArm

Integrator.Arm or AutoArm and program start

Condition: ARMED

Analyzer and Trigger enabled

Trigger Unit

Trigger reached

STACK

mode Condition: TRIGGERED

trace Integrator.Arm

and Analyzer and Trigger enabled or AutoArm and

trace program start

full

STACK mode trace or Trigger Delay

and trace full expired

Condition: BREAKED

Analyzer and Trigger disabled

Analyzer Operation States

PowerIntegrator User’s Guide 1 7

All basic functions of the integrator can be controlled by the integrator state window.

The window displays information about the actual state, the mode and the number of records in the trace

buffer. It also shows information about the trigger unit, like logical trigger level, counters and flags.

triggered The integrator is waiting for the expiration of the trigger delay.

break The trigger unit has stopped the recording

records Displays the used records in the trace buffer

PowerIntegrator User’s Guide 1 8

Operation Modes

The behavior characteristics of the integrator can be changed by the Integrator.Mode command. The basic

operation mode for the trace storage can be FIFO or STACK.

Automatic Trace Control

To simplify the controlling of the integrator, different automatic control options are available. As a default the

AutoArm option is active. This means that the integrator will be armed automatically when the user program

is started, and switches to off, after stopping the real-time emulation.

The combination of AutoTEST and Stack operation mode can be used for making random samples and

displaying the results continuously:

The result will be a continuously updated trace list window, which shows the last sampled signals.

Integrator.Mode Fifo FIFO operation mode, integrator records the last cycles

before stop recording

Integrator.Mode Stack STACK operation mode, the integrator stops recording,

when the trace buffer is full

Integrator.AutoArm Arm the integrator before starting the user program (ICE

or ICD), switch off after stopping

Integrator.AutoInit Init the integrator before starting the user program (ICE

or ICD)

Integrator.AutoTEST Automatically arm the integrator after all windows have

been updated

B:Integrator.Mode AutoTest ON

B:Integrator.Mode Stack

B:Integrator.List

B:Go

PowerIntegrator User’s Guide 1 9

Analyzer Display

Display Commands

The trace buffer can be displayed in tabular form or in graphical form.

The integrator GET command displays the actual input state and activity.

high Signal stays high

low Signal stay low

hilo Signal is toggling

Integrator.List Displays trace in table format

Integrator.Timing Displays channels as waveform graphics

Integrator.Get Displays the input signal level and activity

Integrator.View Displays one line

Integrator.Chart Displays values graphically

Integrator.PROTOcol.’*’ Displays protocols like CAN, I2C, etc.

Integrator.STATistic Displays trace statistics

COVerage Displays code coverage

PowerIntegrator User’s Guide 2 0

B::Integrator.get

record i.a0 i.a1 i.a2 i.a3 i.a4 i.a5 i.a6 i.a7 i.a8 i.a9 i.a10 i.a11 i.a12

direct LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW

i.a13 i.a14 i.a15 i.b0 i.b1 i.b2 i.b3 i.b4 i.b5 i.b6 i.b7 i.b8 i.b9 i.b10