LG 22LD350 User manual

LCD TV
SERVICE MANUAL
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
CHASSIS : LC01A
MODEL : 22LD350 22LD350-CB
North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
Internal Use Only
Printed in ChinaP/NO :MFL62863023 (1008-REV00)

- 2 - LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
CONTENTS
CONTENTS .............................................................................................. 2
SAFETY PRODUCT ................................................................................. 3
SPECIFICATION ....................................................................................... 4
ADJUSTMENT INSTRUCTION ................................................................ 7
EXPLODED VIEW ................................................................................... 12
SVC. SHEET ...............................................................................................

- 3 - LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SAFETY PRECAUTIONS
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
1.5 Kohm/10W
To Instrument's
exposed
METALLIC PARTS
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
AC Volt-meter
When 25A is impressed between Earth and 2nd Ground
for 1 second, Resistance must be less than 0.1
*Base on Adjustment standard
IMPORTANT SAFETY NOTICE
0.15 uF
Ω

1. Application range
This specification is applied to the LCD TV used LC01A chassis.
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC
2) Relative Humidity : 65 % ± 10 %
3) Power Voltage: Standard input voltage (AC 100-240 V~ 50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : CE, IEC specification
- EMC :CE, IEC
4. Module General Specification
- 4 - LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement .
SpecificationItemNO. Remark
1 Display Screen Device 42” wide Color Display Module Edgel LCD
16:9
3 LCD Module 22”TFT LCD FHD AUO/LGD: 42LE4500-CA
Humidity : 10 ~ 90 %
5 Input Voltage AC 100-240 V~, 50 / 60Hz
6
2 Aspect Ratio
4 Storage Environment Temp. : -20 deg ~ 60 deg
22LGD(FHD)
501(H)×297(V)×17.3(D)
Module Size

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 5 -
Specification
Resolution
No.
No. Item Specification Min. Typ. Max. Remark
1. Viewing Angle<CR>10> Right/Left/Up/Down 89 Degree
Luminance (cd/m2) 150
2. Luminance
- 1.3
3. Contrast Ratio CR 200
White Wx 0.279
Wy Typ 0.292 Typ
RED Rx - 0.030.615 +0.03
4. CIE Color Coordinates Ry 0.343
Green Gx 0.319
Gy 0.631
Blue Bx 155
By 0.046
5. LCD Module
Variation
MAX/MIN
1) Standard Test Condition(The unit has been‘ON’)
2) Stable forapproximately 30minutesinadark environment at 25±2
℃
3) The valuesspecifiedare at approximate distance 50Cm from the LCD surface
4) T
a
= 25±2°
C, V
LCD
=12.0V, f
V
=60Hz, D
clk
= 74 . 25MHz VBR_A=1.65V, EXT V
BR_B
=100%
Specification
Resolution
Remark
H-freq (kHz) V-freq (Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080p
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 HDTV 1080p
67.5 60
6. Component Video Input (Y, CB/PB, CR/PR)6. Component Video Input (Y, CB/PB, CR/PR)

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 6 -
7. RGB Input(PC)
No. Specification Proposed Remarks
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08
2. 640*480 31.469 59.94
28.321
25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
For only DOS mode
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1280*768 47.78 59.87 79.5 WXGA
6. 1360*768 47.72 59.8 84.75 WXGA
7. 1280*1024 63.595 60.0 108.875
8. 1920*1080 66.587 59.93 138.625 WUXGA FHD model
720DTV standard
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*400 31.468 70.08 28.321 HDCP
2. 640*480 31.469 59.94 25.17 VESA HDCP
3. 800*600 37.879 60.31 40.00 VESA HDCP
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1280*768 47.78 59.87 79.5 WXGA HDCP
6. 1360*768 47.72 59.8 84.75 WXGA HDCP
7. 1280*1024 63.595 60.0 108.875 SXGA HDCP FHD model
8. 1920*1080 67.5 60 148.5 WUXGA HDCP FHD model
HDCP
（2）PC Mode
8. HDMI Input (PC/DTV)
（1）DTV Mode
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469 /31.5 59.94 / 60 27.00/27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96 / 45 59.94 / 60 74.17/ 74.25 HDTV 720P
5. 1920*1080 33.72 / 33.75 59.94 / 60 74.17/ 74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97 / 27 23.97 / 24 74.17/ 74.25 HDTV 1080P
8. 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 HDTV 1080P

LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 7 -
ADJUSTMENT INSTRUCTION
1. Application Range
This specification sheet is applied to all of the LCD TV with
LC01A chassis.
2. Designation
1) The adjustment is according to the order which is
designated and which must be followed, according to the
plan which can be changed only on agreeing.
2) Power Adjustment: Free Voltage
3) Magnetic Field Condition: Nil.
4) Input signal Unit: Product Specification Standard
5) Reserve after operation: Above 5 Minutes (Heat Run)
Temperature : at 25 ºC ± 5 ºC
Relative humidity : 65 % ± 10 %
Input voltage : 220 V, 60 Hz
6) Adjustment equipments: Color Analyzer (CA-210 or CA-
110), Pattern Generator(MSPG-925L or Equivalent), DDC
Adjustment Jig equipment, Service remote control.
7) Push the “IN STOP” key - For memory initialization.
3. Main PCB check process
* APC - After Manual-Insert, executing APC
* Boot file Download
(1) Execute ISP program “Mstar ISP Utility” and then click
“Config” tab.
(2) Set as below, and then click “Auto Detect” and check “OK”
message.
If “Error” is displayed, Check connection between
computer, jig, and set.
(3) Click “Read” tab, and then load download file (XXXX.bin)
by clicking “Read”.
(4) Click “Connect” tab. If “Can’t” is displayed, check
connection between computer, jig, and set.
(5) Click “Auto” tab and set as below
(6) Click “Run”.
(7) After downloading, check “OK” message.
* USB DOWNLOAD(*.epk file download)
(1) Put the USB Stick to the USB socket.
(2) Automatically detecting update file in USB Stick.
- If version of update file in USB Stick is Lower, it didn’t
work. But version of update file is Higher, USB data is
automatically detecting
f i l e xxx.b i n
(7 ) .........OK
(6)
(5)
(1)
Please Check the Speed : To use speed between
from 200KHz to 400KHz
(2)
filexxx.bin
(3) (4)
Case1 : Software version up
1. After downloading S/W by USB, TV set will reboot
automatically
2. Push “In-stop” key
3. Push “Power on” key
4. Function inspection
5. After function inspection, Push “I n-stop” key.
Case2 : Function check at the assembly line
1. When TV set is entering on the assembly line, Push
“In-stop” key at first.
2. Push “Power on” key for turning it on.
-> If you push “Power on” key, TV set will recover
channel information by itself.
3. After function inspection, Push “In-stop” key.

(3) Show the message “Copying files from memory”
(4) Updating is staring.
(5) After updating is complete, the TV will restart automatically.
(6) If TV turns on, check your updated version and Tool
option. (refer to the next page about tool option)
* If downloading version is higher than your TV have, TV
can lost all channel data. In this case, you have to
channel recover. If all channel data is cleared, you didn’t
have a DTV/ATV test on production line.
* After downloading, have to adjust Tool Option again.
(1) Enter ‘EZ ADJUST’ mode by pushing ‘ADJ’ key.
(2) Select each ‘Tool Option(1~5)’ and push ‘OK’ or ‘G’ key.
(3) Correct the number. (Each model has their number.)
(4) Correction Tool option is complete.
3.1. ADC Process
* You need not connecting RGB(D-sub) cable. Because ADC
uses TV internal pattern.
• Enter ‘EZ ADJUST’ mode by pushing ‘ADJ’ key,
•Enter ‘ADC Calibration’ mode by pushing ‘OK’ or “ ” key
after selecting “6. ADC Calibration”.
<Caution> Turn on Tv by pushing ‘POWER ON’ or ‘P-ONLY’ key.
* ADC Calibration Protocol (RS232)
Adjust Sequence
• aa 00 00 [Enter Adjust Mode]
• xb 00 40 [Component1 Input (480i)]
• ad 00 10 [Adjust 480i Comp1]
• xb 00 60 [RGB Input (1024*768)]
• ad 00 10 [Adjust 1024*768 RGB]
• aa 00 90 End Adjust mode
* Required equipment : factory Service Remote control
3.2. Function Check
(1) Check display and sound
- Check Input and Signal items.
Model Tool option1 Tool option2 Tool option3 Tool option4 Tool option 5
22LD350 8192 8714 3076 14604 32
1) TV
2) AV
3) COMPONENT1/2 (480i)
4) RGB (PC : 1024 x 768 @ 60hz)
5) HDMI 1/2/3
6) PC Audio In
* Display and Sound check is executed by remote control.
- 8 - LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
Item CMD1 CMD2 Data0
Adjust A A 0 0 When transfer the ‘Mode In’,
‘Mode In’ Carry the command.
ADC Adjust A D 1 0 Automatically adjustment
(The use of a internal pattern)
ADC Calibration
ADC Comp 480i NG
ADC Comp 1080p NG
ADC RGB NG
Start Reset
EZ ADJUST
0. Tool Option1
1. Tool Option2
2. Tool Option3
3. Tool Option4
4. Tool Option5
5. Country Group
6. ADC Calibration
7. White Balance
8. 10 Point WB
9. Test Pattern
10. EDID D/L
11. Sub B/C
12. V-Com
13. P-Gamma

- 9- LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
4.3. White Balance Adjustment
4.3.1 Overview
(1) W/B adj. Objective & How-it-works
(2) Objective: To reduce each Panel’s W/B deviation
(3) How-it-works : When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.
(4) Adj. condition : normal temperature
1) Surrounding Temperature : 25 ºC ± 5 ºC
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
4.3.2 Equipment
1) Color Analyzer: CA-210 (LED Module : CH 14)
2) Adj. Computer(During auto adj., RS-232C protocol is
needed)
3) Adjust Remocon
4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model:217, Pattern:78)
-> Only when internal pattern is not available
AColor Analyzer Matrix should be calibrated using CS-1000
4.3.3. Equipment connection MAP
Color Analyzer
Computer
Pattern Generator
RS-232C
RS-232C
RS-232C
Probe
Signal Source
* If TV internal pattern is used, not needed
4.3.4. Adj. Command (Protocol)
<Command Format>
- LEN: Number of Data Byte to be sent
- CMD: Command
- VAL: FOS Data value
- CS: Checksum of sent data
- A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
ARS-232C Command used during auto-adj.
Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f -> Gain adj. completed
*(wb 00 20(start), wb 00 2f(endc) -> Off-set adj.
wb 00 ff -> End white balance auto-adj.
Adj. Map
LEN CMD VAL CS
RS-232C COMMAND Explanation
[CMD ID DATA]
wb 00 00 Begin White Balance adj.
wb 00 10 Gain adj.(internal white pattern)
wb 00 1f Gain adj. completed
wb 00 20 Offset adj.(internal white pattern)
wb 00 2f Offset adj. completed
wb 00 ff End White Balance adj.(Internal pattern disappears)
ITEM Command Data Range Default
(lower case ASCII) (Hex.) (Decimal)
Cmd 1 Cmd 2 Min Max
Cool R-Gain j g 00 C0
G-Gain j h 00 C0
B-Gain j i 00 C0
R-Cut
G-Cut
B-Cut
Medium R-Gain j a 00 C0
G-Gain j b 00 C0
B-Gain j c 00 C0
R-Cut
G-Cut
B-Cut
Warm R-Gain j d 00 C0
G-Gain j e 00 C0
B-Gain j f 00 C0
R-Cut
G-Cut
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Details

Copyright © 2010 LG Electronics. Inc. All rights reserved. - 10- LGE Internal Use Only
Only for training and service purposes
4.3.5. Adj. method
(1) Auto adj. method
1) Set TV in adj. mode using POWER ON key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable (RS-232C)
4) Select mode in adj. Program and begin adjustment.
5) When adj. is complete (OK Sing), check adj. status pre
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj.
W/B Adj. must begin as start command “wb 00 00” , and
finish as end command “wb 00 00”, and Adj. offset if need.
(2) Manual adj. method
1) Set TV in Adj. mode using POWER ON
2) Zero Calibrate the probe of Color Analyzer, then place it
on the center of LCD module within 10cm of the surface.
3) Press ADJ key -> EZ adjust using adj. R/C -> 7. White-
Balance then press the cursor to the right (KEY G).
(When KEY(G) is pressed 216 Gray internal pattern will
be displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.
5) Adj. is performed in COOL, MEDIUM, WARM 3 modes
of color temperature.
AIf internal pattern is not available, use RF input. In EZ
Adj. menu 7.White Balance, you can select one of 2
Test-pattern: ON, OFF. Default is inner(ON). By
selecting OFF, you can adjust using RF signal in 216
Gray pattern.
AAdj. condition and cautionary items
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer (CA-210) probe should be within 10
cm and perpendicular of the module surface (80° ~
100°)
3) Aging time
- After Aging Start, Keep the Power ON status during
5 Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
4.3.6. Reference ( White Balan ce A dj. c oor din at e
and temperature)
ALuminance : 216 Gray
AStandard color coordinate and temperature using CS-1000
(over 66cm(26 inch))
A10 Point White Balance
AColor Coordinate Variation by Aging time
Standard color coordinate and temperate us ingCA-210
（CH9)
Mode Color Coordination Temp UV
x y
COOL 0.269 ± 0.002 0.273 ± 0.002 13000 K 0.0000
MEDIUM 0.285 ± 0.002 0.293 ± 0.002 9300 K 0.0000
WARM 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
Mode Color Coordination Temp ∆UV
x y
COOL 0.269 0.273 13000 K 0.0000
MEDIUM 0.285 0.293 9300 K 0.0000
WARM 0.313 0.329 6500 K 0.0000
On / Off On / Off
Pattern Outer(default)
IRE 100
Luminance 130
Red(130.0 nit) 0
Green(130.0 nit) 0
Blue(130.0 nit) 0
Medium Warm
1 0-2 280 285 296 305 319 340
23-5 278 282 294 302 317 338
36-9 276 285 305 335
410-19 274 282 302 332
520-35 273 279 299 329
636-49 270 276 296 326
750-79 269 273 293 323
8Over 80 269 273 293 323
GP2
291 311
308
292
290
289
287
286
285
312
310
308
308
Aing time
(Min)
Cool
x y x y x y
269 273 285 293 313 329
288
315
313

4.4. DDC EDID Write (RGB 128Byte )
· Connect D-sub Signal Cable to D-Sub Jack.
· Write EDID DATA to EEPROM (24C02) by using DDC2B
protocol.
· Check whether written EDID data is correct or not.
* For SVC main Ass’y, EDID have to be downloaded to Insert
Process in advance.
4.5DDC EDID Write (HDMI 256Byte)
· Connect HDMI Signal Cable to HDMI Jack.
· Write EDID DATA to EEPROM(24C02) by using DDC2B
protocol.
· Check whether written EDID data is correct or not.
* For SVC main Ass’y, EDID have to be downloaded to Insert
Process in advance.
4.6 EDID DATA
1) All Data : HEXA Value
2) Changeable Data :
*: Serial No : Controlled / Data:01
**: Month : Controlled / Data:00
***:Year : Controlled
****:Check sum
- Auto Download
- Manual Download
* Caution
1) Use the proper signal cable for EDID Download
- Analog EDID : Pin3 exists
- Digital EDID : Pin3 exists
2) Nerver connect HDMI & D-sub Cable at the same time.
3) Use the proper cables below for EDID Writing.
4) Download HDMI1, HDMI2，separately because each data is
different.
HDMI3
D-sub to D-sub DVI-D to HDMI or HDMI to HDMI
For HDMI EDIDFor Analog EDID
4.7. Outgoing condition Configuration
4.8. Internal pressure
Confirm whether is normal or not when between power
board’s ac block and GND is impacted on 1.5 kV(dc) or 2.2
kV(dc) for one second.
Push ＇IN STOP＇key ,then in-stop processing will start.
If processing is complete, TV will turn off automatically.
Must not AC powerOFF during processing.
- 11-
LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
EZ ADJUT
0. Tool Option1
1. Tool Option2
2. Tool Option3
3. Tool Option4
4. Country Group
5. ADC Calibration
6. White Balance
7. Test Pattern
8. EDID D/L
9. Sub B/C
0. Tool Option1
1. Tool Option2
2. Tool Option3
3. Tool Option4
4. Tool Option5
5. Country Group
6. ADC Calibration
7. White Balance
8. 10 Point WB
9. Test Pattern
10. EDID D/L
11. Sub B/C
12. V-Com
13. P-Gamma
EDID D/L
HDMI1
HDMI2
HDMI3
RGB
NG
NG
NG
NG
Reset
Start
EDID D/L
HDMI1
HDMI2
HDMI3
RGB
OK
OK
OK
OK
Reset
Start
* EDID data and Model option download (RS232)
Item CMD1 CMD2 Data0
A A 0 0 When transfer the ‘Mode In’,
‘Mode In’ Carry the command.
Download
A E 00 10 Automatically Download
(The use of a internal pattern)
Enter
Download
EDID data and
Model option

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 12 -
EXPLODED VIEW
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
IMPORTANT SAFETY NOTICE
300
200
803
521 802
511
510 400
801
530 540
401
120
122
500
A2
A21
LV1 402
910
900

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
PCM_A[8]
CI_TS_DATA[6]
PCM_A[3]
PCM_A[10]
FE_TS_DATA[5]
PCM_A[0]
PCM_D[6]
CI_TS_DATA[0]
PCM_D[2]
PCM_A[7]
PCM_A[9]
FE_TS_DATA[3]
PCM_A[12]
PCM_A[4]
PCM_D[5]
CI_TS_DATA[3]
PCM_A[5]
FE_TS_DATA[0]
CI_TS_DATA[5]
PCM_A[2]
PCM_A[13]
FE_TS_DATA[4]
PCM_A[1]
PCM_A[3]
PCM_A[2]
CI_TS_DATA[4]
PCM_D[1]
PCM_A[11]
FE_TS_DATA[2]
PCM_D[4]
PCM_A[7]
PCM_A[6]
PCM_A[0]
CI_TS_DATA[7]
PCM_A[4]
PCM_D[0]
FE_TS_DATA[6]
CI_TS_DATA[1]
CI_TS_DATA[2]
PCM_A[6]
PCM_A[14]
PCM_D[3]
PCM_D[7]
FE_TS_DATA[1]
FE_TS_DATA[7]
PCM_A[5]
PCM_A[1]
MODEL_OPT_2
/PCM_WE
R104
10K
OPT
HP_DET
S7_RXD
I2C_SDA
SPI_SDI
FRC_RESET
+3.3V_Normal
I2C_SDA
/PF_OE
PCM_A[0-7]
+3.5V_ST
C104
8pF
OPT
C108
0.1uF
OPT
IC103
CAT24WC08W-T
3
A2
2
A1
4
VSS
1
A0
5SDA
6SCL
7WP
8VCC
TUNER_RESET
FRC_PWM1
CI_TS_DATA[0-7]
R158 100
OPT
M_REMOTE_RX
R105
1K
OPT
UART_FRC_TX
R1081K
OPT
DEMOD_RESET
PCM_D[0-7]
R126
1K
PF_ALE
PF_ALE
SPI_SCK
IC102
HY27UF082G2B-TPCB
2GBIT
26 NC_17
27 NC_18
28 NC_19
29 I/O0
30 I/O1
31 I/O2
32 I/O3
33 NC_20
34 NC_21
35 NC_22
36 VSS_2
37 VCC_2
38 NC_23
39 NC_24
40 NC_25
41 I/O4
42 I/O5
43 I/O6
44 I/O7
45 NC_26
46 NC_27
47 NC_28
48 NC_29
17
ALE
3
NC_3
6
NC_6
16
CLE
15
NC_10
14
NC_9
13
VSS_1
12
VCC_1
11
NC_8
10
NC_7
9
CE
8
RE
7
R/B
4
NC_4
5
NC_5
25 NC_16 24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
WE
/PCM_WAIT
R125
1K
OPT
DSUB_DET
R113
4.7K
M_REMOTE_TX
USB1_OCD
/PF_WE
FE_TS_VAL_ERR
R115
1K
ERROR_OUT
R134 22
R159 100
OPT
CI_TS_SYNC
SC1/COMP1_DET
A_DIM
/PCM_REG
FE_TS_SYNC
PCM_5V_CTL
S7_TXD
5V_DET_HDMI_4
R128 22
+3.3V_Normal
/PCM_IRQA
+5V_Normal
/PF_OE
C111
2.2uF
FRC_SCL
R118
1K OPT
SC_RE1
/PCM_IOWR
R103
0
SCAN_BLK1/OPC_OUT
/PF_CE1
SPI_SDO
C107
0.1uF
R14922
OPT
/PCM_IORD
5V_DET_HDMI_3
PWM2
C105
0.1uF
C103
0.1uF
/PF_WE
R135 22
I2C_SDA
5V_DET_HDMI_2
ET_RXER
R124
1K
MODEL_OPT_3
R120
1K
OPT
C106
8pF
OPT
FRC_PWM0
R123
1K
OPT
R14633
/PF_CE1
/PF_CE0
R101 3.3K
OPT
AV_CVBS_DET
RGB_DDC_SDA
PWM0
MODEL_OPT_1
I2C_SCL
R14822 OPT
CI_TS_VAL
PCM_A[0-14]
R133
10K
I2C_SCL
/F_RB
/RST_PHY
R155
0
OPT
PWM_DIM
/PCM_OE
UART_FRC_RX
Q101
KRC103S
OPT
E
B
C
R106 1K
R138 22
FE_TS_DATA[0-7]
PCM_RST
AR104
22
R117
1K
/PF_WP
I2C_SCL
AR102
22
SCAN_BLK2
SC_RE2
R116
1K OPT
+3.3V_Normal
R107 1K
R157 100
R132
10K
R137 22
CI_TS_CLK
AR103
22
SIDEAV_DET
/PF_CE0
IC102-*1
HY27US08121B-TPCB
512MBIT
26 NC_17
27 NC_18
28 NC_19
29 I/O0
30 I/O1
31 I/O2
32 I/O3
33 NC_20
34 NC_21
35 NC_22
36 VSS_2
37 VCC_2
38 PRE
39 NC_23
40 NC_24
41 I/O4
42 I/O5
43 I/O6
44 I/O7
45 NC_25
46 NC_26
47 NC_27
48 NC_28
17
ALE
3
NC_3
6
NC_6
16
CLE
15
NC_10
14
NC_9
13
VSS_1
12
VCC_1
11
NC_8
10
NC_7
9
CE
8
RE
7
R/B
4
NC_4
5
NC_5
25 NC_16 24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
WE
/PCM_CD
/F_RB
C101
0.1uF
R139 22
5V_DET_HDMI_1
/SPI_CS
/PCM_CE
/PF_WP
R109 3.9K
C109
0.1uF
R127 4.7K
+3.3V_Normal
USB1_CTL
MODEL_OPT_0
PWM0
FRC_SDA
R129 22
PWM1
+3.3V_Normal
PWM2
WIRELESS_DL_RX
R136 22
RGB_DDC_SCL
WIRELESS_DL_TX
R121
1K
FE_TS_CLK
AR101
22
R102
3.3K
R14733
R15133
PWM0
PWM1
AUD_LRCH
AUD_MASTER_CLK
AUD_SCK
+3.3V_Normal
R111 22
R112 22
R156 10K
/FLASH_WP
/RST_HUB
C102
10uF
IC104
M24M01-HRMN6TP
3
E2
2
E1
4
VSS
1
NC
5SDA
6SCL
7WP
8VCC
P3903
12505WS-03A00
OPT
1
2
3
4
P3904
12505WS-03A00
OPT
1
2
3
4
NEC_SDA
I2C_SDA
I2C_SCL
AMP_SCL
R142 3.3K R145 2.2K R143 3.3K R144 2.2K
AMP_SDA
+3.3V_Normal
NEC_SCL
CONTROL_ATTEN
R160
1K
IC102-*2
NAND01GW3A2CN6E
1GBIT
26 NC_17
27 NC_18
28 NC_19
29 I/O0
30 I/O1
31 I/O2
32 I/O3
33 NC_20
34 NC_21
35 NC_22
36 VSS_2
37 VDD_2
38 NC_23
39 NC_24
40 NC_25
41 I/O4
42 I/O5
43 I/O6
44 I/O7
45 NC_26
46 NC_27
47 NC_28
48 NC_29
17
AL
3
NC_3
6
NC_6
16
CL
15
NC_10
14
NC_9
13
VSS_1
12
VDD_1
11
NC_8
10
NC_7
9
E
8
R
7
RB
4
NC_4
5
NC_5
25 NC_16 24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
W/PIF_SPI_CS
R1500
R140 1K R141 1K
MODEL_OPT_6
R1100
LGE101D (S7 Non_Tcon/RM)
IC101
S7_DIVX
PCM_D0
U22
PCM_D1
T21
PCM_D2
T22
PCM_D3
AB18
PCM_D4
AC18
PCM_D5
AC19
PCM_D6
AC20
PCM_D7
AC21
PCM_A0
U21
PCM_A1
V21
PCM_A2
Y22
PCM_A3
AA22
PCM_A4
R22
PCM_A5
R21
PCM_A6
T23
PCM_A7
T24
PCM_A8
AA23
PCM_A9
Y20
PCM_A10
AB17
PCM_A11
AA21
PCM_A12
U23
PCM_A13
Y23
PCM_A14
W23
PCM_REG_N
W22
PCM_OE_N
AA17
PCM_WE_N
V22
PCM_IORD_N
W21
PCM_IOWR_N
Y21
PCM_CE_N
AA20
PCM_IRQA_N
V23
PCM_CD_N
P23
PCM_WAIT_N
R23
PCM_RESET
P22
PCM_PF_CE0Z
AC17
PCM_PF_CE1Z
AB20
PCM_PF_OEZ
AA18
PCM_PF_WEZ
AB21
PCM_PF_ALE
AB19
PCM_PF_AD[15]
AD17
PCM_PF_RBZ
AA19
UART_TX2/GPIO65
M23
UART_RX2/GPIO64
N23
DDCR_DA/GPIO71
M22
DDCR_CK/GPIO72
N22
DDCA_DA/UART0_TX
A5
DDCA_CK/UART0_RX
B5
PWM0/GPIO66
K23
PWM1/GPIO67
K22
PWM2/GPIO68
G23
PWM3/GPIO69
G22
PWM4/GPIO70
G21
SAR0/GPIO31
C6
SAR1/GPIO32
B6
SAR2/GPIO33
C8
SAR3/GPIO34
C7
SAR4/GPIO35
A6
TCON0/POL N21
TCON2/GSP_R/GCLK1 M21
TCON4/CPV/GSC/GCLK3 L22
TCON6/FLK L21
TCON8/CS2/FLK3 P21
GPIO36/UART3_RX K21
GPIO37/UART3_TX L23
GPIO38 K20
GPIO39 L20
GPIO40 M20
GPIO41 G20
GPIO42 G19
GPIO50/UART1_RX F20
GPIO51/UART1_TX F19
GPIO6/PM0/INT0 E7
GPIO7/PM1/PM_UART_TX D7
GPIO8/PM2 E11
GPIO9/PM3 G9
GPIO10/PM4 F9
GPIO11/PM5/PM_UART_RX/INT1 C5
PM_SPI_CS1/GPIO12/PM6 E8
PM_SPI_WP1/GPIO13/PM7 E9
PM_SPI_WP2/GPIO14/PM8/INT2 F7
GPIO15/PM9 F6
PM_SPI_CS2/GPIO16/PM10 D8
GPIO17/PM11/INT3 G12
GPIO18/PM12/INT4 F10
PM_SPI_CK/GPIO1 D9
GPIO0/PM_SPI_CZ D11
PM_SPI_DI/GPIO2 E10
PM_SPI_DO/GPIO3 D10
TS0_CLK AA9
TS0_VLD AA5
TS0_SYNC AA10
TS0_D0 AB5
TS0_D1 AC4
TS0_D2 Y6
TS0_D3 AA6
TS0_D4 W6
TS0_D5 AA7
TS0_D6 Y9
TS0_D7 AA8
TS1_CLK AC5
TS1_VLD AC6
TS1_SYNC AB6
TS1_D0 AC10
TS1_D1 AB10
TS1_D2 AC9
TS1_D3 AB9
TS1_D4 AC8
TS1_D5 AB8
TS1_D6 AC7
TS1_D7 AB7
MPIF_CLK D12
MPIF_CS_N D14
MPIF_BUSY E14
MPIF_D0 E12
MPIF_D1 F12
MPIF_D2 D13
MPIF_D3 E13
LGE101 (S7 NON_TON/DiX/RM)
IC101-*1
S7_NON_DIVX
NC_48
AE1
NC_78
AF16
NC_64
AF1
NC_50
AE3
NC_45
AD14
NC_34
AD3
NC_77
AF15
NC_65
AF2
NC_62
AE15
NC_33
AD2
NC_47
AD16
NC_46
AD15
NC_63
AE16
NC_66
AF3
NC_76
AF14
NC_32
AD1
NC_44
AD13
NC_61
AE14
NC_60
AE13
NC_51
AE4
NC_36
AD5
NC_67
AF4
NC_35
AD4
NC_49
AE2
NC_71
AF8
NC_40
AD9
NC_56
AE9
NC_72
AF9
NC_58
AE11
NC_69
AF6
NC_53
AE6
NC_74
AF11
NC_37
AD6
NC_43
AD12
NC_52
AE5
NC_75
AF12
NC_68
AF5
NC_59
AE12
NC_57
AE10
NC_70
AF7
NC_42
AD11
NC_38
AD7
NC_41
AD10
NC_54
AE7
NC_73
AF10
NC_39
AD8
NC_55
AE8
NC_12
Y11
GND_105
Y19
LVACLKP/LLV6P/BLUE[3] W26
LVACLKN/LLV6N/BLUE[2] W25
LVA0P/LLV3P/BLUE[9] U26
LVA0N/LLV3N/BLUE[8] U25
LVA1P/LLV4P/BLUE[7] U24
LVA1N/LLV4N/BLUE[6] V26
LVA2P/LLV5P/BLUE[5] V25
LVA2N/LLV5N/BLUE[4] V24
LVA3P/LLV7P/BLUE[1] W24
LVA3N/LLV7N/BLUE[0] Y26
LVA4P/LLV8P Y25
LVA4N/LLV8N Y24
LVBCLKP/LLV0P/GREEN[5] AC26
LVBCLKN/LLV0N/GREEN[4] AC25
LVB0P/RLV6P/RED[1] AA26
LVB0N/RLV6N/RED[0] AA25
LVB1P/RLV7P/GREEN[9] AA24
LVB1N/RLV7N/GREEN[8] AB26
LVB2P/RLV8P/GREEN[7] AB25
LVB2N/RLV8N/GREEN[6] AB24
LVB3P/LLV1P/GREEN[3] AC24
LVB3N/LLV1N/GREEN[2] AD26
LVB4P/LLV0P/GREEN[1] AD25
LVB4N/LLV0N/GREEN[0] AD24
RLV3P/RED[7] AD23
RLV3N/RED[6] AE23
RLV0P/LVSYNC AE26
RLV0N/LHSYNC AE25
RLV1N/LCK AF26
RLV2P/RED[9] AF25
RLV1P/LDE AE24
RLV2N/RED[8] AF24
RLV4P/RED[5] AF23
RLV4N/RED[4] AD22
RLV5P/RED[3] AE22
RLV5N/RED[2] AF22
TCON3/OE/GOE/GCLK2 AD19
TCON15/SCAN_BLK1 AE19
TCON18/CS7/GCLK5 AD21
TCON19/CS8/GCLK6 AE21
TCON11/CS5/HCON AF21
TCON10/CS4/OPT_N AD20
TCON9/CS3/OPT_P AE20
TCON16/WPWM AF20
TCON12/DPM AF19
TCON1/STV/GSP/VST AD18
TCON5/TP/SOE AE18
TCON14/SACN_BLK AF18
TCON21/CS10/VGH_ODD AB22
TCON20/CS9/VGH_EVEN AB23
TCON13/LEDON AC23
TCON17/CS6/GCLK4 AC22
NC_26 AB16
NC_19 AA14
NC_30 AC15
NC_15 Y16
NC_31 AC16
NC_29 AC14
NC_21 AA16
NC_20 AA15
NC_11 Y10
NC_17 AA11
NC_25 AB15
NC_24 AB14
MDS62110204
GAS2
22_26LE6500
MDS62110204
GAS1
22_26LE6500
MDS62110204
GAS3
22_26LE6500
FLASH/EEPROM/GPIO
GP2_Saturn7
DIMMING
URSA degug port
for WIRELESS READY
for SERIAL FLASH
/PF_CE0
H : Serial Flash
L : NAND Flash
/PF_CE1
H : 16 bit
L : 8 bit
Boot from SPI flash : 1’b0
Boot from NOR flash : 1’b1
Addr:10101--
I2C
A0’h
<T3 CHIP Config>
(AUD_SCK, AUD_MASTER_CLK, PWM1, PWM0)
EEPROM
<T3 CHIP Config(AUD_LRCH)>
for ETHERNET PHY
HDCP EEPROM
NAND FLASH MEMORY
from CI SLOT
TO SCART1
MIPS_no_EJ_NOR8 : 4’h3 (MIPS as host. No EJ PAD. Byte mode NAND flash.)
MIPS_EJ1_NOR8 : 4’h4 (MIPS as host. EJ use PAD1. Byte mode NAND flash.)
MIPS_EJ2_NOR8 : 4’h5 (MIPS as host. EJ use PAD2. Byte mode NAND flash.)
B51_Secure_no scramble : 4’hb (8051 as host. Internal SPI flash secure boot, no scramble)
B51_Sesure_scramble : 4’hc (8051 as host. Internal SPI flash secure boot with scarmble)
for SYSTEM/HDCP
EEPROM&URSA3
Internal demod out
/External demod in
$0.199
Ver. 2.0
1
PLACE UNDER TUNER

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.5V_ST
OCD1B
R1018 22
OCD1A
+3.5V_ST
SIDE_HP_MUTE
R1080
22
MODEL1_OPT_2
POWER_ON/OFF1
R1062 22
R1060 22
OPT
OCD1B
C1003
0.1uF
NEC_RXD
R1036 22
KEY1
+3.5V_ST
R1067 22
R1048 22
R1081 22
TP1001
RL_ON
OCD1A
R1043 22
R1059 22
IR
WIRELESS_DETECT
R1065 22
R1073 10K
POWER_ON/OFF2_2
CEC_REMOTE_NEC
IC1002
UPD78F0513AGA-GAM-AX
NEC_MICOM
1
P60/SCL0
2
P61/SDA0
3
P62/EXSCL0
4
P63
5
P33/TI51/TO51/INTP4
6
P75
7
P74
8
P73/KR3
9
P72/KR2
10
P71/KR1
11
P70/KR0
12
P32/INTP3/OCD1B
13
P31/INTP2/OCD1A
14
P30/INTP1
15
P17/TI50/TO50
16
P16/TOH1/INTP5
17
P15/TOH0
18
P14/RXD6
19
P13/TXD6
20
P12/SO10
21
P11/SL10/RXD0
22
P10/SCK10/TXD0
23
AVREF
24
AVSS
25 ANI7/P27
26 ANI6/P26
27 ANI5/P25
28 ANI4/P24
29 ANI3/P23
30 ANI2/P22
31 ANI1/P21
32 P20/ANI0
33 P130
34 P01/TI010/TO00
35 P00/TI000
36 P140/PCL/INTP6
37 P120/INTP0/EXLVI 38 P41 39 P40 40 RESET 41 P124/XT2/EXCLKS 42 P123/XT1 43 FLMD0 44 P122/X2/EXCLK/OCD0B 45 P121/X1/OCD0A 46 REGC 47 VSS 48 VDD
FLMD0
+3.5V_ST
R1019 22
R1051 22
R1023 22
R1041 22
SCART1_MUTE
POWER_DET
R1061 22
OPT
NEC_ISP_Tx
P1001
12505WS-12A00
MICOM_DEBUG
1
2
3
4
5
6
7
8
9
10
11
12
13
OCD1B
POWER_ON/OFF2_1
NEC_ISP_Rx
R1007 100
SW1001
JTP-1127WEM
12
4 3
IC1001
M24C16-WMN6T
3
NC/E2
2
NC/E1
4
VSS
1
NC/E0
5SDA
6SCL
7WC
8VCC
R1076 22
NEC_SCL
C1009 1uF
+3.5V_ST
MODEL1_OPT_3
R1037 22
Q1001
2SC3052
E
B
C
NEC_ISP_Rx
GND
R1069 22
+3.5V_ST
MODEL1_OPT_1
MICOM_RESET
C1002 0.1uF
OLP
RF_RESET
R1014 4.7K
R1001
47K
TP1002
R1054 22 19-22_LAMP
LED_B/LG_LOGO
R1039 22
R1070 100
FLMD0
WIRELESS_PWR_EN
NEC_EEPROM_SDA
NEC_SDA
INV_CTL
NEC_EEPROM_SDA
TP1003
R1005 10K AMP_MUTE
NEC_ISP_Rx
AMP_RESET_N
NEC_ISP_Tx
MICOM_RESET
R1049 22
OPT
PANEL_CTL
KEY2
OCD1A
R1072 10K
R1063 22
MODEL1_OPT_3
R1056 22
C1006 0.1uF
R1064 22
MODEL1_OPT_0
+3.5V_ST
R1066 22
R1008
22
+3.5V_ST
+3.5V_ST
NEC_EEPROM_SCL
R1050 10K
MODEL1_OPT_0
R1015 4.7K
R1068 22
NEC_ISP_Tx
NEC_EEPROM_SCL
RF_ENABLE
R1046 47K
OPC_EN
EDID_WP
R1010 22
R1013 22
MODEL1_OPT_1
R1044 10K
OPT
R1045 10K
OPT
R1057 22
R1078 22
LED_R/BUZZ
R1006 10K
NEC_TXD
SOC_RESET
R1002 10K
R1083 10K
OPT
R1084
10K
OPT
+3.5V_ST
R1086 47K
OPT
+3.5V_ST
R1089 20K 1/16W 1%
R1047 20K
1/16W
1%
R1034
4.7M
OPT
R1071 10K
B/L_LED
R1011 10K
TACT_KEY
R1004 10K
PWM_LED
R1012 10K
B/L_LAMP
R1009 10K
PWM_BUZZ/IIC_LED
R1075 10K
TOUCH_KEY
R1074 10K R1079 10K
OPT
R1090 22
MODEL1_OPT_2
WIRELESS_SW_CTRL
R1030 10K
R1091 10K
CEC_ON/OFF R1003 0
R1020 0
R1052 10K
C1010
0.1uF
R1055 22
C1007 15pF C1008 15pF
X1002
32.768KHz
MICOM
GP2_Saturn7M Ver. 1.4
for Debugger
 
MICOM MODEL OPTION
EEPROM for Micom
5
B/L_LED
PIN NO.
11
HIGH
MODEL OPTION
B/L_LAMP
MODEL_OPT_2
MODEL_OPT_0
LOWPIN NAME
MODEL_OPT_1
8
MODEL_OPT_3
30
31 GPIO_LED NON_GPIO_LED
TOUCH_KEY TACT_KEY
PWM_LED
PWM_BUZZ/IIC_LED
MODEL_OPT_1 MODEL_OPT_2 MODEL_OPT_0 MODEL_OPT_3
LOW LOW LOW LOW
LOW LOW
LOW
LOW
LOWLOW
HIGH HIGH
HIGH HIGH HIGH
HIGH
HIGH HIGH
LOW LOW
LD350/450/550
19/22/26LE3300(5500)
32/37/42/47/55LE5300(10)
LD420
LE7300
HIGH HIGH TBD

Fiber Optic
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
C1125
OPT
OPT
DSUB_R-
D1116
5.6V
OPT
SPDIF_OUT
2:X18
+3.3V_Normal
C1127
18pF
50V
R1142
10K
D1113
30V
JK1104 SPG09-DB-010
1RED 2GREEN 3BLUE 4GND_1 5DDC_GND
6RED_GND 7GREEN_GND 8BLUE_GND 9NC
10 SYNC_GND
11 GND_2 12 DDC_DATA 13 H_SYNC 14 V_SYNC 15 DDC_CLOCK
16SHILED
R1108
15K
DSUB_G-
D1117
5.6V
D1110
30V
EDID_WP
D1114
5.6V
OPT
DSUB_G+
C1108
100pF
50V
C1126
68pF
50V
OPT
D1111
30V
R1126
22
OPT
DSUB_HSYNC
C1128
18pF
50V
RGB_DDC_SCL
R1138
0
R1107
15K
R1136
0
R1103
470K
PC_R_IN 2:S16 R1140
4.7K
DSUB_R+
R1111
10K
D1101
5.6V
OPT
AMOTECH
C1117
0.1uF
16V
OPT
R1102
470K
DSUB_B-
IC1105
AT24C02BN-10SU-1.8
3
A2
2
A1
4
GND
1
A0
5SDA
6SCL
7WP
8VCC
JK1103
JST1223-001
1
GND
2
VCC
3
VINPUT
4
FIX_POLE
C1129
0.1uF
16V
R1139
4.7K
+3.3V_Normal
C1121
100pF
50V
R1147
1K
C1123
OPT
OPT
RGB_DDC_SDA
DSUB_B+
DSUB_VSYNC
D1109
30V
R1110
10K
C1107
100pF
50V
D1102
5.6V
OPT
AMOTECH
C1124
OPT
OPT
C1122
68pF
50V
OPT
+5V_Normal
R1143
22
D1115
ENKMC2838-T112
A1
C
A2
PC_L_IN 2:S16
IC1104
NL17SZ00DFT2G
OPT
3
GND
2
B
4Y
1
A5VCC
R1134
0
DSUB_DET
D1112
30V
R1148
0
R1150
0
R1146
10K
R1127
0
C1131
0.1uF
16V
R1141
22
R1152
4.7K
OPT
Q1103
MMBT3904-(F)
E
B
C
HP_ROUT
2:X19
+3.5V_ST
R1130 10K
C1115
1000pF
50V
OPT
SIDE_HP_MUTE
C1116
1000pF
50V
OPT
+3.3V_Normal
SPK_R-_HOTEL
2:X19
SPK_R+_HOTEL
2:X19
HP_DET
R1155
1K
HP_LOUT
2:X19
Q1101
MMBT3904-(F)
E
B
C
Q1102
MMBT3904-(F)
E
B
C
C1119
10uF
16V
EXCEPT_CHINA_HOTEL_OPT
C1118
10uF
16V
EXCEPT_CHINA_HOTEL_OPT
Q1104
MMBT3904-(F)
E
B
C
R1125
1K
R1128
1K
R1133
75
R1135
75
R1137
75
JK1102
PEJ027-01
6B T_TERMINAL2
7B B_TERMINAL2
5T_SPRING
4R_SPRING
7A B_TERMINAL1
6A T_TERMINAL1
3E_SPRING
R1112
0
R1113
0
JK3301
KJA-PH-0-0177
3DETECT
4L
5GND
1R
Q1105 ISA1530AC1
E
B
C
Q1106
2SC3052
E
B
C
R1129
3.3K
COMMON AREA
GP2_Saturn7M
5.15 Mstar Circuit Application
PC AUDIO RGB PC
SPDIF OPTIC JACK
COMMON AREA
Ver. 1.0
New Item Development
EARPHONE BLOCK
9

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
C1101 0.33uF
C1105
0.1uF
R1157 0
R1156 0
R1124
100
NEC_RXD
C1106
0.1uF
+3.5V_ST
R1153 0
R1154 0
D1108
30V
CDS3C30GTH
IR_OUT
C1103
0.1uF
S7_TXD1
D1107
30V
CDS3C30GTH
R1114
4.7K
OPT
NEC_TXD
IC1101
MAX3232CDR
EAN41348201
3
C1-
2
V+
4
C2+
1
C1+
6
V-
5
C2-
7
DOUT2
8
RIN2 9ROUT2
10 DIN2
11 DIN1
12 ROUT1
13 RIN1
14 DOUT1
15 GND
16 VCC
C1104
0.1uF
R1109
4.7K
OPT
C1102
0.1uF
+3.5V_ST
S7_RXD1
R1123
100
R1122
0
OPT
JK1101
SPG09-DB-009
1
2
3
4
5
6
7
8
9
10
RS232C
RS232C 9PIN
Ver. 2.0GP2_Saturn7
10

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
B-MA0
A-TMDML
A-TMWEB
B-TMDQU6
A-MDQL2
A-MDQU4
B-TMDQL3
A-MDQSLB
B-TMDQU6
B-TMA7
A-TMCKE
A-TMCKB
B-MDMU
C1236
0.1uF
A-MDQSLB
A-MA10
A-TMA10
B-TMCKB
A-TMA3
B-TMDQSUB
B-TMWEB
B-TMA3
A-TMODT
A-TMDQU0
A-TMDQSU
B-TMDQL6
B-TMCKE
A-TMBA1
B-MODT
B-MDQU2
B-MVREFDQ
B-MDQL0
B-TMA5
B-TMCASB
B-TMBA1
VCC_1.5V_DDR
A-MBA0
A-TMDQU6
A-MDQU2
A-MDQL7
B-MDQSLB
A-MVREFCA
B-MA9
B-MA2
A-MDQL3
A-MODT
B-MDQL4
A-TMDQU0
B-TMA13
A-MCKB
A-TMDQL7
B-TMDQU2
B-MRASB
B-TMDQU4 B-MDQU6
A-TMDQU3
B-MA7
B-MDQU7
B-TMDQL4
A-TMA2
A-MDQL0
B-TMODT
A-MDQSU
L1201
A-MBA1
B-MDQU6
A-TMODT
B-MWEB
B-MDQL6
A-MCKE
A-TMDQL1
A-TMA12
A-MDQL1
C1231
0.1uF
B-MVREFCA
A-TMRASB
B-MDQL1
A-TMDQL7
A-TMDQL6
A-MDQU7
A-MDQU6
C1227
0.1uF
A-MDQL3
B-MCASB
A-MDQU3
B-TMA10
B-TMA11
+1.5V_DDR
A-TMCK
A-MDQL4
B-MA5
B-TMODT
B-TMA12
A-MCK
C1239
0.1uF
A-TMA2
A-MA9
C1221
0.1uF
B-MDQL2
A-TMDQL0
B-TMDQU7
A-MCASB
B-TMDQU3
B-TMA1
A-MDQL6
B-MA8
B-MA3
A-TMCK
B-MDQU1
C1238
0.1uF
C1244
0.1uF
B-MA12
A-TMRASB
A-MA3
A-TMRESETB
B-TMRASB
A-MA5
A-TMDQL4
C1226
0.1uF
16V
A-MVREFDQ
C1202
1000pF
B-MDQL4
C1230
0.1uF
A-MA11
C1235
0.1uF
R1202
1K 1%
A-TMCASB
A-MA2
B-TMA7
R1224
1K 1%
A-MCK
B-MCK
B-MDQU5
A-MDQU5 A-TMDQU2
B-TMCASB
B-TMA4
B-TMDQL0
C1219
0.1uF
B-TMDQL7
C1201
0.1uF
B-TMDQL4
B-TMDQL2
B-MODT
C1206
0.1uF
B-TMCK
B-TMDQU1
B-TMDQL2
C1224
0.1uF
A-MDQU6
R1228
1K 1%
B-TMDQU0
C1232
0.1uF
B-MDQU7
A-MA9
A-TMA0
A-MDQL1
B-TMDQL5
R1203
240
1%
B-TMA6
C1242
0.1uF
B-MA9
B-TMDQL1
A-TMA4
B-TMA12
A-MODT
B-TMDML
B-MDQSUB
B-TMA3
B-MVREFCA
B-MA5
A-MDQSL
A-MA1
B-TMDMU
A-TMDQSL
B-MBA0
C1203
0.1uF
C1237
0.1uF
B-MA12
VCC_1.5V_DDR
A-TMDQL1
A-MA11
B-MCKE
B-MDQSU
B-MDQL7
B-MA4
B-MA4
R1227
1K 1%
A-TMDQSLB
A-MDQU1
B-MDQU5
A-TMCKB
A-TMA6
A-MA6
C1223
0.1uF
VCC_1.5V_DDR
A-TMA8
C1248
0.1uF
B-TMA4
B-MDQL2
A-TMRESETB
C1247
1000pF
B-MDQU2
A-TMDMU
B-TMA9
B-MDQU0
B-TMRESETB
B-TMDQU2
A-TMDMU
B-MA13
C1241
0.1uF
A-MA0
B-TMA8
A-TMDQL5
A-TMDQU6
A-MA4
A-TMDQL3
A-MDML
B-MDQL3
B-MDQU3
B-TMBA0
VCC_1.5V_DDR
R1204
1K 1%
A-MRESETB
A-MWEB
A-TMDQU1
B-MA0
A-TMA13
A-MBA2
A-TMDQSUB
A-TMDQL5
VCC_1.5V_DDR
A-TMBA1
VCC_1.5V_DDR
B-TMDQL6
B-MDQL7
B-TMA10
B-MRESETB
C1214
0.1uF
R1205
1K 1%
A-MA6
B-MA2
B-TMA13
A-TMBA2
C1228
0.1uF
C1208
0.1uF
C1245
0.1uF
A-MRASB
C1210
0.1uF
A-MDQL5
B-MWEB
C1218
0.1uF
A-TMCKE
A-MDQL4
C1229
0.1uF
B-MDQL1
C1233
0.1uF
A-MDQL6
B-TMA11
B-TMDQSU
A-MA3
A-TMDQSL
A-TMDQSLB
R1226
240
1%
A-MA7
B-MA8
A-TMDQL6
A-TMBA0
A-MDQSU
A-MA13
A-MDQSUB
B-MA1
C1250
0.1uF
A-TMA10
B-TMDQU1
B-TMWEB
B-MDQU3
B-TMRESETB
A-MA13
B-TMDML
B-MCKE
B-TMA0
A-MA8
A-MCKB
A-TMDQL3
A-TMA5
A-TMDQU4
A-MA7
B-TMDQSU
A-TMDQSUB B-MDML
A-MBA2
B-TMDQU4
B-TMA5
A-MDQL2
B-TMDQU0
A-MVREFCA
C1204
1000pF
A-MBA0
C1215
0.1uF
A-MA8
B-MRESETB
B-TMDQSLB
B-TMDQSL
A-MRASB
B-TMA0
B-MBA1
A-TMDQU7
A-MA1
B-MDQU0
A-MDQU0
B-MRASB
B-TMA1
B-TMBA2
A-TMDQL2
A-TMDQU2
A-MRESETB
A-TMDQL2
A-MDQL0
A-TMDML
B-MDQL5
B-TMA8
B-MBA1
A-TMA13
B-MDQSL
B-MDQL3
A-MDQL7
A-TMDQSU
C1212
0.1uF
A-TMA5
A-TMDQU4
B-MDQL0
A-MWEB
B-TMA9
A-TMA0
B-MA10
A-MA12
A-MCKE
B-TMDQSL
A-TMA4
B-TMDQSLB
B-MDQU4
R1225
1K 1%
B-TMDQL1
C1249
1000pF
B-MBA2
B-TMBA1
B-MDQU1
A-MA0
B-MA10
A-MVREFDQ
B-TMDQU7
B-MDQSUB
C1243
0.1uF
A-MDQU2
B-MA13
C1211
0.1uF
A-TMA1
A-MBA1
A-MCASB
B-TMDQL0
B-MDQSL
A-TMA8
B-TMDQL7
A-MDQU3
A-MA5
B-MVREFDQ
B-MA1
B-MDML
B-MDQSU
B-MA6
B-MDMU
B-MCKB
A-MDMU
B-TMDQU5
A-TMDQL0
B-MCK
B-MCASB
A-TMDQU7
A-TMCASB
VCC_1.5V_DDR
A-MA4
VCC_1.5V_DDR
A-MDQU4
B-TMDMU
A-TMA6
A-TMA12
B-TMCK
R1201
1K 1%
B-TMBA2
C1216
0.1uF
C1220
0.1uF
A-MDML
B-TMBA0
VCC_1.5V_DDR
A-MDMU
B-MDQL6
A-MDQU1
B-MBA0
B-TMDQU3
A-TMDQL4
A-MA10
B-TMRASB
B-MCKB
B-MA11
B-MDQU4
A-TMA11
A-TMWEB
A-TMDQU3
B-MA11
B-MBA2
B-TMCKE
B-MDQL5
B-TMDQSUB
A-TMA7
A-TMA9
B-TMA6
B-TMDQL5
B-MA6
A-TMA9
B-MA7
B-MA3
C1222
0.1uF
A-TMA1
A-TMA11
A-MA2
B-TMDQU5
C1217
0.1uF
A-MDQL5
A-TMBA0
C1213
0.1uF
C1207
0.1uF
A-TMDQU1
A-TMDQU5
A-TMDQU5
A-TMBA2
B-TMA2
A-TMA3
C1234
0.1uF
A-MA12
A-MDQU0
B-TMA2
B-MDQSLB
B-TMCKB
A-MDQSUB
A-MDQSL
B-TMDQL3
A-TMA7
A-MDQU7
A-MDQU5
C1205 10uF
C1225
10uF
10V
C1246 10uF
VCC_1.5V_DDR
R1231
10K
VCC_1.5V_DDR
R1232
10K
R1223
10
R1217
10
R1216
10
R1211
10
R1213
10
R1222
10
R1215
10
R1220
10
R1218
10
R1221
10
R1210
10
R1206
10
R1214
10
R1208
10
R1207
10
R1209
10
R1219
10
R1212
10
AR1218
10
AR1215
10
AR1208
10
AR1219
10
AR1216
10
AR1214
10
AR1211
10
AR1220
10
AR1201
10
AR1202
10
AR1217
10
AR1204
10
AR1207
10
AR1210
10
AR1213
10
AR1209
10
AR1203
10
AR1205
10
AR1212
10
AR1206
10
R123410K B-MCKE
A-MCKE R1233 10K
H5TQ1G63BFR-H9C
IC1201
A0 N3
A1 P7
A2 P3
A3 N2
A4 P8
A5 P2
A6 R8
A7 R2
A8 T8
A9 R3
A10/AP L7
A11 R7
A12/BC N7
A13 T3
A15 M7
BA0 M2
BA1 N8
BA2 M3
CK J7
CK K7
CKE K9
CS L2
ODT K1
RAS J3
CAS K3
WE L3
RESET T2
DQSL F3
DQSL G3
DQSU C7
DQSU B7
DML E7
DMU D3
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
DQU0 D7
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ1G63BFR-H9C
IC1202
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
LGE101D (S7 Non_Tcon/RM)
IC101
S7_DIVX/NON_RM
A_DDR3_A0/DDR2_A13
B8
A_DDR3_A1/DDR2_A8
B9
A_DDR3_A2/DDR2_A9
A8
A_DDR3_A3/DDR2_A1
C21
A_DDR3_A4/DDR2_A2
B10
A_DDR3_A5/DDR2_A10
A22
A_DDR3_A6/DDR2_A4
A10
A_DDR3_A7/DDR2_A3
B22
A_DDR3_A8/DDR2_A6
C9
A_DDR3_A9/DDR2_A12
C23
A_DDR3_A10/DDR2_RASZ
B11
A_DDR3_A11/DDR2_A11
A9
A_DDR3_A12/DDR2_A0
C10
A_DDR3_A13/DDR2_A7
B23
A_DDR3_BA0/DDR2_BA2
B21
A_DDR3_BA1/DDR2_CASZ
A11
A_DDR3_BA2/DDR2_A5
A23
A_DDR3_MCLK/DDR2_MCLK
A12
A_DDR3_MCLKZ/DDR2_MCLKZ
C11
A_DDR3_CKE/DDR2_DQ5
B12
A_DDR3_ODT/DDR2_ODT
C20
A_DDR3_RASZ/DDR2_WEZ
A20
A_DDR3_CASZ/DDR2_BA1
B20
A_DDR3_WEZ/DDR2_BA0
A21
A_DDR3_RESETB
C22
A_DDR3_DQSL/DDR2_DQS0
C16
A_DDR3_DQSLB/DDR2_DQSB0
B16
A_DDR3_DQSU/DDR2_DQSB1
A16
A_DDR3_DQSUB/DDR2_DQS1
C15
A_DDR3_DML//DDR2_DQ13
A14
A_DDR3_DMU/DDR2_DQ6
B18
A_DDR3_DQL0/DDR2_DQ3
C18
A_DDR3_DQL1/DDR2_DQ7
B13
A_DDR3_DQL2/DDR2_DQ1
A19
A_DDR3_DQL3/DDR2_DQ10
C13
A_DDR3_DQL4/DDR2_DQ4
C19
A_DDR3_DQL5/DDR2_DQ0
A13
A_DDR3_DQL6/DDR2_CKE
B19
A_DDR3_DQL7/DDR2_DQ2
C12
A_DDR3_DQU0/DDR2_DQ15
A15
A_DDR3_DQU1/DDR2_DQ9
A17
A_DDR3_DQU2/DDR2_DQ8
B14
A_DDR3_DQU3/DDR2_DQ11
C17
A_DDR3_DQU4/DDR2_DQM1
B15
A_DDR3_DQU5/DDR2_DQ12
A18
A_DDR3_DQU6/DDR2_DQM0
C14
A_DDR3_DQU7/DDR2_DQ14
B17
B_DDR3_A0/DDR2_A13 A25
B_DDR3_A1/DDR2_A8 B24
B_DDR3_A2/DDR2_A9 A24
B_DDR3_A3/DDR2_A1 P25
B_DDR3_A4/DDR2_A2 C24
B_DDR3_A5/DDR2_A10 P26
B_DDR3_A6/DDR2_A4 B26
B_DDR3_A7/DDR2_A3 R24
B_DDR3_A8/DDR2_A6 B25
B_DDR3_A9/DDR2_A12 T26
B_DDR3_A10/DDR2_RASZ D24
B_DDR3_A11/DDR2_A11 A26
B_DDR3_A12/DDR2_A0 C25
B_DDR3_A13/DDR2_A7 T25
B_DDR3_BA0/DDR2_BA2 P24
B_DDR3_BA1/DDR2_CASZ C26
B_DDR3_BA2/DDR2_A5 R26
B_DDR3_MCLK/DDR2_MCLK D26
B_DDR3_MCLKZ/DDR2_MCLKZ D25
B_DDR3_CKE/DDR2_DQ5 E24
B_DDR3_ODT/DDR2_ODT N25
B_DDR3_RASZ/DDR2_WEZ M26
B_DDR3_CASZ/DDR2_BA1 N24
B_DDR3_WEZ/DDR2_BA0 N26
B_DDR3_RESETB R25
B_DDR3_DQSL/DDR2_DQS0 J25
B_DDR3_DQSLB/DDR2_DQSB0 J24
B_DDR3_DQSU/DDR2_DQSB1 H26
B_DDR3_DQSUB/DDR2_DQS1 H25
B_DDR3_DML/DDR2_DQ13 F26
B_DDR3_DMU/DDR2_DQ6 L24
B_DDR3_DQL0/DDR2_DQ3 L25
B_DDR3_DQL1/DDR2_DQ7 F24
B_DDR3_DQL2/DDR2_DQ1 L26
B_DDR3_DQL3/DDR2_DQ10 F25
B_DDR3_DQL4/DDR2_DQ4 M25
B_DDR3_DQL5/DDR2_DQ0 E26
B_DDR3_DQL6/DDR2_CKE M24
B_DDR3_DQL7/DDR2_DQ2 E25
B_DDR3_DQU0/DDR2_DQ15 G26
B_DDR3_DQU1/DDR2_DQ9 J26
B_DDR3_DQU2/DDR2_DQ8 G24
B_DDR3_DQU3/DDR2_DQ11 K25
B_DDR3_DQU4/DDR2_DQM1 H24
B_DDR3_DQU5/DDR2_DQ12 K26
B_DDR3_DQU6/DDR2_DQM0 G25
B_DDR3_DQU7/DDR2_DQ14 K24
R1235
56
1%
R1236
56
1%
C1209
0.01uF
25V
R1237 56
1%
R1238 56
1%
C1240
0.01uF
25V
DDR3(256MB)
GP2_Saturn7
DDR3 1.5V By CAP - Place these Caps near Memory
DDR3 1.5V By CAP - Place these Caps near Memory
CLose to DDR3
CLose to Saturn7M IC CLose to Saturn7M IC
Close to DDR Power Pin
Close to DDR Power Pin
CLose to DDR3
Ver. 2.0
21

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPI_SCK
/FLASH_WP
R1402
0
R1401
0
OPT
/SPI_CS
R1404 4.7K
C1401
0.1uF
+3.3V_Normal +3.3V_Normal
Q1401
KRC103S
E
B
C
+3.3V_Normal
R1403 10K
R1405
33
SPI_SDO
SPI_SDI
IC1401
MX25L8005M2I-15G
S_FLASH
3
WP#
2
SO
4
GND
1
CS#
5SI
6SCLK
7HOLD#
8VCC
S-Flash(1MB)
GP2_Saturn7 Ver. 2.0
23

THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FE_TS_DATA[3]
FE_TS_DATA[6]
FE_TS_DATA[7]
FE_TS_DATA[1]
FE_TS_DATA[4]
FE_TS_DATA[0]
FE_TS_DATA[2]
FE_TS_DATA[5]
R3758
82
R3734
0
+5V_TU
C3726
0.1uF
16V
FE_TS_SYNC
R3729 0
CHINA_OPT
R3721 0
CHINA_OPT
C3731
10uF
10V
OPT
Q3705 ISA1530AC1
E
B
C
R3745
10K
CHINA_OPT
+3.3V_TU
RF_SWITCH_CTL
R3722 0
CHINA_OPT
R3743
10K
CHINA_OPT
R3724 0
CHINA_OPT
C3708
0.1uF
16V
IF_AGC_MAIN
Q3703
ISA1530AC1
E
B
C
R3739 100
CHINA_OPT
+5V_General
TU_SIF
IF_AGC_SEL
R3762 0
OPT
TU_CVBSC3702
0.1uF 16V
C3704
0.1uF
16V
R3731 0
CHINA_OPT FE_TS_CLK
TUNER_RESET
R3738 100
CHINA_OPT
R3733
100K
R3730 0
CHINA_OPT
L3703
BLM18PG121SN1D
LNA2_CTL
R3701 0 CHINA_OPT
Q3704
2SC3052
OPT E
B
C
R3750
1K
OPT
C3725
0.1uF
16V
L3702
BLM18PG121SN1D
R3754
10K
OPT
R3737
2.2K
CHINA_OPT
R3702 0 CHINA_OPT
FE_TS_VAL_ERR
R3744
4.7K
CHINA_OPT
C3710
0.1uF
16V
FE_TS_DATA[0-7]
Q3701
ISA1530AC1
CHINA_OPT
E
B
C
C3707
100pF
50V
+5V_TU
IF_P_MSTAR
+3.3V_TU
C3703
100pF
50V
R3723 0
CHINA_OPT
R3707 0
OPT
+3.3V_TU
TU_SDA
C3716
22pF
50V
OPT
C3727
0.1uF
16V
DEMOD_SDA
+3.3V_Normal
+3.3V_TU
C3728
0.1uF
16V
OPT
C3714
22pF
50V
CHINA_OPT
C3724
0.1uF
16V
R3742
4.7K
CHINA_OPT
DEMOD_RESET
C3715
22pF
50V
OPT
+5V_TU
+3.3V_TU
R3749 0
CONTROL_ATTEN
R3728 0
CHINA_OPT
IF_N_MSTAR
R3727 0
CHINA_OPT
C3701
0.1uF
16V
Q3702
2SC3052
CHINA_OPT
E
B
C
L3701
BLM18PG121SN1D
CHINA_OPT
C3712
22pF
50V
CHINA_OPT
TU_SCL
R3753
4.7K
DEMOD_SCL
R3725 0
CHINA_OPT
R3726 0
CHINA_OPT
R3705 0
CHINA_OPT
+5V_TU
+5V_TU
R3732
100
C3709
0.01uF
25V
CHINA_OPT
R3760 0
EU_OPT
R3761 0
EU_OPT
C3737
100pF
50V
C3738
0.1uF
16V
R3704 0EU_OPT
R3752
220
R3751
220
R3755
470
R3740
1.2K R3741
1.2K
R3735
33
R3736
33
C3711
18pF
50V
C3713
18pF
50V
TU3702
TDTJ-S001D
EU_TUNER
14 3.3V
13 1.2V
5AS
12 GND
11 VIDEO
2BST_CNTL
10 NC
4NC[RF_AGC]
1ANT_PWR[OPT]
17 DIF_1
9SIF
8NC[IF_TP]
3+B
16 IF_AGC_CNTL
7SDA
6SCL
15 RESET
18 DIF_2
19
SHIELD
TU3701
TDFR-C035D
CN_HORIZONTAL_LG3911
1RF_S/W_CNTL
2BST_CNTL
3+B1[+5V]
4NC[RF_AGC]
5NC_1
6SCLT
7SDAT
8NC_2
9SIF
10 NC_3
11 VIDEO
12 GND
13 +B2[1.2V]
14 +B3[3.3V]
15 RESET
16 NC_4
17 SCL
18 SDA
19 ERR
20 SYNC
21 VALID
22 MCL
23 D0
24 D1
25 D2
26 D3
27 D4
28 D5
29 D6
30 D7
31
SHIELD
C7934
100uF
16V
CHINA_OPT
TU3701-*1
TDFR-C055D
CN_VERTICAL_LG3911
1RF_S/W_CNTL
2BST_CNTL
3+B1[+5V]
4NC[RF_AGC]
5NC_1
6SCLT
7SDAT
8NC_2
9SIF
10 NC_3
11 VIDEO
12 GND
13 +B2[1.2V]
14 +B3[3.3V]
15 RESET
16 NC_4
17 SCL
18 SDA
19 ERR
20 SYNC
21 VALID
22 MCL
23 D0
24 D1
25 D2
26 D3
27 D4
28 D5
29 D6
30 D7
31
SHIELD
C3722
22uF
16V
C3723
10uF
16V
0.1uF
C3734
OPT
R3748-*1
20K
1% BCD
R3708
10K
BCD
R3709
10K SEMTEK
R3756
0
5%
SEMTEK
C3732
10uF
10V
R3710
10K BCD
0.1uF
C3733
OPT
L3704
500
BCD
0.1uF
C3717
R3747-*1
39K
1% BCD
+3.3V_TU
R3748
5.1K
5%
SEMTEK
IC3701
AP2132MP-2.5TRG1
BCD
3
VIN
2
EN
4
VCTRL
1
PG
5
NC
6
VOUT
7
ADJ
8
GND
9
[EP]
+5V_Normal
+1.2V_TU
0.1uF
C3729
C3730
10uF
10V
R3756-*1
20K
1%
BCD
IC3701-*1
SC4215ISTRT
SEMTEK
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
R3747
9.1K
5%
SEMTEK
+1.2V_TU
VER 2.0
EU CAN TUNER
should be guarded by ground
The pull-up/down of LNA2_CTL
is depended on MODLE_OPT_1.
GPIO must be added for FE_BOOSTER_CTL
FE_BOOSTER_CTL
60mA
FE_AGC_SPEED_CTL
LGIT CAN NIM_H/N TUNER for EU & CHINA
close to TUNER
close to TUNER
close to TUNER
Close to the tuner
200mA
Pull-up can’t be applied
because of MODEL_OPT_2
GPIO must be added.
Close to the CI Slot
1. should be guarded by ground
2. No via on both of them
3. Signal Width >= 12mils
Signal to Signal Width = 12mils
Ground Width >= 24mils
OPTION : RF AGC
close to IF line
GP2_Saturn7
27
090916 de-rating solution
090916 de-rating solution
SEMTEK:Vout=0.8*(1+R1/R2)
BCD:Vout=0.6*(1+R1/R2)
R2
R1
BCD VOUT : 1.215V
SEMTEK VOUT : 1.248V

USB DOWN STREAM
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+5V_USB
R2305 0
+3.3V_Normal
L2301
MLB-201209-0120P-N2
120-ohm
R2306 0
D2301
5.6V
CDS3C05HDMI1
OPT
R2303
4.7K
OPT
IC2301
MIC2009YM6-TR
3ENABLE
2GND
4
FAULT/
1VIN 6
VOUT
5
ILIMIT
C2302
10uF
10V
C2304
0.1uF
C2303
10uF
10V
SIDE_USB_DM
SIDE_USB_DP
R2304 0
R2301 180
USB1_CTL
D2302
5.6V
CDS3C05HDMI1
OPT
USB1_OCD
R2302 47
R2307
10K
/RST_HUB
TP2301
JK2301
KJA-UB-4-0004
1234
5
USB1 OPTION
USB
$0.18
GP2_Saturn7M
USB
Ver. 1.0
39