LG 50PZ750 User manual

PLASMA TV
SERVICE MANUAL
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
CHASSIS : PU12A
MODEL : 50PZ750 50PZ750-UG
North/Latin A erica http://aic.lgservice.co
Europe/Africa http://eic.lgservice.co
Asia/Oceania http://biz.lgservice.co
Internal Use Only
Printed in Korea
P/NO : MFL67006103(1103-REV00)

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Only or training and service purposes
CONTENTS
CONTENTS ............................................................................................................................... 2
SAFETY PRECAUTIONS ...........................................................................................................3
SPECIFICATION.........................................................................................................................4
ADJUSTMENT INSTRUCTION ..................................................................................................6
BLOCK DIAGRAM ...................................................................................................................13
EXPLODED VIEW ...................................................................................................................14
CIRCUIT DIAGRAM .....................................................................................................................

- 3 - LGE Internal Use OnlyCopyright ©2011 LG Electronics Inc. All rights reserved.
Only or training and service purposes
SAFETY PRECAUTIONS
Many electrical and mechanical parts in this chassis have special sa ety-related characteristics. These parts are identi ied by in
the Schematic Diagram and Exploded View.
It is essential that these special sa ety parts should be replaced with the same components as recommended in this manual to
prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modi y the original design without permission o manu acturer.
Ge eral Guida ce
An isolatio Tra sformer should always be used during the
servicing o a receiver whose chassis is not isolated rom the AC
power line. Use a trans ormer o adequate power rating as this
protects the technician rom accidents resulting in personal injury
rom electrical shocks.
It will also protect the receiver and it's components rom being
damaged by accidental shorts o the circuitry that may be
inadvertently introduced during the service operation.
I any use (or Fusible Resistor) in this monitor is blown, replace it
with the speci ied.
When replacing a high wattage resistor (Oxide Metal Film
Resistor, over 1W), keep the resistor 10mm away rom PCB.
Keep wires away rom high voltage or high temperature parts.
Due to high vacuum and large sur ace area o picture tube,
extreme care should be used in ha dli g the Picture Tube.
Do not li t the Picture tube by it's Neck.
Leakage Curre t Cold Check(A te a Cold Check)
With the instrument AC plug removed rom AC source, connect
an electrical jumper across the two AC plug prongs. Place the
AC switch in the on position, connect one lead o ohm-meter to
the AC plug prongs tied together and touch other ohm-meter
lead in turn to each exposed metallic parts such as antenna
terminals, phone jacks, etc.
I the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1MΩ and 5.2MΩ.
When the exposed metal has no return path to the chassis the
reading must be in inite.
An other abnormality exists that must be corrected be ore the
receiver is returned to the customer.
Leakage Curre t Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do ot use a li e Isolatio Tra sformer duri g this check.
Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC
voltage measurements or each exposed metallic part. Any
voltage measured must not exceed 0.75 volt RMS which is
corresponds to 0.5mA.
In case any measurement is out o the limits speci ied, there is
possibility o shock hazard and the set must be checked and
repaired be ore it is returned to the customer.
Leakage Curre t Hot Check circuit
1.5 Kohm/10W
To Instrument's
exposed
METALLIC PARTS
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
AC Volt-meter
IMPORTANT SAFETY NOTICE
0.15uF

- 4 - LGE Internal Use OnlyCopyright ©2011 LG Electronics Inc. All rights reserve .
Only for training an service purposes
SPECIFICATIONS
NOTE : Specifications an others are subject to change without notice for improvement .
1. Application Range
(1) This spec sheet is applie all of PDP TV with PU12A chassis.
2. Specification
Each part is teste as below without special appointment.
(1) Temperature : 25 °C ± 5 °C (77 °F ± 9 °F), CST : 40 °C ± 5 °C
(2) Relative Humi ity : 65 % ± 10 %
(3) Power Voltage : Stan ar input voltage (100 V - 240 V ~ 50 / 60 Hz)
* Stan ar Voltage of each pro uct is marke by mo els
(4) Specification an performance of each parts are followe each rawing an specification by part number in accor ance with
BOM.
(5) The receiver must be operate for about 5 minutes prior to the a justment.
3. Test Method
(1) Performance : LGE TV test metho followe .
(2) Deman e other specification
Safety : UL, CSA, IEC specification, CE
EMC : FCC, ICES, IEC specification, CE
Mo el Name
50PZ750-UG
Remark
Safety : UL1492, CSA C22.2.No.1
EMC : FCC Class B, IC Class B
Market
NORTH AMERICA
Mo el Name
50PZ750-UG
Bran
LG
Market
NORTH AMERICA
CANADA / MEXICO / PANAMA / COLOMBIA

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Only or training and service purposes
4. Ge eral Specificatio
No Item Speci ication Remark
1. Receiving System 1) ATSC / NTSC-M
2. Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02~69
4) CATV : 01~135
5) CADTV : 01~135
3. Input Voltage 1) AC 100 V - 240 V ~ 50 / 60 Hz N.America Mark : 110V, 60Hz
4. Market NORTH AMERICA, KOREA
5. Screen Size 127 cm (50 inch) Wide(1920 ×1080) 50PZ950-UA, 50PZ950-UF
152 cm (60 inch) Wide(1920 ×1080) 60PZ950-UA, 60PZ950-UF
6. Aspect Ratio 16:9
7. Tuning System FS
8. PDP Module PDP50R3#### (1920 ×1080) 50PZ950-UA, 50PZ950-UF
PDP60R3#### (1920 ×1080) 60PZ950-UA, 60PZ950-UF
9. Operating Environment 1) Temp : 0 deg ~ 40 deg
2) Humidity : ~ 80 %
10. Storage Environment 1) Temp : -20 deg ~ 60 deg
2) Humidity : ~ 85 %

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Only or training and service purposes
ADJUSTMENT INSTRUCTION
1. Applicatio Ra ge
This spec. sheet applies to PU12A Chassis applied PDP TV
all models manu actured in TV actory.
2. Specificatio
(1) Because this is not a hot chassis, it is not necessary to use
an isolation trans ormer. However, the use o isolation
trans ormer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be per ormed in the circumstance o
25 cC ± 5 cC o temperature and 65 % ± 10 % o relative
humidity i there is no speci ic designation.
(4) The input voltage o the receiver must keep 100 V - 240 V,
50 / 60 Hz.
(5) The receiver must be operated or about 5 minutes prior to
the adjustment when module is in the circumstance o over
15 cC
- In case o keeping module is in the circumstance o 0 cC,
it should be placed in the circumstance o above 15 cC or
2 hours
- In case o keeping module is in the circumstance o below
-20 cC, it should be placed in the circumstance o above
15 cC or 3 hours.
Caution) When still image is displayed or a period o 20 minutes
or longer (especially where W/B scale is strong. Digital
pattern 13ch and/or Cross hatch pattern 09ch), there
can some a terimage in the black level area.
3. Adjustme t items
3-1. Board-level adjustme t
- Mac address and Id ile(ESN) Download
- Adjust 480i Comp1 adj.
- Adjust 1080p Comp1 adj.
- Adjust 1920*1080 RGB adj.
- EDID/DDC download
Above adjustment items can be also per ormed in Final
Assembly i needed. Both Board-level and Final assembly
adjustment items can be check using In-Start Menu 1.
Adjust Check.
3-2. Fi al assembly adjustme t
- White Balance adjustment
- RS-232C unctionality check
- Factory Option setting per destination
- Ship-out mode setting (In-Stop)
3-3. Etc.
- Ship-out mode
- Service Option De ault
- USB Download(S/W Update, Option)
4. MAC Address a d ESN Key Write
4-1. Equipme t & Co ditio
- Play ile: Serial.exe
- MAC Address edit
- Input Start / End MAC address
4-2. Dow load method
(1) Communication Prot connection
Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
(2) MAC Address Download
- Com 1,2,3,4 and 115200(Baudrate)
- Port connection button click(1)
- Load button click(2) or MAC Address write.
- Start MAC Address write button(3)
- Check the OK Or NG
(3) Input the ESN Key
(Except Mexico/Canada Models)
- download Model sending Key ile
- input by 1 by SET so as not to be duplicated

5. LAN PORT + ESN INSPECTION
5-1. Equipme t & Co ditio
- Each other connection to LAN Port o IP Hub and Jig
5-2. MAC Address & ESN Key & widevi e
Key co firmatio
MAC Address & ESN Key & widevine Key con irmation
MAC Address : All Models
widevine Key : All Models
ESN Key D/L : Except Mexico/Canada Models
- Push “IN-START” Key in service remote controller.
5-3. LAN PORT INSPECTION(PING TEST)
- LAN Port connection with PCB
- Network setting at MENU Mode o TV
- setting automatic IP
- Setting state con irmation
-> I automatic setting is inished, you con irm IP and MAC
Address.
- remove LAN CABLE
6. ADC adjustme t
6-1. Overview
ADC adjustment is needed to ind the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation.
6-2. Equipme t & Co ditio
(1) Jig (RS-232C protocol)
(2). Internal pattern is used. No external signal is needed.
6-3. Adjustme t
(1) Adj. protocol
(2) Check adjust device
Pattern Generator : (MSPG-925FA)
Adjust 480i Comp1
(MSPG-925FA:model :209 , pattern :65)
Adjust 1080p Comp1
(MSPG-925FA:model :225 , pattern :65)
Adjust RGB (MSPG-925FA:model :225 , pattern :65)
The PU02A have not ECHO.
7. EDID(The Exte ded Display
Ide tificatio Data) / DDC(Display
Data Cha el) dow load
7-1. Overview
It is a VESA regulation. A PC or a MNT will display an optimal
resolution through in ormation sharing without any necessity
o user input. It is a realization o °∞Plug and Play°±.
7-2. Equipme t
- Adj. R/C
- Since embedded EDID data is used, EDID download jig,
HDMI cable and D-sub cable are not need.
7-3. Dow load method
(1) Press Adj. key On the Adj. R/C, press Adj. key then select
EDID D/L. By pressing Enter key, EDID download will
begin.
(2) I Download is success ul, OK is displayed.
(3) I Download is a ailure, NG is displayed.
(4) Re-try download
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Only or training and service purposes

7-4. EDID DATA(PCM)
- Re erence: Download is only possible in POWER ON
MODE.
- HDMI
EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type : EDID 1.4
EDID Block 1, Bytes 128-255 [80H-FFH]
Block Type: CEA EDID Timing Extension Version 3
RGB [C/S: 1C]
EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type: EDID 1.3
7-5. EDID DATA(AC-3)
- Re erence: Download is only possible in POWER ON
MODE.
- HDMI
EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type : EDID 1.4
EDID Block 1, Bytes 128-255 [80H-FFH]
Block Type: CEA EDID Timing Extension Version 3
RGB [C/S: 1C]
EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type: EDID 1.3
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Only or training and service purposes
Vender ID C/S1 C/S2
HDMI1 10 9C D2
HDMI2 20 9C C2
HDMI3 30 9C B2
HDMI4 40 9C A2
Vender ID C/S1 C/S2
HDMI1 10 9C 60
HDMI2 20 9C 50
HDMI3 30 9C 40
HDMI4 40 9C 30

8. White Bala ce adj.
8-1. Overview
(1) W/B adj.: Objective & How-it-works
1) Objective: To reduce each Panel’s W/B deviation
2) How-it-works: When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic
Range. In order to prevent saturation o
Full Dynamic range and data, one o
R/G/B is ixed at 192, and the other two is
lowered to ind the desired value.
8-2. Equipme t
(1) Color Analyzer : CA-210 (NCG: CH 9 / WCG: CH12 /PDP
Module:CH10)
(2) Adj. Computer
(During auto adj., RS-232C protocol is needed)
(3) Adj. R/C
(4) Video Signal Generator MSPG-925F 720p/216Gray
(Model:217, Pattern:78)
-> Only when internal pattern is not available
- Color Analyzer Matrix should be calibrated using CS-1000
8-3. Equipme t co ectio map
8-4. Adj. Comma d (Protocol)
OProtocol
<Command Format>
- LEN: Number o Data Byte to be send
- CMD: Command
- VAL: FOS Data
- CS: Checksum o sent Data
- A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
ORS-232C Command used during auto-adj.
Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 -> Adj. data
jb 00 c0
...
...
wb 00 1 -> Gain adj. complete
*(wb 00 20(Start), wb 00 2 (End)) -> O -set adj.
wb 00 -> End white balance auto-adj.
8-5. Auto Adj. method
(1) Set TV in adj. mode using POWER On Key
(2) Zero calibrate probe then place it on the center o the
Display
(3) Connect Cable(RS-232C)
(4) Select mode in adj. Program and begin adj.
(5) When adj. is complete (OK Sign), check adj. status per
mode
(Warm, Medium, Cool)
(6) Remove probe and RS-232C cable to complete adj.
- Adj. must begin w/ command “wb 00 00”, and end “wb 00
” and adj. o set i needed.
- O set adjust limit value.
O set Min = 34 (Decimal)
O set Max = 94 (Decimal)
8-6. Ma ual adj. method
Dynamic contrast : o
Dynamic color : o
OPC : O
Energy saving mode : O
(1) Set TV Picture Mode to Standard and in Advanced
Control, set Dynamic Contrast and Color ‘ O ’ .
(2) Set TV in adj. mode using POWER On Key
(3) Press ADJ key -> EZ adjust using adj. R/C
(4) Using CH + / - KEY, select 10.TEST PATTERN then press
Enter to place in HEAT RUN mode and wait or 30
minutes.
(4) Zero calibrate the probe o Color Analyzer, then place it on
the center o LCD module within 10 cm o the sur ace.
(5) Press ADJ key -> 7. White-Balance then press the cursor
to the right (KEY G)
(When Gis pressed Full White internal pattern will be
displayed)
(6) One o R Gain / G Gain / B Gain should be ixed at 192,
and the rest will be lowered to meet the desired value.
(7) Adj. is per ormed in COOL, MEDIUM, WARM 3 modes o
color temperature
(8) O set Adjust in MEDIUM, WARM 2 modes o color
temperature ( Only THX Model )
V I internal pattern is not available, use HDMI input. In EZ
Adj. menu 7.White Balance, you can select one o 3
options: None, Inner, HDMI. De ault is inner. By selecting
HDMI, you can adjust using HDMI signal.
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Only or training and service purposes

VAdj. condition and cautionary items
(1) Lighting condition in surrounding area
Surrounding lighting should be lower than 10 lux. Try
to isolate adj. area into dark surrounding.
(2) Probe location
- PDP : Color Analyzer (CA-100, CA-100+, CA210)
probe should be irmly attached to the Module
- LCD : Color Analyzer (CA-210) probe should be within
10cm and perpendicular o the module sur ace
(80°~ 100°)
- In case o LCD, B/L on should be checked using no
signal or Full white Pattern
8-7. Refere ce (White Bala ce adj.
coordi ate a d color temperature)
O Standard color coordinate and temperature using CS-1000
O Luminance: Full white 216 Gray
O Standard color coordinate and temperature using CA-210(CH
10)
- Gain color coordinate
O Pattern : Full white 216 Gray
- O set color coordinate : Only THX model
O Pattern : Full white 50 Gray
O Luminance : 5 ± 4 cd
9. Checki g the EYE-Q Operatio .
(1) Press the EYE Key on the adjustment remote controller.
(2) Check the Sensor DATA ( It must be under 10) and keep
the data longer than 1.5s
(3) Check ‘OK’
(Sensor DATA 0 ~ 4095, Power Saving Mode 0 ~ 12)
* IF you press IN-STAP Button, change Green Eye-check OSD.
10. Pi g TEST
* This test is to check Network operation.
10-1. Equipme t Setti g
(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up or an inspection to Test
*IP Number : 12.12.2.2
11. LAN PORT i spectio
(PING TEST)
* In this case Network setting is on Manual Setting.
(1) Play the LAN Port Test Program.
(2) connect each other LAN Port Jack.
(3) Play Test (F9) button and con irm OK Message.
(4) remove LAN CABLE
12. Check Wireless fu ctio .
(1) Connect set and Dongle o Wireless to Cable o HDMI &
TTA 20Pin
(2) At OSD o SET, check the message like Fig 3.
(3) Detach Cable o Wireless Dongle
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13. Magic Motio Remote Co troller
test
Required Equipment
- RF Remote Controller or test, IR-KEY-Code Remote
Controller or test
* You must con irm the battery power o Remote Controller
be ore test
(Recommend that change the battery per every lot)
(1) I you select the ‘start key(Mute)’ on the controller, you can
pairing with the TV SET.
(2) You can check the cursor on the TV Screen, when select
the ‘OK Key’ on the controller
(3) You must remove the pairing with the TV Set by select
‘Vol+(STOP) Key’ on the controller
14. 3D Fu ctio Test
(Pattern Generator MSPG-3233, HDMI mode NO. 371 ,
pattern No. 81)
(1) Please input 3D test pattern like below
(2) Enter 3D mode , then select side by side
(I you don’t wear a 3D Glasses, you will see the picture
like below)
(3) Put on the 3D Glasses, And block the right side o Glasses
(LEFT:OPEN[TEST], RIGHT:CLOSED)
And check the middle sides o picture , RED -> normal ,
others -> abnormal
(4) Put on the 3D Glasses, And block the right side o Glasses
(LEFT:CLOSED, RIGHT:OPEN[TEST])
And check the middle sides o picture , BLUE -> normal ,
others -> abnormal
15. Check RF Emitter.
Required Equipment
- Pattern Generator : 3D-GT002, MSHG-600,
MSPG-6100 [SUPPORT HDMI1.4])
MODE : HDMI mode NO. 872
Pattern No.83
(1) On 3D Mode, Check the picture like below.
(2) I RF Emitter is correctly working, you can see that the
lamp o RF tester turns on.
16. Optio selectio per cou try
16-1. Overview
O Option selection is only done or models in Non-USA North
America due to rating
O Applied model: PU02A Chassis applied USA Model(Not
Canada, Mexico)
16-2. Method
(1) Press ADJ key on the Adj. R/C, then select Country Group
Menu
(2) Depending on destination, select KR or US, then on the
lower option, select US, CA, MX. Selection is done using
+, - KEY
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Only or training and service purposes

16-3. Ship-out (Default) mode check
(Instop)
OAfter final inspection, press In-Stop key of the Adj. R/C and
check that the unit goes to Stand-by mode.
16-4. POW R Supply Unit PCB Ass'y Va/Vs
Voltage adjustment.
Caution ]
Both Vs and Va voltage adjustment are necessary.
(1) Model name: 50/60PK750-UA, 50/60PK950-UA
(2) Va/Vs Adjustment Procedure
1) Connect positive(+) terminal of DMM to Vs/Va pin,
connect negative(-) terminal to GND.
2) Turning ‘ Vs/Va ’ and adjust Vs/Va voltages to a value
which is written on a right/top label of a module.
( deviation ; ± 0.5V)
Caution ]
Each Power Supply Unit PCB assembly must be checked by
check JIG set.
(Because power PCB Ass’y damages to PDP Module, especially
be careful)
Caution]
Set up "RF mode(noise)" before a voltage adjustment.
17. USB Download (S/W Update,
*.epk File Download)
(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick
- If your downloaded program version in USB Stick is Low,
it didn’t work.
But your downloaded version is High, USB data is
automatically detecting
(3) Show the message “Copying files from memory”
(4) Updating is staring.
(5) Updating Completed, The TV will restart automatically.
(6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
have a DTV/ATV test on production line.
* After downloading, have to adjust TOOL OPTION again.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)
(4) Completed selecting Tool option.
* After downloading, have to adjust TOOL OPTION again.
1. Push "IN-START" key in service remote controller.
2. Select "Tool Option 1" and Push “OK” button.
3. Punch in the number. (Each model has their number.)
4. Completed selecting Tool option.
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Only for training and service purposes
Model Tool Tool Tool Tool Tool Tool
Name Value 1 Value 2 Value 3 Value 4 Value 5 Value 6
50PZ950-UA 32777 65 7519 7560 14929 857
60PZ950-UA 32781 65 7519 7560 14921 857
50PZ570-UG 32793 65 7519 7560 14921 857
60PZ570-UG 32797 65 7519 7560 14921 857

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Only or training and service purposes
BLOCK DIAGRAM

- 14 - LGE Internal Use Only
EXPLODED VIEW
303
209
208
400
580
201
601
200
300
301
207
304
202
302
203
240
604
520
602
501
590
204
205
206
120
910
570
540 560
900
305
Many electrical and mec anical parts in t is c assis ave special safety-related c aracteristics. T ese
parts are identified by in t e Sc ematic Diagram and EXPLODED VIEW.
It is essential t at t ese special safety parts s ould be replaced wit t e same components as
recommended in t is manual to prevent X-RADIATION, S ock, Fire, or ot er Hazards.
Do not modify t e original design wit out permission of manufacturer.
IMPORTANT SAFETY NOTICE
LV1
A12
A2
A23
A4
A24 A10 A9

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
NAND_DATA[7]
NAND_DATA[6]
NAND_DATA[5]
NAND_DATA[4]
NAND_DATA[3]
NAND_DATA[2]
NAND_DATA[1]
NAND_DATA[0]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[7]
CI_ADDR[2]
CI_ADDR[12]
CI_ADDR[6]
CI_ADDR[11]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[9]
CI_ADDR[14]
NAND_DATA[7]
NAND_DATA[4]
NAND_DATA[6]
NAND_DATA[2]
NAND_DATA[0]
NAND_DATA[5]
NAND_DATA[1]
NAND_DATA[3]
CI_ADDR[5]
CI_ADDR[10]
SCL2_3.3V
SDA2_3.3V
C106
4.7uF
P101
TJC2508-4A
OPT
1VCC
2SCL
3SDA
4GND
R110
1.5K
+3.3V_Normal
R109
1.5K
+3.3V_Normal
SOC_RESET
R124
1K
OPT
R125
1K
+3.3V_Normal
C112 0.1uF
NAND_ALE
NAND_CEb
FLASH_WP
NAND_WEb
NAND_REb
NAND_CLE
SCL0_3.3V
SDA0_3.3V
+3.3V_Normal
R113
10K
R114
10K
OPT
R118
10K
R117
10K
OPT
R123
10K
OPT
R122
10K
R128
10K
R127
10K
OPT CI_ADDR[4]
NAND_DATA[7]
NAND_DATA[2]
NAND_DATA[1]
R115
10K
R112
10K
+3.3V_Normal
R119
10K
OPT
R111
10K
OPT
R116
10K
OPT
R120
10K
CI_ADDR[3]
CI_ADDR[2]
NAND_ALE
R146 10K
NAND_DATA[0]
CI_ADDR[8]
NAND_CLE
NAND_DATA[3]
NAND_DATA[6]
NAND_DATA[5]
NAND_DATA[4]
+3.3V_Normal
R141 4.7K
R173
4.7K
R169
0
+3.3V_Normal
IC103
M24M01-HRMN6TP
NVR_1M
3
E2
2
E1
4
VSS
1
NC
5SDA
6SCL
7WP
8VCC
C116
0.1uF
+3.3V_Normal
SDA3_3.3V
SCL3_3.3V
HDMI_RX1-
HDMI_RX0+
HDMI_RX2-
HDMI_CLK+
HDMI_RX2+
R106
3K
HDMI_RX1+
HDMI_CLK-
HDMI_RX0-
R189
1M
OPT
54MHz_XTAL_P
54MHz_XTAL_N
54MHz_XTAL_P
54MHz_XTAL_N
R108 12K
BCM_RX
BCM_TX CI_ADDR[2-14]
R132 4.7K
R144 22
OPT
R145 22
OPT
R142 22
OPT
R143 22
OPT
R101
4.7K
CI_ADDR[9]
CI_ADDR[13]
CI_ADDR[11]
CI_ADDR[12]
R154
10K
OPT
R160
10K
OPT
R167
10K
OPT
R170
10K R175 10K
OPT
R177
10K R179 10K
OPT
R181
10K
OPT
R183
10K R187 10K
OPT
R192
10K
OPT
R155
10K R161 10K R168 10K R171 10K
OPT
R176
10K R178 10K
OPT
R180
10K R182 10K R184 10K
OPT
R188
10K R193 10K
NAND_RBb
C102
4700pF
R107 2.7K
C104 10uF
10V
NAND_ALE
+3.3V_Normal
C101
0.1uF
NAND_DATA[0-7]
NAND_CLE
NAND_WEb
+3.3V_Normal
NAND_CEb
NAND_REb
C103
0.1uF
R103 4.7K
OPT
FLASH_WP
+3.3V_Normal
R174
4.7K
OPT
R172
4.7K
OPT
NAND_RBb
+3.3V_Normal
R140
560
1%
NAND_DATA[0-7]
R135 33
R136 33
R191 33
R190 33
+3.3V_Normal R134 33
OPT
R133 33
OPT
5V_HDMI_4
5V_HDMI_2
5V_HDMI_3
5V_HDMI_1
R130
2K
OPT
TXB2P
TXA0P
TXA1P
TXB0P
TXA2N
TXA0N
TXBCLKP
TXB1N
TXACLKP
TXB4P
TXB1P
TXACLKN
TXB0N
TXA4P
TXB4N
TXB2N
TXBCLKN
TXB3P
TXA3P
TXA2P
TXB3N
TXA1N
TXA4N
TXA3N C115
8pF
OPT
C117
8pF
OPT
C107
33pF
50V
OPT
C108
33pF
50V
OPT
C109
33pF
50V
OPT C110
33pF
50V
OPT
C111 0.01uF
+3.3V_Normal
JTAG_RESET
+3.3V_Normal
R166
1K
OPT
R163
1K
OPT
P102
12505WS-10A00
OPT
1
/TRST
2
TDI
3
TDO
4
TMS
5
TCK
6
/RST
7
DINT
8
VIO
9
GND
10
GND
11
GND
R153
1K
OPT
R147
1K
OPT
R162
1K
OPT
R156
1K
OPT
R159
1K
OPT
R150
1K
OPT
JTAG_RESET R139 0
OPT
R164
10K
OPT
R165
10K
CI_ADDR[6]
R157
10K
OPT
R158
10K
CI_ADDR[7]
CI_ADDR[5]
CI_ADDR[10]
CI_ADDR[14]
R100 22
R102 22
R148 22
R195 0
+3.3V_Normal
R197
4.7K
R149
0
R151
10K
BSS83
Q102
S B D
G
C118
0.1uF
16V
RGB_DDC_SDA
+3.3V_Normal
RGB_DDC_SCL
C119
0.1uF
16V
BSS83
Q101
S B D
G
+3.3V_Normal
R198
10K
R1902
0
OPT
R1901
0
OPT
R1900 0
OPT
NAND_CEb2
NAND_CEb2
R138 0
R137 0
HDMI_ARC
R105
4.7K
R104
4.7K
+5V_Normal
R121
2.2K R126 2.2K R131 2K
R129
2K
IC102
TC58DVG3S0ETA00
TOSHIBA_8GBIT
26 NC_17
27 NC_18
28 NC_19
29 I/O1
30 I/O2
31 I/O3
32 I/O4
33 NC_20
34 NC_21
35 NC_22
36 VSS_2
37 VCC_2
38 NC_23
39 PSL
40 NC_24
41 I/O5
42 I/O6
43 I/O7
44 I/O8
45 NC_25
46 NC_26
47 NC_27
48 NC_28
17
ALE
3
NC_3
6
NC_6
16
CLE
15
NC_10
14
NC_9
13
VSS_1
12
VCC_1
11
NC_8
10
NC_7
9
CE
8
RE
7
RY/BY
4
NC_4
5
NC_5
25 NC_16 24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
WE
MED62210801
OPT
M100
X101
54MHz
SUNNY_54MHz
4
GND_2 1X-TAL_1
2GND_1 3
X-TAL_2
X101-*1
54MHz
KDS_54MHz
4GND_2 1
X-TAL_1
2
GND_1 3X-TAL_2
C113
12pF
C114
12pF
R186 0
R185 0
LGE35230
IC101
HDMI0_CLKN
B5
HDMI0_CLKP
C5
HDMI0_D0N
A4
HDMI0_D0P
B4
HDMI0_D1N
A3
HDMI0_D1P
B3
HDMI0_D2N
A2
HDMI0_D2P
B2
CEC
W2
DDC0_SCL
V4
DDC0_SDA
W4
HDMI0_HTPLG_IN
V3
HDMI0_HTPLG_OUT
V2
HDMI0_ARC
D13
HDMI0_RESREF
E6
TXOUT0_L0N AE27
TXOUT0_L0P AE28
TXOUT0_L1N AF27
TXOUT0_L1P AF28
TXOUT0_L2N AG27
TXOUT0_L2P AG28
TXCLK_LN AE26
TXCLK_LP AF26
TXOUT0_L3N AH27
TXOUT0_L3P AG26
TXOUT0_L4N AF25
TXOUT0_L4P AE25
TXOUT0_U0N AH26
TXOUT0_U0P AG25
TXOUT0_U1N AE24
TXOUT0_U1P AD24
TXOUT0_U2N AH25
TXOUT0_U2P AF24
TXCLK_UN AE23
TXCLK_UP AD23
TXOUT0_U3N AG24
TXOUT0_U3P AF23
TXOUT0_U4N AC22
TXOUT0_U4P AD22
TXOUT1_L0N AG23
TXOUT1_L0P AH23
TXOUT1_L1N AE22
TXOUT1_L1P AE21
TXOUT1_L2N AF22
TXOUT1_L2P AH22
TXCLK1_LN AG22
TXCLK1_LP AF21
TXOUT1_L3N AG21
TXOUT1_L3P AF20
TXOUT1_L4N AD21
TXOUT1_L4P AC21
TXOUT1_U0N AG20
TXOUT1_U0P AH20
TXOUT1_U1N AD19
TXOUT1_U1P AE19
TXOUT1_U2N AF19
TXOUT1_U2P AH19
TXCLK1_UN AE18
TXCLK1_UP AD18
TXOUT1_U3N AG19
TXOUT1_U3P AF18
TXOUT1_U4N AG18
TXOUT1_U4P AF17
LT0VCAL_MONITOR AC18
GPIO_BL_ON AH16
BL_PWM/GPIO AG16
LGE35230
IC101
TVM_XTALIN
AG6
TVM_XTALOUT
AF6
IRRXDA
V5
FP_IN0
AB4
FP_IN1
Y4
SPARE_ADC1
AA4
SPARE_ADC2
Y5
FS_IN1
AB2
FS_IN2
AB5
VGA_SDA
U3
VGA_SCL
U2
RDA
Y2
TDA
Y1
BSCDATAA
AA3
BSCCLKA
AA2
RDB/GPIO
H3
TDB/GPIO
H2
BSC_S_SCL
H4
BSC_S_SDA
H5
NMIB
F25
POWER_CTRL
W5
AON_HSYNC
U5
AON_VSYNC
U4
AON_GPIO_36
W3
AON_GPIO_37
W1
AON_RESETOUTB
AB6
TVM_BYPASS
Y6
RESETB
Y3
RESETOUTB
G24
TMODE
J6
TESTEN
W6
VDAC_VREG
F7
VDAC_RBIAS
E7
FAD_7 AB1
FAD_6 AB3
FAD_5 AC1
FAD_4 AC2
FAD_3 AC3
FAD_2 AD2
FAD_1 AD3
FAD_0 AE2
FALE AG1
FCEB_0 AF1
FCEB_1 AC5
FCEB_2 AE6
FCEB_3 AG5
NFWPB AF3
FWE AG2
FRD AE3
FRDYB AA5
FA_0 AF2
FA_1 AE1
FA_2 AC4
FA_3 AD5
FA_4 AD4
FA_5 AE4
FA_6 AE5
FA_7 AD6
FA_8 AH3
FA_9 AF4
FA_10 AH4
FA_11 AG4
FA_12 AF5
FA_13 AG3
FA_14 AH2
FA_15 AH5
TRSTB AD15
TDI/GPIO AF14
TDO AH14
TMS/GPIO AD14
TCK/GPIO AG14
DINT/GPIO AC16
AVS_VFB AH7
AVS_VSENSE AG7
AVS_RESETB AD7
AVS_NDRIVE_1 AF7
AVS_PDRIVE_1 AH8
VDAC_1 C6
VDAC_2 D7
R152
0
NVR_256K
IC103-*1
AT24C256C-SSHL-T
NVR_256K
3
A2
2
A1
4
GND
1
A0
5SDA
6SCL
7WP
8VCC
BBS CONNECT
0000: ST Micro M25P or compatible Serial Flash
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
1010: 8-bit 8Gbit, 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O)
0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices
0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
0111: 3B dual IO Serial Flash
1001: BB dual IO Serial Flash
1011: fast Serail Flash > 50Mhz
1100: OneNAND Flash (always 16-bit)
1110: Reserved
1101, 1111: Reserved
000 = ECC disabled
001 = ECC 1-bit repair
010 = ECC 4-bit BCH (O)
011 = ECC 8-bit BCH, 27 byte spare
100 = ECC 12-bit BCH, 27 byte spare
101 = ECC 8-bit BCH, 16 byte spare
110, 111 = Reservedd
Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)
NAND ECC (FA3, FA2, FALE)
CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
TVM Crystal oscillator bias/gain control
0000: 210uA
0001: 390uA
0010: 570uA
0011: 730uA
0100: 890uA (O)
0111: 1290uA
1000: 1416uA
1111: 2196uA
0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
CI_ADDR[8]:
0: RESETOUTb (in On/Off only) stay asserted until software releases them.
1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
at end of RESETb pulse (O)
NAND_DATA[3]:
0: MIPS will boot from external flash (O)
1: MIPS will boot from ROM
NAND_DATA[5]:
0: FLASH MODE (0)
1: BSC_SLAVE(BBS) MODE
Strap Setting
NAND_DATA[0]:
0: System is LITTLE endian (O)
1: System is BIG endian
CI_ADDR[7]:
0: Disable EDID automatic Downloading from Flash (O)
1: Enable EDID automatic Downloading from Flash
NAND_DATA[6] :
0: Disable OSC clock output on chip Pin (O)
1: Enable OSC clock output on chip pin.
CI_ADDR[6]:
0: Host MIPS run at 500 MHz (O)
1: Host MIPS run at 250 MHz
NAND_CLE:
0: Differential Oscillators TVM not bypassed (O)
1: Differential Oscillators TVM bypassed
NAND_DATA[4]:
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O)
A8’h
NVRAM
54MHz X-TAL
NAND FLASH MEMORY 8Gbit
Write Protection
- High : Normal Operation
- Low : Write Protection
Write Protection
- Low : Normal Operation
- High : Write Protection
BCM REFRENCE is 562ohm
31
1
MAIN & NAND FLASH
BCM35230
FOR HDMI STANDARD
APPLY ONLY WHEN CONNECT TO PULL-UP GPIO
**JTAG OPT
R139, R147, R150, R153, R156, R159,
R162, R163, R166, P102
Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
EPHY_RDP
EPHY_RDN
EPHY_TDN
EPHY_TDP
SCL1_3.3V
SDA1_3.3V
C242
0.1uF
+0.9V_CORE
+3.3V_Normal
+2.5V_BCM35230
C249
10uF C261
10uF
C253
10uF C271
0.01uF
C293
0.1uF
C262
10uF
C259
10uF
C275
0.1uF
R222 0 OPT
R219 0
+3.3V_Normal
C218
0.1uF
L201
BLM18PG121SN1D
R221 0 OPT
C217
0.1uF
R227 0
R216 0
C216 0.01uF
R213 2K
R212
1K
NON_CHB +3.3V_Normal
C229
0.1uF
+0.9V_CORE
C273
0.1uF
C278
0.1uF
+3.3V_Normal
L202
BLM18PG121SN1D L205 BLM18PG121SN1D
L203
BLM18PG121SN1D
L209
BLM18PG121SN1D
L216
BLM18PG121SN1D
L214
BLM18PG121SN1D
L212
BLM18PG121SN1D
L219
BLM18PG121SN1D
L206
BLM18PG121SN1D
L215
BLM18PG121SN1D
L204
BLM18PG121SN1D
L210
BLM18PG121SN1D L217 BLM18PG121SN1D
L218
BLM18PG121SN1D
L211
BLM18PG121SN1D
L207
BLM18PG121SN1D
REMOTE_OR_MODULE_RX
RF_SWITCH_CTL
RF_BOOSTER_CTL
+3.3V_Normal
+0.9V_CORE
+0.9V_CORE
DSUB_DET
COMP1_DET
AV2_CVBS_DET
SC_DET/COMP2_DET
R225 0 OPT
L213
BLM18PG121SN1D
L208
BLM18PG121SN1D
R211
6.04K
DC_MREMOTE
DD_MREMOTE
R230 22
+0.9V_CORE +0.9V_CORE
+0.9V_CORE+0.9V_CORE
+2.5V_BCM35230
+2.5V_BCM35230
AADC_AVDD25 ADAC_AVDD25
EPHY_VDD25 +2.5V_BCM35230
+2.5V_BCM35230 VAFE2_VDD25
+2.5V_BCM35230 VAFE3_VDD25 +2.5V_BCM35230 PLL_VAFE_AVDD25
HDMI_AVDD33USB_AVDD33
VDAC_AVDD33
HDMI_AVDD USB_AVDD VAFE2_DVDD
VAFE3_DVDDPLL_AUD_AVDD PLL_MAIN_AVDD
PLL_MIPS_AVDD
PLL_VAFE_AVDD
+0.9V_CORE
+0.9V_CORE
+0.9V_CORE
AADC_AVDD25
ADAC_AVDD25
EPHY_VDD25
HDMI_AVDD
HDMI_AVDD33
USB_AVDD
USB_AVDD33
VDAC_AVDD33
VAFE2_DVDD
VAFE2_VDD25
VAFE3_DVDD
VAFE3_VDD25
PLL_AUD_AVDD
PLL_MAIN_AVDD
PLL_MIPS_AVDD
PLL_VAFE_AVDD25
PLL_VAFE_AVDD
C201
100pF
OPT
R210
4.87K
1%
+1.5V_DDR
C227
33pF
50V
OPT
C231
33pF
50V
OPT
C276
0.01uF
C272
0.01uF
C274
22uF
C284
22uF C292
22uF
C250
4.7uF
C252
4.7uF
C254
4.7uF
C260
4.7uF
C263
4.7uF
C264
4.7uF
C265
4.7uF
C266
4.7uF C277
4.7uF
C279
4.7uF
C285
4.7uF
C286
4.7uF
C287
4.7uF
C291
4.7uF
C294
4.7uF
C295
4.7uF
C296
4.7uF
+2.5V_BCM35230
+3.3V_Normal+3.3V_Normal
+3.3V_Normal
+3.3V_Normal
CHBO_TS_VAL_ERR
CHBO_TS_CLK
CHBO_TS_SERIAL
CHBO_TS_SYNC
R223 0
R226 22
R218 22
CHB_RESET
RF_SWITCH_CTL_2
R215 22
EPHY_LINK
EPHY_ACTIVITY
IF_AGC_MAIN
IF_N_MAIN
IF_P_MAIN
+2.5V_BCM35230
R204 0
C269
0.1uF
C255
0.1uF
C270
0.1uF
C257
0.1uF
C267
0.1uF
C268
0.1uF
C258
0.1uF
C281
0.1uF
C299
0.1uF
C289
0.1uF
C298
0.1uF
C283
0.1uF
C288
0.1uF
C282
0.1uF
C297
0.1uF
C280
0.1uF
C290
0.1uF
TW9910_RESET
R231
100
1%
R232
100
1%
M_RFModule_RESET
R240 0
AMP_RESET_N
R249 0
R250 0L/R_INDICATOR
MODEL_OPT_1
USB_DP2
USB_DP1
USB_CTL1
USB_DM2
USB_DM1
USB_CTL2
/USB_OCD2
/USB_OCD1
R241 75
KOR
R248 75
KOR
R243 75
KOR
R242 75
KOR
C2000
100pF
50V
KOR
C2001
100pF
50V
KOR
3D_GPIO_0
3D_GPIO_1
3D_GPIO_2
R236 0
R237 0
C247
22uF
C215
0.01uF
C205
10uF
C234
0.1uF
C221
0.1uF
C248
10uF
C203
10uF C211 0.1uF
+1.5V_DDR
C222
0.01uF
C236
0.1uF C238 4.7uF
C209
4.7uF
C223
0.01uF
+0.9V_CORE
C232
4.7uF
+3.3V_Normal
C220
0.1uF
+0.9V_CORE
C213
0.1uF
C207
4.7uF
R206 0
R207 0DEMOD_RESET
FE_TS_SERIAL
FE_TS_CLK
FE_TS_SYN
FE_TS_VAL
R214 0
3V3
R208
3.3K
OPT
R209 0
R217 0
C256
0.1uF
16V
C251
0.1uF
16V
R200 0
OPT
R203 0
OPT
R201 0
OPT
R202 0
OPT
MODEL_OPT_3
C225
0.22uF
6.3V
C202
100pF
50V
OPT C206
100pF
50V
OPT
R233
1.2K R234 1.2K
NFM18PS105R0J
C233
6.3V
OUTIN
GND
NFM18PS105R0J
C204
6.3V
OUTIN
GND
NFM18PS105R0J
C244
6.3V
OUTIN
GND
R295
1K
OPT
R293
1K
OPT
R289
1K
DVR_READY
PDP_MODEL_OPT_0
R294
1K
R292
1K
NON_RF_Emitter
PDP_MODEL_OPT_2
R291
1K
NON_DVR_READY
R296
1K
PDP_MODEL_OPT_3
+3.3V_Normal
PDP_MODEL_OPT_1
R290
1K
RF_Emitter
R205 0
PDP_MODEL_OPT_1
R235 0PDP_MODEL_OPT_0
R287 0
R288 0
PDP_MODEL_OPT_3
PDP_MODEL_OPT_2 C212
390pF
50V
C210
390pF
50V
C208
390pF
50V C214
390pF
50V
C219
390pF
50V
OPT
C224
390pF
50V
OPT
C226
1uF
25V
OPT
C228
0.1uF
16V
OPT
L220
MLG1005S22NJT
TP200
MODEL_OPT_4
R244 1K
/3D_ASIC_RESET
R245 1K OPT
MODEL_OPT_7
MODEL_OPT_2
R247 1K NVR_256K
R259 0
R246 1K NVR_1M
MODEL_OPT_3
R252 1K OPT
R255 1K OPT
R256 1K
MODEL_OPT_0
R251 1K R228 1K OPT
MODEL_OPT_4
REMOTE_SW_CTRL
R253 1K OPT
MODEL_OPT_5
MODEL_OPT_1
R254 1K R239 1K
R257 1K OPT
R229 1K
+3.3V_Normal
R258 1K
R260 0
MODEL_OPT_3
R238 1K OPT
MODEL_OPT_6
MODEL_OPT_1
MODEL_OPT_0
MODEL_OPT_2
R261 22
MODEL_OPT_5
MODEL_OPT_6
MODEL_OPT_7
R220 22
R262 22
R263 22
R224 22
LGE35230
IC101
EPHY_VREF
F26
EPHY_RDAC
D26
EPHY_TDP
F27
EPHY_TDN
F28
EPHY_RDP
E27
EPHY_RDN
E26
USB_MONCDR
F5
USB_RREF
E5
USB_PORT1DN
C2
USB_PORT1DP
D1
USB_PWRFLT_1/GPIO
E1
USB_PWRON_1/GPIO
D2
USB_PORT2DN
B1
USB_PORT2DP
C1
USB_PWRFLT_2/GPIO
C3
USB_PWRON_2/GPIO
C4
TCLKA/GPIO
M4
TDATA_0/GPIO
L5
TDATA_1/GPIO
M5
TDATA_2/GPIO
L6
TDATA_3/GPIO
N3
TDATA_4/GPIO
N1
TDATA_5/GPIO
N2
TDATA_6/GPIO
M3
TDATA_7/GPIO
M2
TSTRTA/GPIO
L4
TVLDA/GPIO
N4
TCLKD/GPIO
K6
TDATD_0/GPIO
J4
TDATD_1/GPIO
K5
TDATD_2/GPIO
J2
TDATD_3/GPIO
J3
TDATD_4/GPIO
K2
TDATD_5/GPIO
K1
TDATD_6/GPIO
K3
TDATD_7/GPIO
L1
TSTRTD/GPIO
L3
TVLDD/GPIO
L2
MPEG_CLK/GPIO
P4
MPEG_D_0/GPIO
T2
MPEG_D_1/GPIO
R3
MPEG_D_2/GPIO
R2
MPEG_D_3/GPIO
P3
MPEG_D_4/GPIO
P2
MPEG_D_5/GPIO
P1
MPEG_D_6/GPIO
R6
MPEG_D_7/GPIO
N5
MPEG_SYNC/GPIO
T4
MPEG_DATA_EN/GPIO
P5
MCIF_RESET/GPIO
R4
MCIF_SCLK/GPIO
U1
MCIF_SCTL/GPIO
T3
MCIF_SDI/GPIO
T1
MCIF_SDO/GPIO
T5
VI_IFP0 C17
VI_IFM0 B17
VDDR_AGC D15
AGC_SDM_2 B16
AGC_SDM_1 A16
GPIO_0 A15
GPIO_1 C16
GPIO_2 G28
GPIO_3 G26
PCI_VIO_0 W14
PCI_VIO_1 W15
PCI_VIO_2 W13
GPIO_4 J5
GPIO_5 R5
GPIO_6 V6
GPIO_7 H6
GPIO_70 AE15
GPIO_71 AF15
GPIO_72 AG15
GPIO_73 AF16
GPIO_74 AD16
GPIO_75 AE16
GPIO_76 AG17
GPIO_77 AH17
GPIO_78 AE17
GPIO_79 AD17
PCI_AD05 AB13
PCI_AD06 AC15
PCI_AD07 AB12
PCI_AD08 AB11
PCI_AD09/GPIO AE14
PCI_AD10/GPIO AG13
PCI_AD11/GPIO AH13
PCI_AD12/GPIO AF13
PCI_AD13/GPIO AE13
PCI_AD14/GPIO AD12
PCI_AD15/GPIO AF12
PCI_AD16/GPIO AG10
PCI_AD17/GPIO AF10
PCI_AD18/GPIO AE10
PCI_AD19/GPIO AD10
PCI_AD20/GPIO AE9
PCI_AD21/GPIO AE8
PCI_AD22 AC10
PCI_AD23 AC11
PCI_AD24 AC8
PCI_AD25 AB8
PCI_CBE00 AC14
PCI_CBE01/GPIO AG12
PCI_CBE02/GPIO AH10
PCI_CBE03 AB7
PCI_DEVSELB/GPIO AG11
PCI_FRAMEB/GPIO AD11
PCI_IRDYB/GPIO AE11
PCI_PAR/GPIO AD13
PCI_PERRB/GPIO AE12
PCI_REQ1B AC12
PCI_SERRB/GPIO AC13
PCI_STOPB/GPIO AH11
PCI_TRDYB/GPIO AF11
LGE35230
IC101
VDDC_1
V12
VDDC_2
V7
VDDC_3
M10
VDDC_4
N10
VDDC_5
P10
VDDC_6
R10
VDDC_7
T10
VDDC_8
U10
VDDC_9
V10
VDDC_10
W10
VDDC_11
V13
VDDC_12
L11
VDDC_13
M11
VDDC_14
N11
VDDC_15
P11
VDDC_16
R11
VDDC_17
T11
VDDC_18
U11
VDDC_19
V11
VDDC_20
W11
VDDC_21
V14
VDDC_22
L18
VDDC_23
M18
VDDC_24
N18
VDDC_25
P18
VDDC_26
R18
VDDC_27
T18
VDDC_28
U18
VDDC_29
V18
VDDC_30
W18
VDDC_31
V15
VDDC_32
L19
VDDC_33
M19
VDDC_34
N19
VDDC_35
P19
VDDC_36
R19
VDDC_37
T19
VDDC_38
U19
VDDC_39
V19
VDDC_40
W19
VDDC_41
V16
VDDC_42
V17
POR_VDD
L10
VDDR1_1
L22
VDDR1_2
AA28
VDDR1_3
V28
VDDR1_4
R28
VDDR1_5
M28
VDDR1_6
J28
VDDR1_7
K23
VDDR1_8
M22
VDDR1_9
T22
VDDR1_10
T23
VDDR1_11
U22
VDDR1_12
Y22
DDR_LDO_VDDO
R22
VDDR3_1
G15
VDDR3_2
H22
VDDR3_3
G23
VDDR3_4
AB9
VDDR3_5
K7
VDDR3_6
AB15
VDDR3_7
L7
VDDR3_8
AB14
VDDR3_9
M7
VDDR3_10
N6
VDDR3_11
P6
AON_VDDC_1
AA6
AON_VDDC_2
AA7
AON_POR_VDD
Y7
AON_VDDR3
U7
AON_VDDR10_1
T7
AON_VDDR10_2
T6
VSS_1 K10
VSS_2 K11
VSS_3 K12
VSS_4 L12
VSS_5 M12
VSS_6 N12
VSS_7 P12
VSS_8 R12
VSS_9 T12
VSS_10 U12
VSS_11 W12
VSS_12 K13
VSS_13 L13
VSS_14 M13
VSS_15 N13
VSS_16 P13
VSS_17 R13
VSS_18 T13
VSS_19 U13
VSS_20 W16
VSS_21 K14
VSS_22 L14
VSS_23 M14
VSS_24 N14
VSS_25 P14
VSS_26 R14
VSS_27 T14
VSS_28 U14
VSS_29 K15
VSS_30 L15
VSS_31 M15
VSS_32 N15
VSS_33 P15
VSS_34 R15
VSS_35 T15
VSS_36 U15
VSS_37 K16
VSS_38 L16
VSS_39 M16
VSS_40 N16
VSS_41 P16
VSS_42 R16
VSS_43 T16
VSS_44 U16
VSS_45 K17
VSS_46 L17
VSS_47 M17
VSS_48 N17
VSS_49 P17
VSS_50 R17
VSS_51 T17
VSS_52 U17
VSS_53 W17
VSS_54 K18
VSS_55 K19
VSS_56 H7
VSS_57 G14
VSS_58 AB16
VSS_59 R7
VSS_60 M6
VSS_61 AB23
VSS_62 P7
VSS_63 W7
VSS_64 J7
VSS_65 N7
VSS_66 AB10
VSS_67 AC23
VSS_68 AC6
VSS_69 G19
VSS_70 AA22
VSS_71 J23
VSS_72 J22
VSS_73 K22
VSS_74 J25
VSS_75 N22
VSS_76 N23
VSS_77 M25
VSS_78 P22
VSS_79 R25
VSS_80 V22
VSS_81 W22
VSS_82 W23
VSS_83 V25
VSS_84 AA25
LGE35230
IC101
AADC_AVDD25
F19
ADACA_AVDD25
D25
ADACC_AVDD25
D24
ADACD_AVDD25
E24
EPHY_BVDD25
F24
EPHY_AVDD25
E25
POR_VDD25
F8
HDMI0_AVDD
D5
HDMI0_AVDD33
D4
LT0VDD25_1
AE20
LT0VDD25_2
AD20
LT0VDD25_3
AC20
LT0VDD25_4
AB20
SPDIF_IN_AVDD25
D14
USB_AVDD
E4
USB_AVDD33
D3
VDAC_AVDD33
D6
VAFE2_DVDD
D18
VAFE2_AVDD25_1
E17
VAFE2_AVDD25_2
D16
VAFE2_DVDD25
D17
VAFE3_DVDD
D9
VAFE3_AVDD25_1
D8
VAFE3_AVDD25_2
E8
VAFE3_AVDD25_3
F9
VAFE3_DVDD25
E9
PLL_AUD_AVDD
G25
PLL_MAIN_AVDD
K4
PLL_MIPS_AVDD
AD25
PLL_VAFE_AVDD
D11
TVM_OSC_AVDD
AE7
AUX_AVDD33
U6
AADC_AVSS F20
ADACA_AVSS G22
ADACC_AVSS G21
ADACD_AVSS F22
EPHY_AVSS F23
HDMI0_AVSS_1 F6
HDMI0_AVSS_2 G6
LT0VSS_1 AB22
LT0VSS_2 AB21
LT0VSS_3 AB19
LT0VSS_4 AC19
LT0VSS_5 AB18
LT0VSS_6 AB17
LT0VSS_7 AC17
SPDIF_IN_AVSS F15
USB_AVSS_1 G7
USB_AVSS_2 G8
VDAC_AVSS G9
VAFE2_VSS_1 G20
VAFE2_VSS_2 E18
VAFE2_VSS_3 G18
VAFE2_VSS_4 G17
VAFE2_VSS_5 F18
VAFE2_VSS_6 G16
VAFE2_VSS_7 F16
VAFE3_VSS_1 G13
VAFE3_VSS_2 G12
VAFE3_VSS_3 F12
VAFE3_VSS_4 G11
VAFE3_VSS_5 G10
VAFE3_VSS_6 F10
PLL_MIPS_AVSS AD26
PLL_VAFE_AVDD25
D12
TVM_OSC_AVSS AC7
very close
to SOC R22 pin
CORE 0.9V
POWER 2.5V
POWER 3.3V
MAIN POWER 312
BCM35230
closed to soc
close to soc
Close to LG1140
Close to Main SoC
RGB/CVBS_EMI_Improve
LOWHIGH
Not Support
DVR READY
MODEL_OPT_3
MODEL_OPT_0
MODEL_OPT_1
MODEL_OPT_2
Support
Not SupportSupport
MOTION R/C
RGB_EMI_Improve
Very close to L22 Ball
Place Cap
V_Sync_Out
T2 Tuner
external
URSA5
S Tuner
Not Support
1
Support
LOW
10 1
MODEL_OPT_0
Enable
0
MODEL_OPT_1
Support
1
DDR speed
PHM
MODEL OPTION
1600
MODEL_OPT_6
MODEL_OPT_5
1333
0
0
NO_FRC
DisableMODEL_OPT_7
BCM
internal
FRC
MODEL_OPT_4
Not Support
LG FRC2
HIGH
Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SC_G/COMP2_Y
INCM_TUNER
INCM_SIF
INCM_G
INCM_AUD_SC/COMP2
R321 5.1
AUD_LRCH
INCM_AUD_AV2
C322 0.1uF
C329 0.1uF
INCM_B
COMP1_Pr
INCM_AUD_AV1
C331 0.1uF
INCM_G
SPDIF_OUT
R313
10K
AUD_LRCK
AV2_CVBS_IN
INCM_TUNER
INCM_VID_COMP1
TU_CVBS
C319 0.1uF
AUD_SCK
R314
12K
C330 0.1uF
C304 0.1uF
INCM_B
INCM_R
INCM_VID_AV2
SC_R/COMP2_Pr
R319
10K
OPT
COMP1_Pb
C303 0.1uF
C325 0.1uF
C323 0.1uF
C324 0.1uF
R323 5.1
SC_B/COMP2_Pb
C317 0.1uF
DSUB_HSYNC
R322 5.1
DSUB_B+
C327 0.1uF
DSUB_G+
C332 0.1uF
INCM_VID_AV1
COMP1_Y
C321 0.1uF
DSUB_VSYNC
AV1_CVBS_IN
INCM_VID_AV1
DSUB_R+
INCM_VID_COMP1
+2.5V_BCM35230
C328 0.1uF
C326 0.1uF
C320 0.1uF
INCM_VID_SC/COMP2
+2.5V_BCM35230
R315
120
OPT
R305
240
OPT
R320
12K
OPT
INCM_SIF
INCM_VID_AV2
C318 0.1uF
AUD_MASTER_CLK
TU_RESET
C335 0.1uF
C333 0.1uF
C334 0.1uF
C336 0.1uF
INCM_VID_SC/COMP2
INCM_AUD_PC
R324 5.1
SCL3_3.3V
SDA3_3.3V
INCM_R
R307 0
AV1_R_IN C306 1uF 10V
INCM_AUD_AV1
AV1_L_IN
C307 1uF 10V
C305 1uF 10V
C310 1uF 10V
C309 1uF 10V
C308 1uF 10V
INCM_AUD_PC
PC_L_IN
PC_R_IN
SC/COMP2_L_IN C312 1uF 10V
C313 1uF 10V
SC/COMP2_R_IN
C311 1uF 10V
INCM_AUD_SC/COMP2
C315 1uF 10V
INCM_AUD_AV2
C314 1uF 10V
C316 1uF 10V
AV2_R_IN
AV2_L_IN
REMOTE_OR_MODULE_TX
+3.3V_Normal
R301
2.2K R302 2.2K
C301
33pF
50V
OPT
C302
33pF
50V
OPT
TU_SIF
TU_RESET_SUB
AV1_CVBS_DET
C300 1uF 10V
INCM_AUD_COMP1
COMP1_R_IN C338 1uF 10V
C337 1uF 10V
COMP1_L_IN
R300 5.1 INCM_AUD_COMP1
+3.3V_Normal
R325 33
C340
33pF
50V
OPT
R326 33
C339
33pF
50V
OPT
MOD_SDA
MOD_SCL
R328 0
R306
75
1/10W
1%
OPT
R309 0
R308 0
R333 0
R332 0
R330
1.2K
R329
1.2K
R311
36
R312
36
R317
36
R316
36
R304
36
R303
36
R318
0
R310
0
R331 0
LGE35230
IC101
VI_R
B6
VI_INCM_R
A6
VI_G
C7
VI_INCM_G
A7
VI_B
B7
VI_INCM_B
C8
HSYNC_IN
C13
VSYNC_IN
A13
VI_Y1
C9
VI_PR1
A9
VI_PB1
B9
VI_INCM_COMP1
B8
VI_SC_R1
C11
VI_SC_G1
A10
VI_SC_B1
B10
VI_INCM_SC1
C10
VI_FB_1/GPIO
D10
VI_FS1
F13
VI_SC_R2
A12
VI_SC_G2
C12
VI_SC_B2
B12
VI_INCM_SC2
B11
VI_FB_2/GPIO
E12
VI_FS2
E14
VI_L1
E15
VI_C1_1
F17
VI_INCM_LC1_1
E16
VI_C1_2
F14
VI_INCM_LC1_2
E11
VI_CVBS1
C18
VI_INCM_CVBS1
B18
VI_CVBS2
A18
VI_INCM_CVBS2
C19
VI_CVBS3
A19
VI_INCM_CVBS3
B19
VI_CVBS4
C20
VI_INCM_CVBS4
B20
VI_SIF1_1
E19
VI_INCM_SIF1_1
D19
VI_SIF1_2
E10
VI_INCM_SIF1_2
F11
LGE35230
IC101
SPDIF_INC_P
B15
SPDIF_INC_N
C15
SPDIF_IND_P
C14
SPDIF_IND_N
B14
I2SSCK_IN/GPIO
G4
I2SWS_IN
F4
I2SSD_IN/GPIO
G5
AADC_LINE_L1
C25
AADC_LINE_R1
B24
AADC_INCM1
A24
AADC_LINE_L2
E22
AADC_LINE_R2
E23
AADC_INCM2
D23
AADC_LINE_L3
C24
AADC_LINE_R3
C23
AADC_INCM3
B23
AADC_LINE_L4
E21
AADC_LINE_R4
D21
AADC_INCM4
D22
AADC_LINE_L5
B22
AADC_LINE_R5
C22
AADC_INCM5
A22
AADC_LINE_L6
F21
AADC_LINE_R6
D20
AADC_INCM6
E20
AADC_LINE_L7
A21
AADC_LINE_R7
C21
AADC_INCM7
B21
I2SSCK_OUTA/GPIO AF8
I2SWS_OUTA/GPIO AF9
I2SSD_OUTA0/GPIO AG9
I2SSOSCK_OUTA/GPIO AC9
I2SSD_OUTA1/GPIO AD8
I2SSD_OUTA2/GPIO AD9
I2SSCK_OUTC/GPIO E2
I2SWS_OUTC/GPIO F2
I2SSD_OUTC/GPIO E3
I2SSOSCK_OUTC/GPIO F3
I2SSCK_OUTD/GPIO G2
I2SWS_OUTD/GPIO G3
I2SSD_OUTD/GPIO G1
I2SSOSCK_OUTD/GPIO H1
SPDIF_OUTA/GPIO B13
AUDMUTE_0/GPIO AG8
AUDMUTE_1 E13
ADAC_AL_N C28
ADAC_AL_P C27
ADAC_AR_N D28
ADAC_AR_P D27
ADAC_CL_N C26
ADAC_CL_P A27
ADAC_CR_N B27
ADAC_CR_P B28
ADAC_DL_N B25
ADAC_DL_P A25
ADAC_DR_N A26
ADAC_DR_P B26
AUDIO INCM
VIDEO INCM
Run Along DSUB_R Trace
Run Along DSUB_G Trace
Run Along DSUB_B Trace
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace
Run Along AV2_CVBS Trace
Run Along TUNER_CVBS_IF_P Trace
Run Along AV1_CVBS Trace
Route Along With TUNER_SIF_IF_N
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace
Route Between AV1_L_IN & AV1_R_IN Trace
Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace
Route Between AV2_L_IN & AV2_R_IN Trace
Route Between PC_L_IN & PC_R_IN Trace
Near JK1104
JK1103
JK2501
JK1102
Near
Near
Near
TU2101/2
TU2201/2/3
JK801
Near
P801
Near
Near
Near
Near
Near
Near
P801
Near
JK1103
JK2501
JK1101
TU2101/2
TU2201/2/3
JK1104
P801
JK1102
Near
BCM35230
31
3
MAIN AUDIO/VIDEO
Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR_DQ[31]
DDR_DQ[29]
DDR_DQ[29]
DDR_DQ[4]
DDR_DM[0]
DDR_DQ[8]
DDR_DQ[18]
DDR_DQ[13]
DDR_DQ[16]
DDR_DQ[27]
DDR_DQ[10]
DDR_DQ[3]
DDR_DQ[4]
DDR_DQ[5]
DDR_DQ[10]
DDR_DQ[2]
DDR_DQ[17]
DDR_DM[3]
DDR_DQ[25]
DDR_DQ[2]
DDR_DQ[7]
DDR_DQ[26]
DDR_DQ[20]
DDR_DQ[6]
DDR_DQ[19]
DDR_DQ[17]
DDR_DQ[1]
DDR_DQ[21]
DDR_DQ[27]
DDR_DM[2]
DDR_DQ[0]
DDR_DQ[12]
DDR_DQ[1]
DDR_DQ[22]
DDR_DQ[26]
DDR_DQ[30]
DDR_DQ[25]
DDR_DQ[28]
DDR_DQ[8]
DDR_DQ[16]
DDR_DQ[14]
DDR_DQ[12]
DDR_DQ[7]
DDR_DQ[11]
DDR_DQ[14]
DDR_DQ[24]
DDR_DM[1]
DDR_DQ[31]
DDR_DQ[23]
DDR_DQ[19]
DDR_DQ[15]
DDR_DQ[22]
DDR_DQ[9]
DDR_DQ[6]
DDR_DQ[23]
DDR_DQ[20]
DDR_DQ[5]
DDR_DQ[24]
DDR_DQ[21]
DDR_DQ[13]
DDR_DQ[9]
DDR_DQ[18]
DDR_DQ[15]
DDR_DQ[30]
DDR_DQ[0]
DDR_DQ[3]
DDR_DQ[11]
DDR_DQ[28]
R405
4.7K
DDR_DQ[1]
R408
4.7K
R403
4.7K
R404
4.7K
HYNIX_DDR
DDR_DQ[8]
DDR_DQ[3]
DDR_DQ[0]
DDR_DQ[7]
DDR_DQ[4]
R406
4.7K
OPT
R410
4.7K
OPT
DDR_DQ[10]
R402
4.7K
OPT
DDR_DQ[5]
R401
4.7K R407 4.7K R409 4.7K
OPT
DDR_DQ[6]
DDR_DQ[2]
R432
4.7K
OPT
DDR_DQ[9]
R423
4.99K
1%
DDR23_AA4
DDR_AA9
DDR_QS3b
C439 1uF
DDR_CASb
DDR_AA8
DDR_AA14
DDR_CKE
DDR_QS3
DDR_WEb
DDR_RESETb
DDR_AA14
DDR_AA13
DDR01_CLK
R413
56
1%
DDR23_AA6
DDR23_AA5
DDR_QS0b
R419
56
1%
DDR_AA10
DDR_QS3b
+1.5V_DDR
DDR_BAA0
DDR_AA10
C437
100pF
DDR_AA12
DDR_AA3
DDR01_AA4
DDR_DQ[8-15]
DDR_AA14
R430
4.7K
OPT
C440 1uF
DDR23_AA5
DDR_BAA2
DDR_QS2b
DDR01_CLK
C416
0.01uF
C441 1uF
DDR_AA0
DDR_AA13
DDR_AA3
DDR_QS0
DDR_AA11
+1.5V_DDR
DDR_DQ[16-23]
DDR23_CLK
R427 56
DDR_CASb
DDR_AA3
+1.5V_DDR
DDR_BAA2
C450 0.1uF
DDR_DQ[0-7]
DDR_AA10
R411 240
1%
C454
1uF
6.3V
DDR_AA9
C423
10uF
DDR23_CLKb
DDR_WEb
R416
4.99K
1%
DDR_BAA1
DDR01_CLKb
DDR_AA9
DDR_VREFA
DDR_CKE
C425
10uF
DDR_DM[0]
DDR_RASb
+1.5V_DDR
DDR_BAA1
DDR01_CLKb
C415
0.01uF
DDR_AA0
C436
0.01uF
DDR_QS2
DDR_RESETb
DDR_QS3
R417
4.99K
1%
+1.5V_DDR
DDR_DQ[24-31]
DDR_AA12
DDR23_AA5
DDR23_AA6
DDR_AA13
DDR_RESETb
AR401 56
DDR_AA1
C438 1uF
R431
4.7K
OPT
DDR_AA2
+1.5V_DDR
DDR_AA12
DDR_AA2
DDR_AA2
C412
1uF C426 1uF
NFM18PS105R0J
C433
6.3V
OUTIN
GND
R420 10K
DDR_DQ[24-31]
K4B2G1646C
IC402
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
AR405 56
DDR_AA3
DDR_DQ[8-15]
DDR_QS1b
DDR23_CLK
DDR23_AA4
C442
100pF
C401
1000pF
R428
82
DDR_WEb
R429
82
DDR01_AA6
DDR_AA0
DDR_RESETb
DDR_DM[1]
DDR_AA0
DDR_VREFA
C452 0.1uF
C409 0.1uF
C405
10uF
DDR_RASb
DDR_QS1
AR403 56
DDR_CKE
DDR_DM[2]
C419
1000pF
DDR_QS1
DDR01_AA6
DDR_BAA0
DDR_DM[3]
DDR_AA7
+1.5V_DDR
R415 240
1%
DDR_AA1
DDR_AA7
DDR_DM[0-3]
C435
0.01uF
DDR_AA10
C404 0.1uF
AR404 56
DDR23_CLKb
R421 240
1%
DDR_CASb
C411 0.1uF
DDR01_AA4
NFM18PS105R0J
C402
6.3V
OUTIN
GND
DDR23_AA4
DDR_QS2b
DDR_QS0
R425 56 OPT
DDR_AA1
DDR_BAA2
DDR_DQ[0-7]
DDR_AA8
DDR_AA12
+1.5V_DDR
DDR_VREFA
DDR_DQ[16-23]
K4B2G1646C
IC401
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
+1.5V_DDR
DDR_WEb
DDR_BAA0
DDR_AA7
NFM18PS105R0J
C410
6.3V
OUTIN
GND
R426 56
+1.5V_DDR
C417
470pF
DDR_QS2
DDR_BAA0
DDR01_AA5
DDR_AA7 +1.5V_DDR
R414 10K
AR402 56
DDR_AA8
DDR_AA11
DDR_BAA2
R418
56
1%
DDR_AA1
DDR01_AA5
DDR01_AA5
DDR_AA8
DDR_AA2
C406 0.1uF
C403
2.2uF
DDR_QS0b
R422
4.99K
1%
DDR01_AA4 DDR_AA13 R424 56
AR406 56
DDR_RASb
DDR_AA11
C408 0.1uF
DDR_CKE
NFM18PS105R0J
C432
6.3V
OUTIN
GND
DDR_AA14
C451 0.1uF
DDR23_AA6
DDR_BAA1
C455
1uF
6.3V
DDR01_AA6
DDR_AA9
C421
2.2uF
C453
1uF
6.3V
R412
56
1%
DDR_AA11
+1.5V_DDR
DDR_QS1b
DDR_CASb
DDR_RASb
DDR_BAA1
C407
2.2uF
LGE35230
IC101
DDR_DQA_0
U26
DDR_DQA_1
R26
DDR_DQA_2
U27
DDR_DQA_3
R27
DDR_DQA_4
V27
DDR_DQA_5
P26
DDR_DQA_6
U25
DDR_DQA_7
P27
DDR_DQA_8
R24
DDR_DQA_9
N24
DDR_DQA_10
T25
DDR_DQA_11
M23
DDR_DQA_12
R23
DDR_DQA_13
N25
DDR_DQA_14
T24
DDR_DQA_15
N26
DDR_DQA_16
L26
DDR_DQA_17
H27
DDR_DQA_18
L27
DDR_DQA_19
J26
DDR_DQA_20
M27
DDR_DQA_21
G27
DDR_DQA_22
M26
DDR_DQA_23
H26
DDR_DQA_24
L23
DDR_DQA_25
H25
DDR_DQA_26
L24
DDR_DQA_27
J24
DDR_DQA_28
M24
DDR_DQA_29
H23
DDR_DQA_30
L25
DDR_DQA_31
H24
DDR_DMA_0
T26
DDR_DMA_1
P25
DDR_DMA_2
J27
DDR_DMA_3
K24
DDR_DQSA_P_0
T27
DDR_DQSA_N_0
T28
DDR_DQSA_P_1
P24
DDR_DQSA_N_1
P23
DDR_DQSA_P_2
K27
DDR_DQSA_N_2
K28
DDR_DQSA_P_3
K25
DDR_DQSA_N_3
K26
DDR_ADA_0 V23
DDR_ADA_1 AB27
DDR_ADA_2 Y23
DDR_ADA_3 Y26
DDR_ADA_4 AB26
DDR_ADA_5 Y24
DDR_ADA_6 AC26
DDR_ADA_ALT_4 AB24
DDR_ADA_ALT_5 AC25
DDR_ADA_ALT_6 AC24
DDR_ADA_7 AB25
DDR_ADA_8 AD28
DDR_ADA_9 Y25
DDR_ADA_10 AA27
DDR_ADA_11 AC27
DDR_ADA_12 AA26
DDR_ADA_13 AA24
DDR_ADA_14 AD27
DDR_BAA_0 Y27
DDR_BAA_1 AB28
DDR_BAA_2 W24
DDR_RASA_N V24
DDR_CASA_N W25
DDR_WEA_N V26
DDR_CKEA U24
DDR_CKA01_P W27
DDR_CKA01_N W28
DDR_CKA23_P N28
DDR_CKA23_N N27
DDR_VREFA U23
DDR_RST_N AA23
DDR_ZQ W26
JEDEC Types : DDR_DQ[0:4]
00001 : DDR3-1333H (CasL=9)
10101 : DDR3-1600K (CasL=11) (O)
Bus Width : DDR_DQ[10:9]
0 - 16b
1 - 32b (O)
DDR Voltage : DDR_DQ[7]
0 - 1.35V for DDR3
1 - 1.5V for DDR3 (O)
Chip Width : DDR_DQ[8]
0 - 8b
1 - 16b (O)
Chip Size : DDR_DQ[6:5]
00 - 4Gbit
01 - 2Gbit (O)
10 - 1Gbit
11 - 512Mbit
DDR STRAP
MAIN DDR 31 4
BCM35230
Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THERMAL
THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+2.5V_BCM35230
+5V_Normal
L514
BLM18PG121SN1D
+5V_USB
L513
BLM18PG121SN1D
C527
33uF
25V
MOD_ON
C514
0.1uF
16V
R515
100
P500
SMAW200-H18S1
14
9
4
18
13
8
3
17
12
7
2
16
11
6
1
15
10
5
19
R517
100
C528
10uF
6.3V
OPT
C521
0.1uF
16V
RL_ON
R514
100
L501
CB4532UK121E
EAM38058401
PSU_ERR_DET
C508
10uF
6.3V
OPT +5V_ST
C526
0.1uF
50V
R512
10K
OPT
P_+5V
P_17V
R5160
L504
MLB-201209-0120P-N2
0LCML00003B
R518
10K
OPT
AC_DET
+5V_ST
L503
MLB-201209-0120P-N2
0LCML00003B
R513
10K
OPT
C520
0.1uF
16V
C534
0.1uF
16V
IC503
AP2121N-3.3TRE1
EAN58801701
1
GND
2VOUT 3
VIN
+5V_ST +3.3V_ST
C541
0.1uF
16V
C535
10uF
6.3V
L507 CB3216PA501E EAM44020101
P_+5V
R519 910
1%
R521
1K
1%
C536
10uF
6.3V
C532
0.1uF
16V
C530
10uF
6.3V
OPT
R520 66.5
1%
L508
MLB-201209-0120P-N2
0LCML00003B
IC502
AZ1085S-ADJTR/E1
1
ADJ/GND
2OUTPUT 3
INPUT
C537
0.1uF
16V
P_+5V
C539
100uF
16V
OPT
P_17V
+5V_TU
+3.3V_Normal
C552
0.015uF
50V
C559
10uF
10V
R527
3.6K
C561
10uF
10V
OPT
C547
4.7uF
50V
R526
16K
C549
0.01uF
50V
D500
40V
MBRA340T3G
C545
4.7uF
50V
C556
10uF
10V
C551
0.1uF
50V
C565
0.1uF
16V
C566
100uF
16V
C564
22uF
10V
R538
0
1/10W
5%
R539
330
1/10W
1%
R537 110 1/10W 1%
R532
1.2K
1%
R529 0
R530
27K
1%
C558
47pF
50V
R531
10K
1%
R533 75
IC500
TPS54231D
3
EN
2
VIN
4
SS
1
BOOT
5VSENSE
6COMP
7GND
8PH
C555
820pF
50V
C531
47uF
16V
C582
22uF
16V
R552
13K
C590
22uF
16V
OPT
C586 0.01uF
C588
22uF
16V
R553
330K
C585
3300pF
50V
C589
22uF
16V
C587
0.1uF
50V
R551
0
L519
3.6uH
R554
22
C584 0.1uF 16V
OPT
C583
0.1uF
50V
L518
MLB-201209-0120P-N2
+3.3V_Normal
C592
0.1uF
16V
POWER_ON/OFF2_2
P_+5V
R523
0
1/10W
5%
C510
0.1uF
16V
C509
22uF
10V
3V3
C516
0.1uF
16V
+1.5V_DDR
C503
10uF
10V
IC504
AZ1085S-ADJTR/E1
1
ADJ/GND
2OUTPUT 3
INPUT
C505
22uF
10V
R541 0
R534 150
1%
R535
75 1%
R536
1K 1%
R550
2K
C523
10uF
6.3V
R546
2K1%
L502
MLB-201209-0120P-N2
C515 1000pF 50V
R547 10K
1%
C519
10uF
6.3V
OPT
R543
16K
C522
10uF
6.3V
OPT
C513
0.1uF
16V
OPT
C506
10uF
16V
C507
10uF
16V
L505
2uH
C511
0.1uF
50V
OPT
C517
10uF
6.3V
R544
10K
C525
3300pF
50V
OPT
R540
4.7K
OPT
+0.9V_CORE
C524
10uF
6.3V
C518
10uF
6.3V
R545
05%
R542 0
P_+5V
POWER_ON/OFF2_2
C533
100uF
16V
L511
22.0uH
IC506
AZ1117BH-ADJTRE1
2
OUTPUT
3
INPUT 1ADJ/GND
C529
100uF
16V
C542
100uF
16V C544
100uF
16V
C512
100uF
16V
+5V_Normal
R524 0
IC505
SN1007054RTER
1
VIN_1
3
GND_1
7
COMP
9SS
10 PH_1
11 PH_2
12 PH_3
13 BOOT 14 PWRGD 15 EN 16 VIN_3
5
AGND
8
RT/CLK
6
VSENSE
4
GND_2
2
VIN_2 17
EP[GND]
C591
100pF
50V
R555
51K
1%
R556 16K
1%
IC501
AOZ1038PI
3
AGND
2
VIN
4
FB
1
PGND
5COMP
6EN
7NC_1
8NC_2
9
[EP]LX
+0.9V_CORE_BCM35230(AOZ1038PI)
POWER 5
BCM35230
MAX 1A
MAX 1.9A
31
CURRENT: MAX 3A
CURRENT: MAX 6A
CURRENT: MAX 3A
Stand-by (5VST --> +3.3V)
R2
V0 = 1.25(1+R2/R1)
R1
Max 960 mA
+2.5V_BCM35230
R1
+5V_TU
R2
2A
+3.3V_NORMAL
+7V
6ms
+3.3V_NORMAL
R1
Vout=Vref*(1+R1/R2)|Vref=3.35V
R2
*MUST BE OPTIMAZE COMP (10.08.16)
+1.5V_DDR
V0 = 1.25(1+R2/R1)
R2 R1
R2
MAX 4000 mA
Switching freq: 555K
Placed on SMD-TOP
5A
R1
*NOTE 17
Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
AC_DET
MODEL1_OPT_3
R603 33
R601
47K
R611 10K
MODEL1_OPT_1
IR_MICOM
MODEL1_OPT_0
HDMI_CEC
R605 10K
NEC_RXD
MODEL1_OPT_2
R606 10K
OPT
R604 33
R608 10K
750/570
R610 10K
750/950
NEC_TXD
R609 10K
570
C601
0.1uF
R612 10K
OPT
LED_RED
R607 10K
950
R602 33
+3.3V_ST
MOD_ON
PSU_ERR_DET
LED_Power_On
LED_LOGO
SUB_SCL
SUB_SDA
DISP_EN
AMP_MUTE R629 33
R677
0
US
+3.3V_ST
IR_MICOM IR_OUT
R669
10K
+3.3V_ST
R675
0
US
IR
R672
47K
R671
47K
R676
0US
+3.3V_ST
Q603
2SC3052 EB
C
JK600
PEJ027-01
US
6B T_TERMINAL2 7B B_TERMINAL2
5T_SPRING 4R_SPRING
7A B_TERMINAL1 6A T_TERMINAL1
3E_SPRING
R674
0
KR_BR
Q602
2SC3052 EB
CR673
3.3K
R668
4.7K
R670
0
OPT
R667
22
R678
0
US
P602
12507WS-04L
OPT
1
2
3
4
5LED_LOGO
+5V_Normal
Q604
2SC3875S(ALY)
OPT
E
B
C
C610
10uF
10V
OPT
+3.3V_Normal
R680
4.7K
OPT
BLUE_LED_ON
NEC_ISP_Tx
X600
10MHz
R632
22
MODEL1_OPT_1
KEY1
OCD1A
R634
22
FLMD0
GND
C603
0.1uF
WIRELESS_DET
C608 1uF
KEY2
R622 22
SOC_RESET
MODEL1_OPT_0
EEPROM_SCL
RL_ON
R620 4.7K
EEPROM_SDA
WIRELESS_PWR_EN
GND
OCD1B
R621 4.7K
R623 22
MICOM_DOWNLOAD
EEPROM_SDA
SDA2_3.3V
SCL2_3.3V
MODEL1_OPT_2
NEC_ISP_Rx
EEPROM_SCL
R600 10K
C604 0.1uF
R681 0
IC601
M24C16-WMN6T
3
NC/E2
2
NC/E1
4
VSS
1
NC/E0
5SDA
6SCL
7WC
8VCC
R628 22
+3.3V_ST
+3.3V_ST
+3.3V_ST
+3.3V_ST
EDID_WP
MODEL1_OPT_3
R666 22
MICOM_RESET
R664 0
IC600
uPD78F0514
1
P60/SCL0
2
P61/SDA0
3
P62/EXSCL0
4
P63
5
P33/TI51/TO51/INTP4
6
P75
7
P74
8
P73/KR3
9
P72/KR2
10
P71/KR1
11
P70/KR0
12
P32/INTP3/OCD1B
13
P31/INTP2/OCD1A
14
P30/INTP1
15
P17/TI50/TO50
16
P16/TOH1/INTP5
17
P15/TOH0
18
P14/RXD6
19
P13/TXD6
20
P12/SO10
21
P11/SL10/RXD0
22
P10/SCK10/TXD0
23
AVREF
24
AVSS
25 ANI7/P27
26 ANI6/P26
27 ANI5/P25
28 ANI4/P24
29 ANI3/P23
30 ANI2/P22
31 ANI1/P21
32 P20/ANI0
33 P130
34 P01/TI010/TO00
35 P00/TI000
36 P140/PCL/INTP6
37 P120/INTP0/EXLVI 38 P41 39 P40 40 RESET 41 P124/XT2/EXCLKS 42 P123/XT1 43 FLMD0 44 P122/X2/EXCLK/OCD0B 45 P121/X1/OCD0A 46 REGC 47 VSS 48 VDD
R638
100K
OCD1B
OCD1A
+3.3V_ST
NEC_ISP_Tx
NEC_ISP_Rx
R617
10K
R639
0MICOM_DOWNLOAD
MICOM_RESET
006:H20;006:AA24
R637 680
C607
0.1uF
16V
+3.3V_ST
R635
0
+3.3V_ST
C609
10uF
16V
R682 0
R683 22
POWER_ON/OFF2_2
+3.3V_ST
R636 22
R619
4.7K
+3.3V_ST
R618
4.7K
R63322
R631 22
R627 22
OPT
R624 100
R626 0
R663
10K
+5V_Normal
AMP_RESET_N
TOUCH_Version_CHECK
+3.3V_ST
R641 10K
R614 10K
OPT
R616 10K
R615 10K
R613 10K
OPT
IC602
AZ7029RTRE1
OPT
2
GND
3
OUT 1VCC
SW600
SKHMPWE010
OPT
12
4 3
5
C605
15pF
50V
C606
15pF
50V
X601
32.768KHz
R640
4.7M
R648 100K 1/10W 1%
R662
120K
1/16W
1%
R625
22
R630 4.7K
P600
YFDW254-16S
14
9
4
13
8
3
12
7
2
16
11
6
1
15
10
5
NEC_ISP_Tx
FLMD0
OCD1B
MICOM_RESET
OCD1A
NEC_ISP_Rx
+3.3V_ST
Q3205
2SC3052
E
B
C
R642
10K
R643 20K
L600
BLM18PG121SN1D
OPT
R679
4.7K
1/16W
5%
OPT
C600
13pF
C602
13pF
31
Model option will be changed for GP3
MICOM MODEL OPTION
6
MICOM
BCM35230
WIRED-IR
wHITE_LED
HIGH
PIN NO.
MODEL1_OPT_2
DVB
950
LOW
MODEL1_OPT_3
8
11
MODEL1_OPT_0
MODEL PWM OPTION
GALAXY
ATSC
RED_LED ONLY
LCDPDP
570
MODEL1_OPT_1
PIN NAME
30
31
750/950
750/570
for Debugger
 
EEPROM for Micom
10Mhz Crystal
NEC CONFIGURATION
KDS
PZ570
PZ750
PZ950
OPT_1 OPT_2
0
0
0
1
1
0
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Only for training and service purposes
LGE Internal Use Only