Linear technology Dc1842a Quick setup guide

dc1843af

DEMO MANUAL DC1843A

DESCRIPTION

DC1842A and DC1680A

LTC4290B/LTC4271

8-Port PSE with Digital Isolation

Demonstration kit DC1843A is an 8-port Type 2 power

sourcing equipment (PSE) composed of a DC1842A

daughter card and DC1680A motherboard. The kit is used

for evaluation of the LTC4290B and LTC4271 PSE chipset.

Up to 8 powered devices (PDs) can be connected and

powered from this system using a single power supply.

A DC590 is connected to the DC1680A for I2C interfacing

with QuikEval™. This demonstration manual provides a

Quick Start Procedure, a DC1842A overview, a DC1680A

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

QuikEval is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

BOARD PHOTO

overview, schematics, BOMs, and layout printouts. Refer

totheLayoutGuideforDemonstrationCircuit1842Awhen

laying out the LTC4290B/LTC4271 circuit. Contact Linear

Technology for this document.

Design files for this circuit board are available at

http://www.linear.com/demo

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DEMO MANUAL DC1843A

QUICK START PROCEDURE

Figure 1. DC1842A Backside. Setting AUTO and MID Jumpers

Figure 2. Inserting the DC1842A into J1 of the DC1680A

Demonstration kit DC1843A includes the DC1842A

daughter card and DC1680A motherboard. The kit is set

up for evaluating the LTC4290B/LTC4271. Follow the pro-

cedure below and refer to Figures 1 through 4 for proper

equipment setup.

NOTE (DC1843A Kit): Connector J1 on the DC1680A has

four pegs blocking the unused last four pins to match the

30-pinconnectoroftheDC1842A.Dustcapsblockthefour

unused ports at each RJ45 connector on the DC1680A

for the 8-Port.

1. On the DC1842A set AUTO jumper JP1 to HI (Figure 1)

to enable AUTO pin mode.

2. On the DC1842A set MID jumper JP2 to LO (Figure 1)

to disable midspan mode.

3. Alignpin1ofthe30-pinmaleconnectorontheDC1842A

with pin 1 of the 30-pin female connector on the

DC1680A(Figure2).Pin12ispolarizedtoassistwiththe

alignment. Carefully push the DC1842A straight down

untilthetwo30-pinconnectorsareflushwitheachother.

4. On the DC1680A, connect a supply with the positive rail

to POS and negative rail to NEG (Figure 3). Use a power

supply capable of sourcing the maximum load expected

(8 ports ×850mA ≥ 6.8A). Ramp the supply up to 55V.

5. Connect up to 8 PDs to ports 1-8 at the DC1680A, J4

(Figure 3).

6. TheDC590isoptionallyconnectedtotheDC1680Acon-

nector J5 with a 14-pin ribbon cable (Figure 3). A GUI

for the LTC4290B/LTC4271 is brought up by QuikEval

for I2C interfacing from a PC (Figure 4).

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DEMO MANUAL DC1843A

QUICK START PROCEDURE

Figure 3. DC1680A Basic Setup

Figure 4. DC1843A System Setup with the DC590, DC1680A, DC1842A and 55V Power Supply

x 8

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1842A OPERATION

Figure 5. DC1842A 8-Port PSE Daughter Card with Digital Isolation Features the LTC4290B and LTC4271

8-Port PSE Daughter Card with Digital Isolation

Demonstration circuit 1842A (Figure 5) features the

LTC4290B/LTC4271 chipset on a compact daughter card

with digital isolation. The LTC4290B/LTC4271 chipset is

an 8-port power sourcing equipment (PSE) controller

designed for use in IEEE 802.3at Type 1 and Type 2 (high

power) compliant Power over Ethernet (PoE) systems. A

transformer isolated communication protocol replaces

expensiveopto-couplersandcomplexisolated3.3Vsupply

resulting in significant BOM cost savings. The LTC4290B/

LTC4271 chipset delivers lowest-in-industry heat dissipa-

tionbyutilizinglowRON externalMOSFETsand0.25Ωsense

resistors, eliminating the need for expensive heat sinks.

Advanced power management features in the LTC4290B/

LTC4271 chipset include: per port 12-bit current monitor-

ing ADCs, DAC programmable current limit, and versatile

quick shutdown of preselected ports. PD discovery uses a

proprietarydualmode4-pointdetectionmechanismensur-

ing excellent immunity from false PD detection. Midspan

PSEs are supported with 2-event classification and a two

second backoff timer. The LTC4290B/LTC4271 includes

an I2C serial interface operable up to 1MHz.

The DC1842A demonstrates proper LTC4290B/LTC4271

board layout that is approximately the height and width

of a 2 × 4 RJ45 connector. The compact layout is made

possiblebythesmallpackage size of key components. The

LTC4290Bis ina 6mm× 6mmQFN, whilethe LTC4271is in

a 4mm × 4mm QFN. Each port has a FDMC3612 MOSFET

in a 3mm × 3mm power33 package.

The daughter card inserts in the DC1680A motherboard

through J1, a polarized 30-pin connector. Isolated 3.3V

and logic control signals are brought in on this connec-

tor. Also connected at J1 is the PoE VEE supply from the

motherboard and 8 PSE controlled outputs.

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1842A OPERATION

Board Layout

Proper board layout is crucial for proper LTC4290B/

LTC4271 chipset operation, robustness, and accuracy.

When laying out, pay attention to parts placement, Kelvin

sensing, power paths, and copper fill. It is imperative to

followtheLTC4290B/LTC4271LayoutGuidefordemonstra-

tion circuit 1842A document when laying out the board.

ContactLinearTechnologyCorporation for this document.

Figure 6. DC1842A Digital and Analog Isolation

Isolation and Power Supplies

The LTC4290B/LTC4271 chipset provides communication

across an isolation barrier through a data transformer

(Figure 6). This eliminates the need for expensive opto-

couplers. All digital pins reside on the digital ground refer-

ence and are isolated from the analog PoE supply. A 3.3V

supply for VDD and an isolated VEE supply are connected

to the DC1842A through the 30-pin connector.

VDD33

DND

CPD

CND

DPD

AGND

VEE

DNA

VEE

ISOLATION

WÜRTH 7490100143

CPA

30-PIN

CONNECTOR

DC1842A SIDE DC1680A SIDE

VDD33 SUPPLY

VEE SUPPLY

CNA

DPA

TX+

RX–

CT(4)

CT(2)

RX+

TX–

TD+

RD–

CT(3)

RD+

TD–

LTC4271 U2

LTC4290

C23

1μF

C21

0.1μF

R13

100Ω

DC1843A F06

DGND

C19

1μF

100V

SMAJ58A

R14

100Ω

C22

1μF

R15

100Ω

R16

100Ω

R21

100Ω

R22

100Ω

R23

100Ω

R24

100Ω

C24, 2nF

2kV

–

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1842A OPERATION

Figure 7. DC1842A, LTC4271 I2C and Address Connections

I2C Communication and Addressing

TheLTC4271internalregistersare accessed viaI2Ctoread

and/or write configuration, status, and interrupt registers.

The I2C lines SDAOUT, SDAIN and SCL connect to the

34-pin connector (Figure 7). Subsequently, the I2C bus

is accessed on the DC1680A.

The LTC4290B/LTC4271 chipset has an address of

(A610A3A2A1A0b), where A6, A3, A2, A1, and A0are the

logic state of the AD6, AD3, AD2, AD1, and AD0 pins

respectively. On the DC1842A, AD0 and AD1 are tied low

with pull-down resistors. AD2, AD3 and AD6 are brought

out to the 30-pin connector (Figure 7) and set with three

switches on the DC1680A.

I/O LED Indicators

The DC1842A features four LEDs to indicate the states

of the LTC4290B/LTC4271 chipset general purpose input

outputpins.Thesepinsareconfiguredasinputsoroutputs

via I2C. GP1 and GP0 are referenced to DGND and driven

by the LTC4271 when set as outputs (Figure 8). XIO0 and

XIO1arereferencedtoVEE andare driven bytheLTC4290B

when set as outputs (Figure 9). J2 provides test points

for access to these I/Os.

Figure 8. DC1842A, LTC4290B General Purpose I/O LED Indicators

Figure 9. DC1842A, LTC4271 General Purpose I/O LED Indicators

Figure 10. DC1842A AUTO and MID Jumpers

DGND

SDAOUT

SDAIN

SCL

INT

SDAOUT

SDAIN

SCL

INT

AD6

AD3

AD2

AD1

AD0

AD6

AD3

AD2

TO 30-PIN

CONNECTOR

LTC4271

0Ω

DC1843A F07

0Ω R9

0Ω

VDD33

GP1

GP0

DGND

J2, PIN 5

J2, PIN 6

LTC4271

DC1843A F09

R28

560Ω R29

560Ω

GRN

GP0

GRN

GP1

VDD33

AUTO

MID

DGND

J2, PIN 3

J2, PIN 4

LTC4271

DC1843A F10

JP1 JP2

AUTO

MID

AGND

XIO1

XIO0

VEE

J2, PIN 9

J2, PIN 10

VEE

LTC4290

DC1843A F08

R30

27k R31

27k

GRN

XIO0

GRN

XIO1

Q13B

BC846AS

Q13A

BC846AS R33

220k

R32

220k

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1842A OPERATION

AUTO and MID Jumpers

The AUTO and MID pins of the LTC4271 are set by

jumpers JP1 and JP2 respectively on the DC1842A

(Figure 10). Setting JP1 to HI enables the AUTO pin mode

in the LTC4290B/LTC4271 chipset. J2 provides test points

for access to AUTO and MID.

In AUTO pin mode (JP1 high), the LTC4290B/LTC4271

chipset internal I2C registers default to the AUTO pin

high state after a software or hardware reset, or system

power on. The LTC4290B/LTC4271 chipset autonomously

detects,powerson anddisconnects power toPDs without

the need for I2C host control.

Setting JP1 to LO disables AUTO pin mode and sets the

LTC4290B/LTC4271 chipset to a low current shutdown

mode. An I2C host controller can then be used to config-

ure the LTC4290B/LTC4271 chipset to semi-auto mode

for controlled PSE operation or to manual mode for test

purposes.

Setting JP2 to HI enables the midspan mode detection

backoff timer in the LTC4290B/LTC4271 chipset. For

endpoint PSEs, set JP2 to LO to disable midspan mode.

For quick PSE evaluation in AUTO pin mode with

MIDSPANdisabled,setJP1HIandJP2LOontheDC1842A.

S1B Diodes Port Protection

Ethernet ports can be subject to significant ESD events

when long data cables, each potentially charged to thou-

sands of volts, are plugged into the low impedance of the

RJ45 jack. To protect against damage, each port requires

a pair of clamp diodes; one to AGND and one to VEE

(Figure 11). An additional surge suppressor is required

for each LTC4290B chip from VEE to AGND. The diodes

at the ports steer harmful surges into the supply rails,

where they are absorbed by the surge suppressor and

the VEE bypass capacitance. The surge suppressor has

the additional benefit of protecting the LTC4290B from

transients on the VEE supply.

S1B diodes work well as port clamp diodes. The two

S1B diodes per port are a part of the LTC4290B/LTC4271

application. These components are not on the DC1842A

due to space constraints but are shown in Figure 11 for

completeness.

In addition to the S1B diodes, a SMAJ58A or equivalent

is recommended for the VEE surge suppressor placed

directly across the AGND and VEE pins on the LTC4290B.

Figure 11. DC1842A, 1 of 8 Port Outputs. S1B Protection Diodes Located on the DC1680A

30-PIN

CONNECTOR

DC1842A SIDE DC1680A SIDE

DC1843A F11

VEE

VEE VEE

S1B

PROTECTION

S1B

VSSK

C19

1μF

100V

D26

B1100

4 × 1.00

FDMC3612

OUTn OUTn

PORT

SENSEn

RSENSEn

GATEn OUTn

LTC4290

AGND

SMAJ58A

C26

0.1μF

0.22μF

X7R

100V

VEE

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1680A OPERATION

Demonstration circuit 1680A is configured as an 8-Port,

IEEE802.3at Type 1 and Type 2 PoE PSE motherboard in

theDC1843A kit. ThisboardacceptsvariousPSEdaughter

cards featuring Linear Technology PSE controllers. The

DC1680A is capable of powering up to 8 PDs.

Daughter Card Insertion Precautions

When inserting or removing the daughter card into the

DC1843A, verify all supplies and LEDs are off. Push the

card straight down for insertion or pull straight up for

removal to avoid bending the connector pins. Follow the

instructions in the Quick Start Procedure for alignment.

VEE Supply

ConnectapowersupplyforVEE withthepositiverailtoPOS

and negative rail to NEG as shown in Figure 3 of the Quick

Start Procedure. Set the voltage within the range in Table 1

dependingon whether theapplication isaType1 or Type 2.

Choose a power supply rating and set the current limit

highenoughtoprovide power forthemaximumnumber of

PDs connected and to meet each PD power requirements.

Table 1. DC1680A VEE Power Range for Type 1 and Type 2 PSEs

PSE TYPE

VEE SUPPLY

RANGE

MAX DELIVERED

PORT POWER

POWER

SUPPLY*

Type 1 45V to 57V 13W 200W

Type 2 51V to 57V 25.5W 400W

*Recommended DC1843A power supply minimum to avoid drooping in

a worst-case scenario with ILIM current at all 8 ports.

PD Connection

PDs are connected using an Ethernet cable to any of the

8 ports at the 2×6, RJ45 connector J4 on the DC1680A

(Figure 3). J4 has an integrated Ethernet transformer and

common mode termination for each port. Test points for

port outputs OUT1 through OUT8 are provided.

8-Port Configuration

TheDC1680Aisconfiguredforan8-portPSEmotherboard

for the DC1843A kit. Four RJ45 dust caps at J3 and four

dust caps at J4 are inserted to block off the four unused

Ethernet ports. Additional pegs are placed in the last 4

pins of connector J1 to block off the unused pins when

the DC1842A daughter card is inserted.

DC1680A USER FEATURES

Refer to Figure 12 and Figure 13 for the following user

features.

Onboard 3.3V Supply

The DC1680A has an onboard VDD33 digital supply gen-

erated from the VEE supply. DGND is a negative voltage

referenced to AGND. If an external 3.3V supply is to be

used, contact Linear Technology Applications for proper

connection.

VEE and VDD33 LED Indicators

LEDs for VEE and VDD33 indicate if voltage is present at

these supplies. Verify these LEDs are off before inserting

or removing the daughter card.

Digital Connections

The DC1680A has connections for I2C control from a

host controller. The DC590 is optionally connected to

the DC1680A at J5 through a 14-pin ribbon cable. The

QuikEval software will automatically detect the DC1680A

and open the LTC4271 GUI. A second 14-pin ribbon cable

can be connected to J6 for I2C expansion to another

DC1680A board with slight board modifications. Contact

Linear Technology Applications for instructions.

Digital test points include SCL, SDA, DGND, INT, MSD,

and RESET. I2C address pin AD6, AD3, and AD2 are set

with a 3-bit switch SW3.

Midspan PSE

The DC1843A can be configured as a midspan PSE.

Upstream switch data comes in to J3. Data and PoE go

out to a PD at J4. Set both MID and AUTO pins logic high.

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1680A OPERATION

Figure 12. DC1680A Connections and Supply LEDs

MSD and RESET Pushbuttons

Pushbutton switch SW1, when pressed, pulls the RESET

pin of the daughter card logic low. The PSE controller is

thenheldinactive with allportsoff andallinternalregisters

reset to their power-up states. When SW1 is released,

RESET ispulledhigh,andthePSEbeginsnormaloperation.

Pushbutton switch SW2 when pressed pulls the maskable

shutdown input (MSD) pin of the daughter card logic low.

Whenpressed,allportsthathavetheircorrespondingmask

bit set in the mconfig register of the PSE controller will be

shutdown. These ports must then be manually re-enabled

via I2C or by resetting the PSE.

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1680A OPERATION

Figure 13. DC1680A Address Switch, Pushbutton Switches, INT LED, and Port Power LEDs

Interrupt LED

A red LED indicates when the INT line is pulled logic low

by the daughter card. When the interrupt is cleared (high)

via I2C servicing, the LED is turned off.

Port 1 Through 8 Power LED Indicators

Each PSE port has a green LED indicator to show when

PoE power is present at the port. The LEDs are driven by

the respective port OUT voltage.

DC1680A System Setup

Figure 14 shows a basic DC1680A system setup. The

DC1842A daughter card is inserted in the 30-pin connec-

tor J1. A power supply is connected to VEE with banana

cables. The DC590 connects with 14-pin ribbon cable

to the DC1680A and to a PC via USB. On the PC a GUI

communicates with the board. At the PSE output, PDs are

connected.AsamplePDdemoboardisshowninFigure14.

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1680A OPERATION

Figure 14. DC1680A and DC1842A System Setup with Power Supply, DC590 and PD Demo Board

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1842A LAYOUT

Top Silkscreen

Layer 1: Top Layer

Layer 2: VEE Plane 1

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DEMO MANUAL DC1843A

DEMONSTRATION CIRCUIT 1842A LAYOUT

Layer 3: VEE Plane 2

Layer 4: Bottom Layer

Bottom Silkscreen