LSI L80225 User manual

MD400182/B April, 2002 1 of 88
Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
®
L80225 10/100 MbpsTX/10BT
Ethernet Physical Layer Device
(PHY)
Technical Manual
Features
Note: Check for the latest revision of this document before start-
ing any designs. This document is available on the Web, at
www.lsilogic.com
•Single Chip 100Base-TX /10Base-T
physical layer solution
•Dual Speed - 10/100 Mbps
•Half and Full Duplex
•MII interface to Ethernet Controller
•MI interface for configuration & status
•Optional Repeater Interface
•AutoNegotiation: 10/100, Full/Half
Duplex
•Meets all applicable IEEE 802.3
standards
•Advertisement control through pins
•Adaptive Equalizer
•On-chip wave shaping - no external filters
required
•Baseline Wander Correction
•LED outputs
– Link
– Activity
– Collision
– Full Duplex
– 10/100
•Few external components
•3.3 V supply with 5 V tolerant I/O
•44 PLCC
Contents
Description - - - - - - - - - - - - - - - - - - - - - 2
Pin Description - - - - - - - - - - - - - - - - - - 4
Block Diagram- - - - - - - - - - - - - - - - - - - 8
Functional Description - - - - - - - - - - - - - 9
Register Description- - - - - - - - - - - - - - -43
Application Information - - - - - - - - - - - - 51
Specifications - - - - - - - - - - - - - - - - - - - 65
Ordering Information - - - - - - - - - - - - - - 84
Revision History - - - - - - - - - - - - - - - - - 84
Surface Mount Packages- - - - - - - - - - - 87

2 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
Description
The L80225 is a highly integrated analog interface IC for twisted pair
Ethernet applications. The L80225 can be configured for either
(100Base-TX) or 10 Mbps (10Base- T) Ethernet operation.
The L80225 consists of 4B5B/Manchester encoder/decoder,
scrambler/descrambler, transmitter with wave shaping and output driver,
twisted pair receiver with on chip equalizer and baseline wander
correction, clock and data recovery, AutoNegotiation, controller interface
(MII), and serial port (MI).
The addition of internal output waveshaping circuitry and on-chip filters
eliminates the need for external filters normally required in 100Base-TX
and 10Base-T applications.
The L80225 can automatically configure itself for 100 or 10 Mbps and
Full or Half Duplex operation with the on-chip AutoNegotiation algorithm.
The L80225 can access six 16-bit registers though the Management
Interface (MI) serial port. These registers contain configuration inputs,
status outputs, and device capabilities.
The L80225 is ideal as a media interface for 100Base-TX/ 10Base-T
adapter cards, motherboards, repeaters, switching hubs, and external
PHYs.
The L80225 operates from a single 3.3V supply. All inputs and outputs
are 5V tolerant and will directly interface to other 5V devices.

Description 3 of 88
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
Pin Configuration
FD_LED/(MDA1) L_LED/(MDA0)
GND2 TPI- TPI+ VDD1 TPO- TPO+ DUPLX GND1 ANEG
REXT
RESET
OSCIN
GND4
TX_EN
TX_ER
TXD3
TXD2
TXD1
TXD0
TX_CLK
C_LED/(MDA2)
LA_LED/(MDA3)
GND3
VDD2
SPEED
MDC
MDIO
COL
CRS
RX_DV
RX_ER
RXD3 RXD2 RXD1 RXD0
GND5
RPTR
VDD3
RX_CLK
RX_EN
GND6
VDD4
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
28 27 26 25 24 23 22 21 20 19 18 6
5 4 3 2 1
44 43 42 41 40
L80225
44 Pin PLCC
Top View

4 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
1 Pin Description
Pin Description
Pin # Pin Name I/O Description
28
24
10
1
VDD4
VDD3
VDD2
VDD1
—Positive Supply. 3.3 V ±5% Volts
27
22
36
9
4
41
GND6
GND5
GND4
GND3
GND2
GND1
—Ground. 0V
43 TPO+ O Twisted Pair Transmit Output, Positive.
44 TPO - O Twisted Pair Transmit Output, Negative.
2 TPI+ I Twisted Pair Receive Input, Positive.
3 TPI - I Twisted Pair Receive Input, Negative.
39 REXT — Transmit Current Set. An external resistor connected between this pin
and GND will set the output current for the TP and FX transmit outputs.
37 OSCIN I Clock Oscillator Input. There must be either a 25 MHz crystal between
this pin and GND or a 25 MHz clock applied to this pin. TX_CLK output
is generated from this input.
29 TX_CLK O Transmit Clock Output. This controller interface output provides a clock
to an external controller. Transmit data from the controller on TXD, TX_EN,
and TX_ER is clocked in on rising edges of TX_CLK and OSCIN.
35 TX_EN I Transmit Enable Input. This controller interface input has to be asserted
active high to indicate that data on TXD and TX_ER is valid, and it is
clocked in on rising edges of TX_CLK and OSCIN.
33
32
31
30
TXD3
TXD2
TXD1
TXD0
ITransmit Data Input. These controller interface inputs contain input nibble
data to be transmitted on the TP outputs, and they are clocked in on rising
edges of TX_CLK and OSCIN when TX_EN is asserted.
34 TX_ER I Transmit Error Input. This controller interface input causes a special pat-
tern to be transmitted on the twisted pair outputs in place of normal data,
and it is clocked in on rising edges of TX_CLK when TX_EN is asserted.

Pin Description 5 of 88
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
25 RX_CLK O Receive Clock Output. This controller interface output provides a clock
to an external controller. Receive data on RXD, RX_DV, and RX_ER is
clocked out on falling edges of RX_CLK.
15 CRS O Carrier Sense Output. This controller interface output is asserted active
high when valid data is detected on the receive twisted pair inputs, and it
is clocked out on falling edges of RX_CLK.
16 RX_DV O Receive Data Valid Output. This controller interface output is asserted
active high when valid decoded data is present on the RXD outputs, and
it is clocked out on falling edges of RX_CLK.
18
19
20
21
RXD3
RXD2
RXD1
RXD0
OReceive Data Output. These controller interface outputs contain receive
nibble data from the TP input, and they are clocked out on falling edges
of RX_CLK.
17 RX_ER O Receive Error Output. This controller interface output is asserted active
high when a coding or other specified errors are detected on the receive
twisted pair inputs and it is clocked out on falling edges of RX_CLK.
14 COL O Collision Output. This controller interface output is asserted active high
when a collision between transmit and receive data is detected.
12 MDC I Management Interface (MI) Clock Input. This MI clock shifts serial data
into and out of MDIO on rising edges.
13 MDIO I/O Management Interface (MI) Data Input/Output. This bidirectional pin
contains serial MI data that is clocked in and out on rising edges of the
MDC clock.
8LA_LED/
(MDA3) I/O
O.D.
Pullup
Link + Activity LED/Management Interface Address Input. This pin
indicates the occurrence of Link or Activity. It can drive an LED from VDD.
0 = Link Detect
Blink = Link Detect and Activity
1 = No Link Detect
During powerup or reset, this pin is high impedance and its value is
latched in as the physical device address MDA3 for the MI serial port.
7C_LED/
(MDA2) I/O
O.D.
Pullup
Collision LED Output/Management Interface Address Input. This pin
indicates the occurrence of a Collision. It can drive an LED from VDD.
0 = Collision Detect
1 = No Collision
During powerup or reset, this pin is high impedance and the value on this
pin is latched in as the physical device address MDA2 for the MI serial
port.
Pin Description (Cont.)
Pin # Pin Name I/O Description

6 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
6FD_LED/
(MDA1) I/O
Pullup Full Duplex LED Output/Management Interface Address Input. This pin a Full Duplex Detect output. It can drive an LED from VDD.
0 = Full Duplex Mode Detect with Link Pass
1 = Half Duplex
During powerup or reset, this pin is high impedance and its value is
latched in as the physical address device address MDA1 for the MI serial
port.
5L_LED/
(MDA0) I/O
Pullup Link LED Output/Management Interface Address Input. This pin is a 10/100 Mbps Detect output. It can drive an LED from VDD.
0 = 100 Mbit Mode Detected with Link Pass
1 = 10 Mbit Mode Detected
During powerup or reset, this pin is high impedance and the value on this
pin is latched in as the address MDA0 for the MI serial port.
26 RX_EN I Receive Enable Input
1 = All Outputs Enabled
0 = Receive Controller Outputs are High Impedance (RX_CLK,
RXD[3:0], RX_DV, RX_ER, COL).
23 RPTR I Repeater Mode Enable Input.
1 = Repeater Mode Enabled
0 = Normal Operation
11 SPEED I Speed Select Input. This input pin selects 10/100 Mbps operation when
pin ANEG = 0. When ANEG = 1, this pin controls the 10/100 advertise-
ment abilities of the device.
1 = 100 Mbps
0 = 10 Mbps
42 DPLX I Full/Half Duplex Select Input. This input pin selects Half/Full Duplex
operation when pin ANEG = 0. When ANEG = 1, this pin controls the
Half/Full Duplex advertisement abilities.
1 = Full Duplex
0 = Half Duplex
Pin Description (Cont.)
Pin # Pin Name I/O Description

Pin Description 7 of 88
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
40 ANEG I AutoNegotiation Enable Input.
1 = AutoNegotiation On
0 = AutoNegotiation Off
38 RESET I
Pullup RESET Input 1 = Normal Operation
0 = Device Reset
Pin Description (Cont.)
Pin # Pin Name I/O Description
ANEG Speed Duplx
0 0 0 Forced 10 Mbit Half Duplex Mode
0 0 1 Forced 10 Mbit Full Duplex Mode
0 1 0 Forced 100 Mbit Half Duplex Mode
0 1 1 Forced 100 Mbit Full Duplex Mode
1 0 0 AutoNegotiate and Advertise 10 M Half
Duplex only
1 0 1 AutoNegotiate and Advertise 10 M Half/Full
Duplex only
1 1 0 AutoNegotiate and Advertise all the capabili-
ties Mode (Default).
Note: To control advertisement through the
register, these three pins must be configured
in this default mode.
1 1 1 AutoNegotiate and Advertise 10/100 M Half
Duplex only

8 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
2 Block Diagram
Figure 1 Block Diagram
Clock
Generator
PLL
OSCIN
RESET
RX_EN
RPTR
ANEG
Interface
TX_CLK
TXD[3:0]
MDC
MDIO Serial
Controller
DPLX
SPEED
TX_EN
TX_ER
RX_CLK
RXD[3:0]
CRS
RX_DV
RX_ER
Collison
4B5B
Encoder Scrambler MLT3 Encoder Switched
Clock
Generator
LP
Filter
100BASETX Transmitter
ROM DAC LP
Filter +
−
4B5B
Decoder Descrambler Clock
Recovery
& Data
Auto-
& Link
Negotiation
Adaptive
Equalizer
LP
Filter
REXT
TPO+
TPO−
TPI+
TPI−
+
-
100BaseTX Receiver
10BaseTX Receiver
Recovery
Clock & Data
(Manchester
Decoder)
Manchester
Encoder
10BaseT Transmitter
Oscillator
COL
LED[3:0]
MDA[3:0] LED
Drivers
Port
(MI)
VDD[4:1]
GND[6:1]
Current
Sources
PLL
Squelch
+/− Vth
+
−
+
+/− Vth
+
−
+
Squelch
MLT3
Encoder
(MII)

Functional Description 9 of 88
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
3 Functional Description
3.1 General
The L80225 is a complete 100/10 Mbps Ethernet Media Interface IC. The
L80225 has nine main sections: controller interface, encoder, decoder,
scrambler, descrambler, clock and data recovery, twisted pair transmitter,
twisted pair receiver, and MI serial port. A block diagram is shown in
Figure 1.
The L80225 can operate as a 100Base-TX device (hereafter referred to
as 100 Mbps mode) or as a 10Base-T device (hereafter referred to as
10 Mbps mode). The difference between the 100 Mbps mode and the 10
Mbps mode is data rate, signaling protocol, and allowed wiring. The 100
Mbps TX mode uses two pairs of category 5 or better UTP or STP
twisted pair cable with 4B5B encoded, scrambled, and MLT-3 coded 62.5
MHz ternary data to achieve a throughput of 100 Mbps. The 10 Mbps
mode uses two pairs of category 3 or better UTP or STP twisted pair
cable with Manchester encoded, 10 MHz binary data to achieve a 10
Mbps throughput. The data symbol format on the twisted pair cable for
the 100 and 10 Mbps modes is defined in IEEE 802.3 specifications and
shown in Figure 2.
On the transmit side for 100 Mbps TX operation, data is received on the
controller interface from an external Ethernet controller per the format
shown in Figure 3. The data is then sent to the 4B5B encoder for
formatting. The encoded data is then sent to the scrambler. The
scrambled and encoded data is then sent to the TP transmitter. The TP
transmitter converts the encoded and scrambled data into MLT-3 ternary
format, preshapes the output, and drives the twisted pair cable.

10 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
Figure 2 TX/10BT Frame Format
Interframe
GAP PREAMBLE SFD DA SA LN LLC Data FCS Interframe
GAP
Ethernet MAC Frame
SSD DA SA LN LLC DATA FCS
100 Base-TX Data Symbols
IDLE PREAMBLE SFD ESD IDLE
IDLE =
SSD =
PREAMBLE =
SFD =
DA, SA, LN, LLC DATA, FCS =
ESD =
[ 1 1 1 1 ...]
[ 1 1 0 0 0 1 0 0 0 1 ]
[ 1 0 1 0 ...] 62 Bits Long
[ 1 1 ]
[ DATA ]
[ 0 1 1 0 1 0 0 1 1 1 ]
Before/After
4B5B Encoding,
Scrambling, and
MLT3 Coding
DA SA LN LLC DATA FCS
10 Base-T Data Symbols
IDLE PREAMBLE SFD SOI IDLE
IDLE =
PREAMBLE =
SFD =
DA, SA, LN, LLC DATA, FCS =
[ NoTransitions ]
[ 1 1 ]
[ DATA ]
[ 1 1 ] With No MID Bit
SOI = Transition
[ 1 0 1 0 ...] 62 Bits Long Before/After
Manchester
Encoding
SSD DA SA LN LLC DATA FCS
100 Base-FX Data Symbols
IDLE PREAMBLE SFD ESD IDLE
IDLE =
SSD =
PREAMBLE =
SFD =
DA, SA, LN, LLC DATA, FCS =
ESD =
[ 1 1 1 1 ...]
[ 1 1 0 0 0 1 0 0 0 1 ]
[ 1 0 1 0 ...] 62 Bits Long
[ 1 1 ]
[ DATA ]
[ 0 1 1 0 1 0 0 1 1 1 ]
Before/After
4B5B Encoding

Functional Description 11 of 88
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
Figure 3 MII Frame Format
PRMBLE SFD DATA 1
TX_EN = 1
PREAMBLE =
SFD =
DATAn =
IDLE =
[ 1 0 1 0 ...] 62 Bits Long
[ 1 1 ]
[Between 64−1518 Data Bytes]
TX_EN = 0
TX_EN = 0
IDLE PREAMBLE
Start of
Frame DATA Nibbles
DATA 2 DATA N-1 DATA N
62 Bits 2 Bits
a. MII Frame Format
b. MII Nibble Order
D0 D1 D2 D3 D4
First Bit MACs Serial Bit Stream
D5 D6 D7
LSB
TXD2/RXD2
TXD3/RXD3
TX_EN = 0
IDLE
MSB
Second
Nibble
TXD0/RXD0
TXD1/RXD1
First
Nibble
MII
Nibble
Stream
Signals
TXD1
TXD2
TXD3
TX_EN
1. 1st preamble nibble transmitted.
2. 1st SFD nibble transmitted.
3. 1st data nibble transmitted.
4. D0 thru D7 are the first 8 bits of the data field.
X
X
X
0
TXD0 X X
X
X
0
X0
1
0
1
110
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
120
1
1
1
1D1
D2
D3
1
D03D5
D6
D7
1
D43
c. Transmit Preamble and SFD Bits
Signals
RXD1
RXD2
RXD3
RX_DV
1. 1st preamble nibble received. Depending on mode, device may eliminate either all or some of the preamble
nibbles, up to 1st SFD nibble.
2. 1st SFD nibble received.
3. 1st data nibble received.
4. D0 thru D7 are the first 8 bits of the data field.
X
X
X
0
RXD0 X 0
1
0
1
110
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
10
1
0
1
120
1
1
1
1D1
D2
D3
1
D03D5
D6
D7
1
D43
d. Receive Preamble and SFD Bits
Delim.
Bit Value
Bit Value

12 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
On the receive side for 100 Mbps TX operation, the twisted pair receiver
receives incoming encoded and scrambled MLT-3 data from the twisted
pair cable, removes any high frequency noise, equalizes the input signal
to compensate for the effects of the cable, qualifies the data with a
squelch algorithm, and converts the data from MLT-3 coded twisted pair
levels to internal digital levels. The output of the twisted pair receiver then
goes to a clock and data recovery block which recovers a clock from the
incoming data, uses the clock to latch in valid data into the device, and
converts the data back to NRZ format. The NRZ data is then
unscrambled and decoded by the 4B5B decoder and descrambler,
respectively, and outputted to an external Ethernet controller by the
controller interface.
10 Mbps operation is similar to the 100 Mbps TX operation except, (1)
there is no scrambler/descrambler, (2) the encoder/decoder is
Manchester instead of 4B5B, (3) the data rate is 10 Mbps instead of 100
Mbps, and (4) the twisted pair symbol data is two level Manchester
instead of ternary MLT-3.
The Management Interface, (hereafter referred to as the MI serial port),
is a two pin bidirectional link through which configuration inputs can be
set and status outputs can be read.
Each block plus the operating modes are described in more detail in the
following sections. Since the L80225 can operate as either a 100Base-
TX or a 10Base-T device, each of the following sections describes the
performance of the respective section in both the 100 and 10 Mbps
modes.

Functional Description 13 of 88
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
3.2 Differences between 80220/80221, L80225, and 80223
3.3 Controller Interface
3.3.1 General
The L80225 has two interfaces to an external controller: Media
Independent Interface (referred to as the MII).
3.3.2 MII - 100 Mbps
The MII is a nibble wide packet data interface defined in IEEE 802.3 and
shown in Figure 3. The L80225 meets all the MII requirements outlined
in IEEE 802.3. The L80225 can directly connect, without any external
logic, to any Ethernet controllers or other devices which also complies
with the IEEE 802.3 MII specifications. The MII frame format is shown in
Figure 3.
The MII consists of eighteen signals: four transmit data bits (TXD[3:0]),
transmit clock (TX_CLK), transmit enable (TX_EN), transmit error
(TX_ER), four receive data bits (RXD[3:0]), receive clock (RX_CLK),
carrier sense (CRS), receive data valid (RX_DV), receive data error
Table 1 80221, L80225, and 80223
Difference 80221 L80225 80223
Power Supply 5V 3.3V 3.3V
RESET Pin No Yes Yes
FX Interface No Yes Yes
Transmit Xfmr. Winding Ratio 2:1 1:1 1:1
T4 Interface Yes No No
Speed Pin No Yes Yes
Duplx Pin No Yes Yes
Hardware Advertisement Control No Yes No
Registers 16-20 Yes No Yes

14 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
(RX_ER), and collision (COL). The transmit and receive clocks operate
at 25 MHz in 100 Mbps mode.
On the transmit side, the TX_CLK output runs continuously at 25 MHz.
When no data is to be transmitted, TX_EN has to be deasserted. While
TX_EN is deasserted, TX_ER and TXD[3:0] are ignored and no data is
clocked into the device. When TX_EN is asserted on the rising edge of
TX_CLK, data on TXD[3:0] is clocked into the device on rising edges of
the TX_CLK output clock. TXD[3:0] input data is nibble wide packet data
whose format needs to be the same as specified in IEEE 802.3 and
shown in Figure 3. When all data on TXD[3:0] has been latched into the
device, TX_EN has to be deasserted on the rising edge of TX_CLK.
TX_ER is also clocked in on rising edges of the TX_CLK clock. TX_ER
is a transmit error signal which, when asserted, will substitute an error
nibble in place of the normal data nibble that was clocked in on TXD[3:0].
The error nibble is defined to be the /H/ symbol, which is defined in IEEE
802.3 and shown in Table 2.
Since OSCIN input clock generates the TX_CLK output clock, TXD[3:0],
TX_EN, and TX_ER are also clocked in on rising edges of OSCIN.
On the receive side, as long as a valid data packet is not detected, CRS
and RX_DV are deasserted and RXD[3:0] is held low. When the start of
packet is detected, CRS and RX_DV are asserted on falling edge of
RX_CLK. The assertion of RX_DV indicates that valid data is clocked out
on RXD[3:0] on falling edges of the RX_CLK clock. The RXD[3:0] data
has the same frame structure as the TXD[3:0] data and is specified in
IEEE 802.3 and shown in Figure 3. When the end of packet is detected,
CRS and RX_DV are deasserted, and RXD[3:0] is held low. CRS and
RX_DV also stay deasserted if the device is in the Link Fail State.
RX_ER is a receive error output which is asserted when certain errors
are detected on a data nibble. RX_ER is asserted on the falling edge of
RX_CLK for the duration of that RX_CLK clock cycle during which the
nibble containing the error is being outputted on RXD[3:0].
The collision output, COL, is asserted whenever the collision condition is
detected.

Functional Description 15 of 88
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
3.3.3 MII - 10 Mbps
10 Mbps operation is identical to the 100 Mbps operation except, (1)
TX_CLK and RX_CLK clock frequency is reduced to 2.5 MHZ, (2)
TX_ER is ignored, (3) RX_ER is disabled and always held low, and (4)
receive operation is modified as follows: On the receive side, when the
squelch circuit determines that invalid data is present on the TP inputs,
the receiver is idle. During idle, RX_CLK follows TX_CLK, RXD[3:0] is
held low, and CRS and RX_DV are deasserted. When a start of packet
is detected on the TP receive inputs, CRS is asserted and the clock
recovery process starts on the incoming TP input data. After the receive
clock has been recovered from the data, the RX_CLK is switched over
to the recovered clock and the data valid signal RX_DV is asserted on a
falling edge of RX_CLK. Once RX_DV is asserted, valid data is clocked
out on RXD[3:0] on falling edges of the RX_CLK clock. The RXD[3:0]
data has the same packet structure as the TXD[3:0] data and is
formatted on RXD[3:0] as specified in IEEE 802.3 and shown in Figure 3.
When the end of packet is detected, CRS and RX_DV are deasserted.
CRS and RX_DV also stay deasserted as long as the device is in the
Link Fail State.
3.3.4 MII Disable
The MII inputs and outputs can be disabled by setting the MII disable bit
in the MI serial port Control register. When the MII is disabled, the MII
inputs are ignored, the MII outputs are placed in high impedance state,
and the TP output is high impedance.
If the MI address lines, MDA[3:0], are pulled high during reset or
powerup, the L80225 powers up and resets with the MII disabled.
Otherwise, the L80225 powers up and resets with the MII enabled.
3.3.5 Receive Output High Impedance Control
The RX_EN pin can be configured to be RX_EN, a high impedance
control for the receive controller output signals, by setting the R/J
Configuration select bit in the MI serial port Configuration 2 register.
When this pin is configured to be RX_EN and is deasserted active low,
the following outputs will be placed in the high impedance state:
RX_CLK, RXD[3:0], RX_DV, RX_ER, and COL.

16 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
3.3.6 TX_EN to CRS Loopback Disable
The internal TX_EN to CRS loopback can be disabled by appropriately
setting the TXEN to CRS loopback disable bit in the MI serial port
Configuration 1 register.
3.4 Encoder
3.4.1 4B5B Encoder - 100 Mbps
100Base-TX requires that the data be 4B5B encoded. 4B5B coding
converts the 4-Bit data nibbles into 5-Bit date code words. The mapping
of the 4B nibbles to the 5B code words is specified in IEEE 802.3 and
shown in Table 2. The 4B5B encoder on the L80225 takes 4B nibbles
from the controller interface, converts them into 5B words according to
Table 2, and sends the 5B words to the scrambler. The 4B5B encoder
also substitutes the first 8 bits of the preamble with the SSD delimiters
(a.k.a. /J/K/ symbols) and adds an ESD delimiter (a.k.a. /T/R/ symbols)
to the end of every packet, as defined in IEEE 802.3 and shown in
Figure 2. The 4B5B encoder also fills the period between packets, called
the idle period, with the a continuous stream of idle symbols, as shown
in Figure 2.
3.4.2 Manchester Encoder - 10 Mbps
The Manchester encoding process combines clock and NRZ data such
that the first half of the data bit contains the complement of the data, and
the second half of the data bit contains the true data, as specified in
IEEE 802.3. This guarantees that a transition always occurs in the middle
of the bit cell. The Manchester encoder on the L80225 converts the 10
Mbps NRZ data from the controller interface into a Manchester Encoded
data stream for the TP transmitter and adds a start of idle pulse (SOI) at
the end of the packet as specified in IEEE 802.3 and shown in Figure 2.
The Manchester encoding process is only done on actual packet data,

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and the idle period between packets is not Manchester encoded and
filled with link pulses.
Table 2 4B/5B Symbol Mapping
Symbol Name Description 5B Code 4B Code
0 Data 0 11110 0000
1 Data 1 01001 0001
2 Data 2 10100 0010
3 Data 3 10101 0011
4 Data 4 01010 0100
5 Data 5 01011 0101
6 Data 6 01110 0110
7 Data 7 01111 0111
8 Data 8 10010 1000
9 Data 9 10011 1001
A Data A 10110 1010
B Data B 10111 1011
C Data C 11010 1100
D Data D 11011 1101
E Data E 11100 1110
F Data F 11101 1111
I Idle 11111 0000
J SSD #1 11000 0101
K SSD #2 10001 0101
T ESD #1 01101 0000
R ESD #2 00111 0000

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3.5 Decoder
3.5.1 4B5B Decoder - 100 Mbps
Since the TP input data is 4B5B encoded on the transmit side, it must
also be decoded by the 4B5B decoder on the receive side. The mapping
of the 5B nibbles to the 4B code words is specified in IEEE 802.3 and
shown in Table 2. The 4B45 decoder on the L80225 takes the 5B code
words from the descrambler, converts them into 4B nibbles per Table 2,
and sends the 4B nibbles to the controller interface. The 4B5B decoder
also strips off the SSD delimiter (a.k.a. /J/K/ symbols) and replaces them
with two 4B Data 5 nibbles (a.k.a. /5/ symbol), and strips off the ESD
delimiter (a.k.a. /T/R/ symbols) and replaces it with two 4B Data 0 nibbles
(a.k.a. /I/ symbol), per IEEE 802.3 specifications and shown in Figure 2.
The 4B5B decoder detects SSD, ESD and, codeword errors in the
incoming data stream as specified in IEEE 802.3. These errors are
indicated by asserting RX_ER output while the errors are being
transmitted across RXD[3:0], and they are also indicated in the serial
port by setting SSD, ESD, and codeword error bits in the MI serial port
Status Output register.
3.5.2 Manchester Decoder - 10 Mbps
In Manchester coded data, the first half of the data bit contains the
complement of the data, and the second half of the data bit contains the
true data. The Manchester decoder in the L80225 converts the
Manchester encoded data stream from the TP receiver into NRZ data for
the controller interface by decoding the data and stripping off the SOI
H Halt 00100 Undefined
--- Invalid codes All others100001
1. These 5B codes are not used. For decoder, these 5B codes are
decoded to 4B 0000. For encoder, 4B 0000 is encoded to 5B
11110, as shown in symbol Data 0.
Table 2 4B/5B Symbol Mapping (Cont.)
Symbol Name Description 5B Code 4B Code

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April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
pulse. Since the clock and data recovery block has already separated the
clock and data from the TP receiver, the Manchester decoding process
to NRZ data is inherently performed by that block.
3.6 Clock and Data Recovery
3.6.1 Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data present on
the TP inputs, the PLL is locked to the 25 MHz TX_CLK. When valid data
is detected on the TP inputs with the squelch circuit and when the
adaptive equalizer has settled, the PLL input is switched to the incoming
data on the TP input. The PLL then recovers a clock by locking onto the
transitions of the incoming signal from the twisted pair wire. The
recovered clock frequency is a 25 MHz nibble clock, and that clock is
outputted on the controller interface signal RX_CLK.
3.6.2 Data Recovery - 100 Mbps
Data recovery is performed by latching in data from the TP receiver with
the recovered clock extracted by the PLL. The data is then converted
from a single bit stream into nibble wide data word according to the
format shown in Figure 3.
3.6.3 Clock Recovery - 10 Mbps
The clock recovery process for 10 Mbps mode is identical to the 100
Mbps mode except, (1) the recovered clock frequency is 2.5 MHz nibble
clock, (2) the PLL is switched from TX_CLK to the TP input when the
squelch indicates valid data, (3) The PLL takes up to 12 transitions (bit
times) to lock onto the preamble, so some of the preamble data symbols
are lost, but the clock recovery block recovers enough preamble symbols
to pass at least 6 nibbles of preamble to the receive controller interface
as shown in Figure 3.
3.6.4 Data Recovery - 10 Mbps
The data recovery process for 10 Mbps mode is identical to the 100
Mbps mode. As mentioned in the Manchester Decoder section, the data
recovery process inherently performs decoding of Manchester encoded
data from the TP inputs.

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3.7 Scrambler
3.7.1 100 Mbps
100Base-TX requires scrambling to reduce the radiated emissions on the
twisted pair. The L80225 scrambler takes the encoded data from the
4B5B encoder, scrambles it per the IEEE 802.3 specifications, and sends
it to the TP transmitter.
3.7.2 10 Mbps
A scrambler is not used in 10 Mbps mode.
3.8 Descrambler
3.8.1 100 Mbps
The L80225 descrambler takes the scrambled data from the data
recovery block, descrambles it per the IEEE 802.3 specifications, aligns
the data on the correct 5B word boundaries, and sends it to the 4B5B
decoder.
The algorithm for synchronization of the descrambler is the same as the
algorithm outlined in the IEEE 802.3 specification. Once the descrambler
is synchronized, it will maintain synchronization as long as enough
descrambled idle pattern 1's are detected within a given interval. To stay
in synchronization, the descrambler needs to detect at least 25
consecutive descrambled idle pattern 1's in a 1 ms interval. If 25
consecutive descrambled idle pattern 1's are not detected within the 1
ms interval, the descrambler goes out of synchronization and restarts the
synchronization process.
If the descrambler is in the unsynchronized state, the descrambler loss
of synchronization detect bit is set in the MI serial port Status Output
register to indicate this condition. Once this bit is set, it will stay set until
the descrambler achieves synchronization.
3.8.2 10 Mbps
A descrambler is not used in 10 Mbps mode.