Marvell ARMADA 88F6810 Guide

Marvell. Moving Forward Faster
Doc. No. MV-S302310-U0, Rev. A
August 30, 2017
Document Classification: Public
88F6810, 88F6820 and 88F6828 Hardware Design Guide
88F6810, 88F6820 and
88F6828
ARMADA®38x Family
High-Performance Single/Dual Core
CPU System on Chip
Hardware Design Guide

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88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
Page 2 Document Classification: Public August 30, 2017

Revision History
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 3
Revision History
Table 1: Revision History
Revision Date Comments
A August 30, 2017 Initial Public Release

88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
Page 1 Document Classification: Public August 30, 2017
Table of Contents
Revision History ....................................................................................................................................... 3
Introduction ............................................................................................................................................... 3
1 4-Layer Board Recommendations ............................................................................................. 5
1.1 Stack-Up Example .......................................................................................................................................... 5
1.2 General Guidelines ......................................................................................................................................... 6
1.3 88F6810, 88F6820 and 88F6828 Power Filtering ........................................................................................... 7
1.4 Routing Guidelines for the ISET Signal ........................................................................................................... 8
1.5 Board Recommendations for Stripline Routing PCB ....................................................................................... 8
2 Generic Guidelines for SERDES Interfaces .............................................................................. 9
2.1 Insertion Loss and Loss Budget ...................................................................................................................... 9
2.2 Inter-Symbol Interference (ISI) ...................................................................................................................... 12
2.3 Placement of Devices and Connectors on the Board .................................................................................... 14
2.4 PCB Materials Selection ............................................................................................................................... 15
2.5 Crosstalk ....................................................................................................................................................... 16
2.6 Return Path Continuity .................................................................................................................................. 18
2.7 Target Routing Impedance ............................................................................................................................ 20
2.8 Capacitive Discontinuities ............................................................................................................................. 23
2.9 Trace Symmetry and Matching—Mode Conversion ...................................................................................... 25
2.10 Via Structures ................................................................................................................................................ 25
2.11 Selecting the Appropriate Components ........................................................................................................ 29
3 Generic Power Board Guidelines ............................................................................................ 30
3.1 Generic Power Network Guidelines .............................................................................................................. 30
3.2 DC Voltage Drop ........................................................................................................................................... 31
3.3 Polygon Shape Considerations ..................................................................................................................... 31
3.4 Analog Power Filtering .................................................................................................................................. 32
3.5 Core Power Decoupling ................................................................................................................................ 34
3.6 I/O Power Bypassing ..................................................................................................................................... 34
3.7 Bulk Capacitors ............................................................................................................................................. 35
3.8 Termination Voltage (VTT) Layout Recommendations ................................................................................ 36
4 Unused Interface ....................................................................................................................... 37
5 JTAG Connection Information ................................................................................................. 38
6 16-bit SDRAM DDR3 Interface ................................................................................................. 39
6.1 Interface Connectivity .................................................................................................................................... 39

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6.2 Interface Signals Layout Guidelines .............................................................................................................. 44
6.3 Special Software Setting ............................................................................................................................... 55
7 32-bit SDRAM DDR3 Interface .................................................................................................. 56
7.1 Interface Connectivity .................................................................................................................................... 56
7.2 Interface Signals Layout Guidelines .............................................................................................................. 61
7.3 Power Signals ............................................................................................................................................... 73
7.4 Special Software Setting ............................................................................................................................... 73
8 32-bit SDRAM DDR4 Interface .................................................................................................. 75
8.1 Interface Connectivity .................................................................................................................................... 75
8.2 Interface Signals Layout Guidelines .............................................................................................................. 78
8.3 Power Signals ............................................................................................................................................... 83
8.4 Special Software Setting ............................................................................................................................... 84
9 Network Ethernet Ports ............................................................................................................. 85
10 Reduced Gigabit Media Independent Interface (RGMII) ......................................................... 86
10.1 Interface Connectivity .................................................................................................................................... 86
10.2 Connectivity ................................................................................................................................................... 86
10.3 Interface Signals Layout Guidelines .............................................................................................................. 87
11 Serial Gigabit Media Independent Interface (SGMII) ............................................................. 91
11.1 Interface Connectivity .................................................................................................................................... 91
11.2 Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection ............................................. 92
11.3 Power Considerations ................................................................................................................................... 94
11.4 Specific Signals ............................................................................................................................................. 94
12 High Speed Serial Gigabit Media Independent Interface (HS-SGMII) ................................... 95
12.1 Interface Connectivity .................................................................................................................................... 95
12.2 Interface Signals Layout Guidelines .............................................................................................................. 96
12.3 Power Considerations ................................................................................................................................... 98
12.4 Specific Signals ............................................................................................................................................. 98
13 Quad Serial Gigabit Media Independent Interface (QSGMII) ................................................ 99
13.1 Interface Connectivity .................................................................................................................................... 99
13.2 Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection ........................................... 100
13.3 Clock Considerations .................................................................................................................................. 102
13.4 Power Considerations ................................................................................................................................. 102
13.5 Specific Signals ........................................................................................................................................... 102
14 PCI Express (PCIe) Interface 1.0/1.1 ..................................................................................... 103
14.1 Connectivity ................................................................................................................................................. 103
14.2 Interface Signals Layout Guidelines ............................................................................................................ 105

88F6810, 88F6820 and 88F6828
Hardware Design Guide
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14.3 Power Considerations ................................................................................................................................. 109
14.4 Specific Signals .......................................................................................................................................... 109
15 PCI Express (PCIe) Interface 2.0 ........................................................................................... 111
15.1 Connectivity ................................................................................................................................................. 111
15.2 Interface Signals Layout Guidelines ............................................................................................................ 113
15.3 Power Considerations ................................................................................................................................. 119
15.4 Reference Clock Considerations ................................................................................................................. 119
15.5 Specific Signals .......................................................................................................................................... 119
16 Universal Serial Bus (USB) 2.0 Interface .............................................................................. 120
16.1 Interface Connectivity .................................................................................................................................. 120
16.2 Interface Signals Layout Guidelines ............................................................................................................ 122
16.3 Power Considerations ................................................................................................................................. 125
16.4 Specific Signals ........................................................................................................................................... 125
17 Universal Serial Bus (USB) 3.0 Interface .............................................................................. 126
17.1 General Design Considerations .................................................................................................................. 126
17.2 Interface Connectivity .................................................................................................................................. 126
18 Serial ATA (SATA) Interface 3.0 ............................................................................................. 131
18.1 Connectivity ................................................................................................................................................. 131
18.2 Interface Signals Layout Guidelines ............................................................................................................ 131
18.3 Clock Considerations .................................................................................................................................. 133
18.4 Power Considerations ................................................................................................................................. 133
18.5 Specific Signals ........................................................................................................................................... 133
19 SDIO 3.0 and MMC 4.4 ............................................................................................................. 134
19.1 Interface Connectivity .................................................................................................................................. 134
19.2 Connectivity ................................................................................................................................................. 134
20 Serial Management Interface (SMI) ....................................................................................... 137
20.1 Interface Connectivity .................................................................................................................................. 137
20.2 Interface Signals Layout Guidelines ............................................................................................................ 137
21 Device Bus Interface ............................................................................................................... 139
21.1 Device Bus Interface Connectivity .............................................................................................................. 139
21.2 DEV_READYn Support ............................................................................................................................... 142
21.3 Device Bus Interface Control Signals at Reset ........................................................................................... 142
21.4 NAND Flash Support ................................................................................................................................... 143
22 General Clock Guidelines ...................................................................................................... 144
22.1 Core Clock .................................................................................................................................................. 145

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23 ARMADA®38x Family Clock Topology ................................................................................ 147
23.1 Clock Topology ........................................................................................................................................... 147
23.2 PCI Express Clock Topology ...................................................................................................................... 148
24 Adaptive Voltage Scaling (AVS) ............................................................................................. 151
24.1 Connectivity ................................................................................................................................................. 151

88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
Page 1 Document Classification: Public August 30, 2017
List of Figures
Figure 1: Insertion Loss Curve ....................................................................................................................... 10
Figure 2: Typical Trace Differential Amplitude Insertion Loss and ISI ........................................................... 12
Figure 3: Difference in Attenuation Due To ISI - Time Domain Influence ...................................................... 13
Figure 4: ISI Originated Jitter - Eye Pattern ................................................................................................... 13
Figure 5: Stack-up Cross-section with a High Probability of Crosstalk .......................................................... 17
Figure 6: Non-continuous Reference Plane Return Current Path Influence .................................................. 19
Figure 7: Layer Transfer ................................................................................................................................ 19
Figure 8: Reference Plane Clearance ............................................................................................................ 21
Figure 9: Changed Width for Differential Impedance Compensation ............................................................. 22
Figure 10: Voids Underneath AC Coupling Capacitors' Pads .......................................................................... 23
Figure 11: Voids Underneath BGA Device Ball ............................................................................................... 24
Figure 12: Voids Underneath SMT Connector/QFP Lead Frame Pads ........................................................... 24
Figure 13: Proper Deskew ............................................................................................................................... 25
Figure 14: Via Structures ................................................................................................................................. 26
Figure 15: Via Stubs ........................................................................................................................................ 27
Figure 16: Differential Via Structure ................................................................................................................. 27
Figure 17: Recommended Via Structure Dimensions for SERDES Interface up to 12.5 Gbps ....................... 28
Figure 18: Recommended Via Structure Dimensions for 25 Gbps SERDES Interfaces .................................. 29
Figure 19: Coupling of Vias .............................................................................................................................. 31
Figure 20: Routing Length Between the Capacitor and the Vias .....................................................................31
Figure 21: Required Analog Power Filter Voltage Transfer Function ............................................................... 32
Figure 22: Analog Power Filter Example ......................................................................................................... 33
Figure 23: Return Path Discontinuity—Bypass Capacitor ............................................................................... 35
Figure 24: Placement of a Bypass Capacitor in Relation to Device Ground Pins ............................................ 35
Figure 25: JTAG Connection ........................................................................................................................... 38
Figure 26: On Board 1x16-bit Wide Memory Device with ECC Connected to the Controller ........................... 41
Figure 27: On Board 2x8-bit Wide Memory Devices with ECC Connected to the Controller ........................... 42
Figure 28: On Board 16-bit, 4x8-bit Wide Memory Devices with ECC Connected to the Controller ................ 43
Figure 29: On Board 16-bit, 1x16-bit Wide Memory with ECC Topology—Address and Control .................... 45
Figure 30: On Board 16-bit, 1x16-bit Single-Side Assembly Topology with ECC—Data ................................. 46
Figure 31: On Board 16-bit, 2x8-bit Wide Memory Topology with ECC —Address
and Control in Daisy Chain .............................................................................................................48
Figure 32: On-Board 16-bit, 2x8-bit with ECC, Single-Side Assembly Topology—Data .................................. 49
Figure 33: On Board 16-bit, 4x8-bit Wide Memory Topology for Clock/Address/Command/Control with
ECC Implemented as a Clamshell Assembly .................................................................................52
Figure 34: On Board 16-bit, 4x8-bit Wide Memory with ECC Topology for Data ............................................. 53
Figure 35: On-Board 32-bit 2 Memory Devices, 2x16-bit Single-Side Connectivity ......................................... 58
Figure 36: On-Board 32-bit, 4x8-bit Single-Side Connectivity ......................................................................... 59
Figure 37: On-Board 32-bit, 8x8-bit Clamshell Connectivity with ECC ............................................................ 60
Figure 38: On-Board 32-bit, 2x16-bit Single-Side Assembly Topology—Address and Control with ECC ....... 62

List of Figures
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 2
Figure 39: On-Board 32-bit, 2x16-bit Single-Side Assembly Topology with ECC—Data ................................. 63
Figure 40: On-Board 32-bit, 4x8-bit Single-Side Assembly Topology with ECC—Address and Control ......... 66
Figure 41: On-Board 32-bit, 4x8-bit, with ECC, Single-Side Assembly Topology—Data ................................. 67
Figure 42: On-Board 32-bit, 8x8-bit Clamshell Topology with ECC—Address and Control ............................. 70
Figure 43: On-Board 32-bit, 8x8-bit Clamshell Topology with ECC—Data ...................................................... 71
Figure 44: On-Board 32-bit, 4x8-bit Single-Side Connectivity ......................................................................... 77
Figure 45: On-Board 32-bit, 4x8-bit Single-Side Assembly Topology with ECC—Address and Control ......... 80
Figure 46: On-Board 32-bit, 4x8-bit, with ECC, Single-Side Assembly Topology—Data ................................. 81
Figure 47: RGMII Port Connection to PHY ...................................................................................................... 87
Figure 48: RGMII Port Connection to Another RGMII MAC ............................................................................. 87
Figure 49: RGMII Routing Topology ................................................................................................................ 88
Figure 50: SGMII Generic Point-to-Point Connection ...................................................................................... 91
Figure 51: SGMII Topology for Chip-to-Chip, End-to-End Connection ............................................................ 92
Figure 52: SGMII Generic Point-to-Point Connection ...................................................................................... 95
Figure 53: Topology for Chip-to-Chip, End-to-End Connection ....................................................................... 96
Figure 54: QSGMII Generic Point-to-Point Connection ................................................................................... 99
Figure 55: QSGMII Topology for Chip-to-Chip, End-to-End Connection ....................................................... 100
Figure 56: PCI Express Interface Connectivity .............................................................................................. 104
Figure 57: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell®Device ............. 104
Figure 58: Topology with an Existing Connector and/or an Add-in Card ....................................................... 105
Figure 59: Topology with a Same-Board Connection .................................................................................... 108
Figure 60: PCI Express Interface Connectivity .............................................................................................. 112
Figure 61: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell®Device ............. 113
Figure 62: Topology with an Existing Connector and/or an Add-in Card ....................................................... 114
Figure 63: Topology with a Same-Board Connection .................................................................................... 117
Figure 64: USB 2.0 Interface Connectivity to a Connector—Including Optional Common Mode Choke and
Protection Diodes Circuitry ...........................................................................................................120
Figure 65: Vbus Connectivity when Configured as a Host ............................................................................. 121
Figure 66: Vbus Connectivity when Configured as a Device .........................................................................121
Figure 67: Topology—Including Common Mode Choke and Protection Diodes Optional Circuitry—when
Configured as a Device ...............................................................................................................122
Figure 68: Topology—Including Optional Common Mode Choke and Protection Diodes Circuitry—when
Configured as a Host ....................................................................................................................124
Figure 69: Topology—Including Common Mode Choke and Protection Diodes
Optional Circuitry—when Configured as a Device .......................................................................127
Figure 70: Topology—Including Optional Common Mode Choke and Protection
Diodes Circuitry—when Configured as a Host ..............................................................................129
Figure 71: SATA Interface Connectivity ......................................................................................................... 131
Figure 72: Topology for Connection to a Standard SATA 3.0 1-Meter Cable ................................................ 132
Figure 73: SDIO 3.0/MMC4.4 Connection to Connector Side ....................................................................... 134
Figure 74: SDIO 3.0/MMC 4.4 Routing Topology .......................................................................................... 135
Figure 75: Clock Transition Examples ........................................................................................................... 138
Figure 76: Master SMI Connectivity Example ................................................................................................ 138
Figure 77: Using Two 8-bit Flash Devices to Comprise a 16-bit Bus ............................................................. 139
Figure 78: Example of a 16-bit Wide Device Connection .............................................................................. 140

88F6810, 88F6820 and 88F6828
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Page 3 Document Classification: Public August 30, 2017
Figure 79: Example of a 512 KB Flash Device with an 8-bit Data Bus Connection ....................................... 141
Figure 80: DEV_READYn Connection Example ............................................................................................ 142
Figure 81: Connectivity for Chip Enable Don’t Care NAND Flash ................................................................ 143
Figure 82: Core Clock Connectivity ............................................................................................................... 145
Figure 83: Reference Clock Distribution ........................................................................................................ 146
Figure 84: Clock Topology ............................................................................................................................. 147
Figure 85: Internal Reference Clock with up to 2 PCIe Root Complex Ports ................................................. 148
Figure 86: External Reference Clock with 4 PCIe Root Complex Ports ......................................................... 149
Figure 87: External Reference Clock with 1 PCIe Endpoint and 3 Root Complex Ports ............................... 149
Figure 88: Internal Reference Clock Topology with 4 PCIe Root Complex Ports .......................................... 150
Figure 89: Internal Reference Clock Topology with 1 PCIe Endpoint and 3 Root Complex Ports ................. 150
Figure 90: Board Connectivity for VDD_CPU with Direct AVS Feedback Connection ................................. 152
Figure 91: Board Connectivity for VDD_CPU with AVS Feedback Connection with Resistor Voltage
Divider Regulator ..........................................................................................................................152