Marvell ARMADA 88F6810 Guide

Marvell. Moving Forward Faster
Doc. No. MV-S302310-U0, Rev. A
August 30, 2017
Document Classification: Public
88F6810, 88F6820 and 88F6828 Hardware Design Guide
88F6810, 88F6820 and
88F6828
ARMADA®38x Family
High-Performance Single/Dual Core
CPU System on Chip
Hardware Design Guide

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88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
Page 2 Document Classification: Public August 30, 2017

Revision History
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 3
Revision History
Table 1: Revision History
Revision Date Comments
A August 30, 2017 Initial Public Release

88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
Page 1 Document Classification: Public August 30, 2017
Table of Contents
Revision History ....................................................................................................................................... 3
Introduction ............................................................................................................................................... 3
1 4-Layer Board Recommendations ............................................................................................. 5
1.1 Stack-Up Example .......................................................................................................................................... 5
1.2 General Guidelines ......................................................................................................................................... 6
1.3 88F6810, 88F6820 and 88F6828 Power Filtering ........................................................................................... 7
1.4 Routing Guidelines for the ISET Signal ........................................................................................................... 8
1.5 Board Recommendations for Stripline Routing PCB ....................................................................................... 8
2 Generic Guidelines for SERDES Interfaces .............................................................................. 9
2.1 Insertion Loss and Loss Budget ...................................................................................................................... 9
2.2 Inter-Symbol Interference (ISI) ...................................................................................................................... 12
2.3 Placement of Devices and Connectors on the Board .................................................................................... 14
2.4 PCB Materials Selection ............................................................................................................................... 15
2.5 Crosstalk ....................................................................................................................................................... 16
2.6 Return Path Continuity .................................................................................................................................. 18
2.7 Target Routing Impedance ............................................................................................................................ 20
2.8 Capacitive Discontinuities ............................................................................................................................. 23
2.9 Trace Symmetry and Matching—Mode Conversion ...................................................................................... 25
2.10 Via Structures ................................................................................................................................................ 25
2.11 Selecting the Appropriate Components ........................................................................................................ 29
3 Generic Power Board Guidelines ............................................................................................ 30
3.1 Generic Power Network Guidelines .............................................................................................................. 30
3.2 DC Voltage Drop ........................................................................................................................................... 31
3.3 Polygon Shape Considerations ..................................................................................................................... 31
3.4 Analog Power Filtering .................................................................................................................................. 32
3.5 Core Power Decoupling ................................................................................................................................ 34
3.6 I/O Power Bypassing ..................................................................................................................................... 34
3.7 Bulk Capacitors ............................................................................................................................................. 35
3.8 Termination Voltage (VTT) Layout Recommendations ................................................................................ 36
4 Unused Interface ....................................................................................................................... 37
5 JTAG Connection Information ................................................................................................. 38
6 16-bit SDRAM DDR3 Interface ................................................................................................. 39
6.1 Interface Connectivity .................................................................................................................................... 39

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6.2 Interface Signals Layout Guidelines .............................................................................................................. 44
6.3 Special Software Setting ............................................................................................................................... 55
7 32-bit SDRAM DDR3 Interface .................................................................................................. 56
7.1 Interface Connectivity .................................................................................................................................... 56
7.2 Interface Signals Layout Guidelines .............................................................................................................. 61
7.3 Power Signals ............................................................................................................................................... 73
7.4 Special Software Setting ............................................................................................................................... 73
8 32-bit SDRAM DDR4 Interface .................................................................................................. 75
8.1 Interface Connectivity .................................................................................................................................... 75
8.2 Interface Signals Layout Guidelines .............................................................................................................. 78
8.3 Power Signals ............................................................................................................................................... 83
8.4 Special Software Setting ............................................................................................................................... 84
9 Network Ethernet Ports ............................................................................................................. 85
10 Reduced Gigabit Media Independent Interface (RGMII) ......................................................... 86
10.1 Interface Connectivity .................................................................................................................................... 86
10.2 Connectivity ................................................................................................................................................... 86
10.3 Interface Signals Layout Guidelines .............................................................................................................. 87
11 Serial Gigabit Media Independent Interface (SGMII) ............................................................. 91
11.1 Interface Connectivity .................................................................................................................................... 91
11.2 Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection ............................................. 92
11.3 Power Considerations ................................................................................................................................... 94
11.4 Specific Signals ............................................................................................................................................. 94
12 High Speed Serial Gigabit Media Independent Interface (HS-SGMII) ................................... 95
12.1 Interface Connectivity .................................................................................................................................... 95
12.2 Interface Signals Layout Guidelines .............................................................................................................. 96
12.3 Power Considerations ................................................................................................................................... 98
12.4 Specific Signals ............................................................................................................................................. 98
13 Quad Serial Gigabit Media Independent Interface (QSGMII) ................................................ 99
13.1 Interface Connectivity .................................................................................................................................... 99
13.2 Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection ........................................... 100
13.3 Clock Considerations .................................................................................................................................. 102
13.4 Power Considerations ................................................................................................................................. 102
13.5 Specific Signals ........................................................................................................................................... 102
14 PCI Express (PCIe) Interface 1.0/1.1 ..................................................................................... 103
14.1 Connectivity ................................................................................................................................................. 103
14.2 Interface Signals Layout Guidelines ............................................................................................................ 105

88F6810, 88F6820 and 88F6828
Hardware Design Guide
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14.3 Power Considerations ................................................................................................................................. 109
14.4 Specific Signals .......................................................................................................................................... 109
15 PCI Express (PCIe) Interface 2.0 ........................................................................................... 111
15.1 Connectivity ................................................................................................................................................. 111
15.2 Interface Signals Layout Guidelines ............................................................................................................ 113
15.3 Power Considerations ................................................................................................................................. 119
15.4 Reference Clock Considerations ................................................................................................................. 119
15.5 Specific Signals .......................................................................................................................................... 119
16 Universal Serial Bus (USB) 2.0 Interface .............................................................................. 120
16.1 Interface Connectivity .................................................................................................................................. 120
16.2 Interface Signals Layout Guidelines ............................................................................................................ 122
16.3 Power Considerations ................................................................................................................................. 125
16.4 Specific Signals ........................................................................................................................................... 125
17 Universal Serial Bus (USB) 3.0 Interface .............................................................................. 126
17.1 General Design Considerations .................................................................................................................. 126
17.2 Interface Connectivity .................................................................................................................................. 126
18 Serial ATA (SATA) Interface 3.0 ............................................................................................. 131
18.1 Connectivity ................................................................................................................................................. 131
18.2 Interface Signals Layout Guidelines ............................................................................................................ 131
18.3 Clock Considerations .................................................................................................................................. 133
18.4 Power Considerations ................................................................................................................................. 133
18.5 Specific Signals ........................................................................................................................................... 133
19 SDIO 3.0 and MMC 4.4 ............................................................................................................. 134
19.1 Interface Connectivity .................................................................................................................................. 134
19.2 Connectivity ................................................................................................................................................. 134
20 Serial Management Interface (SMI) ....................................................................................... 137
20.1 Interface Connectivity .................................................................................................................................. 137
20.2 Interface Signals Layout Guidelines ............................................................................................................ 137
21 Device Bus Interface ............................................................................................................... 139
21.1 Device Bus Interface Connectivity .............................................................................................................. 139
21.2 DEV_READYn Support ............................................................................................................................... 142
21.3 Device Bus Interface Control Signals at Reset ........................................................................................... 142
21.4 NAND Flash Support ................................................................................................................................... 143
22 General Clock Guidelines ...................................................................................................... 144
22.1 Core Clock .................................................................................................................................................. 145

Table of Contents
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23 ARMADA®38x Family Clock Topology ................................................................................ 147
23.1 Clock Topology ........................................................................................................................................... 147
23.2 PCI Express Clock Topology ...................................................................................................................... 148
24 Adaptive Voltage Scaling (AVS) ............................................................................................. 151
24.1 Connectivity ................................................................................................................................................. 151

88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
Page 1 Document Classification: Public August 30, 2017
List of Figures
Figure 1: Insertion Loss Curve ....................................................................................................................... 10
Figure 2: Typical Trace Differential Amplitude Insertion Loss and ISI ........................................................... 12
Figure 3: Difference in Attenuation Due To ISI - Time Domain Influence ...................................................... 13
Figure 4: ISI Originated Jitter - Eye Pattern ................................................................................................... 13
Figure 5: Stack-up Cross-section with a High Probability of Crosstalk .......................................................... 17
Figure 6: Non-continuous Reference Plane Return Current Path Influence .................................................. 19
Figure 7: Layer Transfer ................................................................................................................................ 19
Figure 8: Reference Plane Clearance ............................................................................................................ 21
Figure 9: Changed Width for Differential Impedance Compensation ............................................................. 22
Figure 10: Voids Underneath AC Coupling Capacitors' Pads .......................................................................... 23
Figure 11: Voids Underneath BGA Device Ball ............................................................................................... 24
Figure 12: Voids Underneath SMT Connector/QFP Lead Frame Pads ........................................................... 24
Figure 13: Proper Deskew ............................................................................................................................... 25
Figure 14: Via Structures ................................................................................................................................. 26
Figure 15: Via Stubs ........................................................................................................................................ 27
Figure 16: Differential Via Structure ................................................................................................................. 27
Figure 17: Recommended Via Structure Dimensions for SERDES Interface up to 12.5 Gbps ....................... 28
Figure 18: Recommended Via Structure Dimensions for 25 Gbps SERDES Interfaces .................................. 29
Figure 19: Coupling of Vias .............................................................................................................................. 31
Figure 20: Routing Length Between the Capacitor and the Vias .....................................................................31
Figure 21: Required Analog Power Filter Voltage Transfer Function ............................................................... 32
Figure 22: Analog Power Filter Example ......................................................................................................... 33
Figure 23: Return Path Discontinuity—Bypass Capacitor ............................................................................... 35
Figure 24: Placement of a Bypass Capacitor in Relation to Device Ground Pins ............................................ 35
Figure 25: JTAG Connection ........................................................................................................................... 38
Figure 26: On Board 1x16-bit Wide Memory Device with ECC Connected to the Controller ........................... 41
Figure 27: On Board 2x8-bit Wide Memory Devices with ECC Connected to the Controller ........................... 42
Figure 28: On Board 16-bit, 4x8-bit Wide Memory Devices with ECC Connected to the Controller ................ 43
Figure 29: On Board 16-bit, 1x16-bit Wide Memory with ECC Topology—Address and Control .................... 45
Figure 30: On Board 16-bit, 1x16-bit Single-Side Assembly Topology with ECC—Data ................................. 46
Figure 31: On Board 16-bit, 2x8-bit Wide Memory Topology with ECC —Address
and Control in Daisy Chain .............................................................................................................48
Figure 32: On-Board 16-bit, 2x8-bit with ECC, Single-Side Assembly Topology—Data .................................. 49
Figure 33: On Board 16-bit, 4x8-bit Wide Memory Topology for Clock/Address/Command/Control with
ECC Implemented as a Clamshell Assembly .................................................................................52
Figure 34: On Board 16-bit, 4x8-bit Wide Memory with ECC Topology for Data ............................................. 53
Figure 35: On-Board 32-bit 2 Memory Devices, 2x16-bit Single-Side Connectivity ......................................... 58
Figure 36: On-Board 32-bit, 4x8-bit Single-Side Connectivity ......................................................................... 59
Figure 37: On-Board 32-bit, 8x8-bit Clamshell Connectivity with ECC ............................................................ 60
Figure 38: On-Board 32-bit, 2x16-bit Single-Side Assembly Topology—Address and Control with ECC ....... 62

List of Figures
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 2
Figure 39: On-Board 32-bit, 2x16-bit Single-Side Assembly Topology with ECC—Data ................................. 63
Figure 40: On-Board 32-bit, 4x8-bit Single-Side Assembly Topology with ECC—Address and Control ......... 66
Figure 41: On-Board 32-bit, 4x8-bit, with ECC, Single-Side Assembly Topology—Data ................................. 67
Figure 42: On-Board 32-bit, 8x8-bit Clamshell Topology with ECC—Address and Control ............................. 70
Figure 43: On-Board 32-bit, 8x8-bit Clamshell Topology with ECC—Data ...................................................... 71
Figure 44: On-Board 32-bit, 4x8-bit Single-Side Connectivity ......................................................................... 77
Figure 45: On-Board 32-bit, 4x8-bit Single-Side Assembly Topology with ECC—Address and Control ......... 80
Figure 46: On-Board 32-bit, 4x8-bit, with ECC, Single-Side Assembly Topology—Data ................................. 81
Figure 47: RGMII Port Connection to PHY ...................................................................................................... 87
Figure 48: RGMII Port Connection to Another RGMII MAC ............................................................................. 87
Figure 49: RGMII Routing Topology ................................................................................................................ 88
Figure 50: SGMII Generic Point-to-Point Connection ...................................................................................... 91
Figure 51: SGMII Topology for Chip-to-Chip, End-to-End Connection ............................................................ 92
Figure 52: SGMII Generic Point-to-Point Connection ...................................................................................... 95
Figure 53: Topology for Chip-to-Chip, End-to-End Connection ....................................................................... 96
Figure 54: QSGMII Generic Point-to-Point Connection ................................................................................... 99
Figure 55: QSGMII Topology for Chip-to-Chip, End-to-End Connection ....................................................... 100
Figure 56: PCI Express Interface Connectivity .............................................................................................. 104
Figure 57: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell®Device ............. 104
Figure 58: Topology with an Existing Connector and/or an Add-in Card ....................................................... 105
Figure 59: Topology with a Same-Board Connection .................................................................................... 108
Figure 60: PCI Express Interface Connectivity .............................................................................................. 112
Figure 61: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell®Device ............. 113
Figure 62: Topology with an Existing Connector and/or an Add-in Card ....................................................... 114
Figure 63: Topology with a Same-Board Connection .................................................................................... 117
Figure 64: USB 2.0 Interface Connectivity to a Connector—Including Optional Common Mode Choke and
Protection Diodes Circuitry ...........................................................................................................120
Figure 65: Vbus Connectivity when Configured as a Host ............................................................................. 121
Figure 66: Vbus Connectivity when Configured as a Device .........................................................................121
Figure 67: Topology—Including Common Mode Choke and Protection Diodes Optional Circuitry—when
Configured as a Device ...............................................................................................................122
Figure 68: Topology—Including Optional Common Mode Choke and Protection Diodes Circuitry—when
Configured as a Host ....................................................................................................................124
Figure 69: Topology—Including Common Mode Choke and Protection Diodes
Optional Circuitry—when Configured as a Device .......................................................................127
Figure 70: Topology—Including Optional Common Mode Choke and Protection
Diodes Circuitry—when Configured as a Host ..............................................................................129
Figure 71: SATA Interface Connectivity ......................................................................................................... 131
Figure 72: Topology for Connection to a Standard SATA 3.0 1-Meter Cable ................................................ 132
Figure 73: SDIO 3.0/MMC4.4 Connection to Connector Side ....................................................................... 134
Figure 74: SDIO 3.0/MMC 4.4 Routing Topology .......................................................................................... 135
Figure 75: Clock Transition Examples ........................................................................................................... 138
Figure 76: Master SMI Connectivity Example ................................................................................................ 138
Figure 77: Using Two 8-bit Flash Devices to Comprise a 16-bit Bus ............................................................. 139
Figure 78: Example of a 16-bit Wide Device Connection .............................................................................. 140

88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
Page 3 Document Classification: Public August 30, 2017
Figure 79: Example of a 512 KB Flash Device with an 8-bit Data Bus Connection ....................................... 141
Figure 80: DEV_READYn Connection Example ............................................................................................ 142
Figure 81: Connectivity for Chip Enable Don’t Care NAND Flash ................................................................ 143
Figure 82: Core Clock Connectivity ............................................................................................................... 145
Figure 83: Reference Clock Distribution ........................................................................................................ 146
Figure 84: Clock Topology ............................................................................................................................. 147
Figure 85: Internal Reference Clock with up to 2 PCIe Root Complex Ports ................................................. 148
Figure 86: External Reference Clock with 4 PCIe Root Complex Ports ......................................................... 149
Figure 87: External Reference Clock with 1 PCIe Endpoint and 3 Root Complex Ports ............................... 149
Figure 88: Internal Reference Clock Topology with 4 PCIe Root Complex Ports .......................................... 150
Figure 89: Internal Reference Clock Topology with 1 PCIe Endpoint and 3 Root Complex Ports ................. 150
Figure 90: Board Connectivity for VDD_CPU with Direct AVS Feedback Connection ................................. 152
Figure 91: Board Connectivity for VDD_CPU with AVS Feedback Connection with Resistor Voltage
Divider Regulator ..........................................................................................................................152

List of Tables
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 1
List of Tables
Table 1: Revision History ................................................................................................................................ 3
Table 1: Related Documents .......................................................................................................................... 3
Table 2: 4-Layer Stack Up Example ............................................................................................................... 5
Table 3: List of Capacitors .............................................................................................................................. 8
Table 4: Definition of Analog Power Filter Symbols ...................................................................................... 33
Table 5: Signal Groups ................................................................................................................................. 40
Table 6: Routing Constraints when Using On Board 16-bit, 1x16-bit Wide Memory Topology —
Address and Control Using a Clamshell Assembly .........................................................................46
Table 7: Routing Constraints—On-Board 16-bit, 2x8-bit Topology ............................................................... 50
Table 8: Routing Constraints when Using On Board 16-bit, 4x8-bit Wide Memory Topology Using a
Clamshell Assembly .......................................................................................................................53
Table 9: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select ............................................................. 55
Table 10: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly ............. 55
Table 11: Signal Groups ................................................................................................................................. 56
Table 12: Routing Constraints—32-bit, 2x16-bit Single Side Assembly Topology ......................................... 63
Table 13: Routing Constraints—On-Board 32-bit with or without ECC, 4x8-bit Topology .............................. 68
Table 14: Routing Constraints—On-Board 32-bit with or without ECC, 8x8-bit Clamshell Topology ............. 71
Table 15: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select ............................................................. 73
Table 16: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly ............. 74
Table 17: Signal Groups ................................................................................................................................. 75
Table 18: Routing Constraints—On-Board 32-bit with or without ECC, 4x8-bit Topology .............................. 82
Table 19: ODT Control Matrix for SDRAM DDR4 with 1 Chip Select ............................................................. 84
Table 20: Signal Groups ................................................................................................................................. 86
Table 21: No Internal Delay on Transmitting or on Receiving Peer Side—Tx Path ........................................ 88
Table 22: Internal Delay on Transmitting or on Receiving Peer Side—Tx Path ............................................. 89
Table 23: No Internal Delay on Receiving or on Transmitting Peer Side—Rx Path ....................................... 89
Table 24: Internal Delay on Receiving or on Transmitting Peer Side—Rx Path ............................................. 90
Table 25: Signal Groups ................................................................................................................................. 91
Table 26: Routing Constraints Chip-to-Chip, End-to-End Connection ............................................................ 92
Table 27: Signal Groups ................................................................................................................................. 95
Table 28: Routing Constraints for a Chip-to-Chip End-to-End Connection ..................................................... 96
Table 29: Signal Groups ................................................................................................................................. 99
Table 30: Routing Constraints for a Chip-to-Chip End-to-End Connection Topology ................................... 100
Table 31: Signal Groups ............................................................................................................................... 103
Table 32: Specific Device ............................................................................................................................ 103
Table 33: System Board with Existing Connector ......................................................................................... 106
Table 34: Add-in Card ................................................................................................................................... 107
Table 35: Same-Board Connection .............................................................................................................. 108
Table 36: Signal Groups ............................................................................................................................... 111
Table 37: Specific Device ............................................................................................................................. 111

88F6810, 88F6820 and 88F6828
Hardware Design Guide
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Table 38: System Board with Existing Connector ......................................................................................... 114
Table 39: Add-in Card ................................................................................................................................... 116
Table 40: Same-Board Connection .............................................................................................................. 117
Table 41: USB Interface Pin Connectivity Groups ........................................................................................ 120
Table 42: Routing Constraints when Configured as a Device ..................................................................... 122
Table 43: Routing Constraints when Configured as a Host ..........................................................................124
Table 44: USB Interface Pin Connectivity Groups ........................................................................................ 126
Table 45: Routing Constraints when Configured as a Device ...................................................................... 127
Table 46: Topology—Including Optional Common Mode Choke and Protection Diodes Circuitry—
when Configured as a Host ..........................................................................................................129
Table 47: Signal Groups ............................................................................................................................... 131
Table 48: Connection to a Standard SATA 3.0 1-Meter Cable ..................................................................... 132
Table 49: Signal Groups ............................................................................................................................... 134
Table 50: Routing Constraints for SDIO 3.0 and MMC 4.4 Interfaces .......................................................... 135
Table 51: Core Clock Tx/Rx Path Constraints .............................................................................................. 145

Introduction
Relevant Devices
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 3
Introduction
This hardware design guide is provided by Marvell®for board designs that use the 88F6810,
88F6820 and 88F6828 devices. It provides designers with guidelines and design rule
recommendations.
If the guidelines listed in this document are not followed, it is important to perform thorough signal
integrity and timing simulations for the design. This will ensure proper signal integrity and timing. Any
deviation from the guidelines should be simulated.
For full hardware specifications, refer to the specific device’s Hardware Specifications document.
In this document, the 88F6810, 88F6820 and 88F6828 are often referred to as the “device”.
Refer to the 88F6810, 88F6820 and 88F6828 reference design layout files as the best practice for
board editing and layout options. Pay close attention to sensitive interfaces such as power, DDR,
SERDES, and clock routing.
Relevant Devices
This document is relevant for the following devices:
88F6810
88F6820
88F6828
Related Documents
The following documents contain additional information related to the 88F6810, 88F6820 and
88F6828.
See the Marvell Extranet website for the latest product documentation.
Note
This revision is based on simulations prior to actual silicon testing. The information
may change in future revisions, based on silicon testing.
Refer to the respective device Hardware Specifications for the precise pin names
and bus lengths.
Some features may not be supported in the initial stepping of the device.
Table 1: Related Documents
Title Document
Number
88F6810, 88F6820 and 88F6828 Marvell®ARMADA®38x Family
High-Performance Single/Dual Core CPU System on Chip Functional
Specifications
MV-S109094-00
88F6810, 88F6820 and 88F6828 Marvell®ARMADA®38x Family
High-Performance Single/Dual CPU System-on-Chip Hardware
Specifications
MV-S108817-00

88F6810, 88F6820 and 88F6828
Hardware Design Guide
Doc. No. MV-S302310-U0 Rev. A Copyright © 2017 Marvell
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AN-216 EMI Guidelines MV-S300935-00
Table 1: Related Documents (Continued)
Title Document
Number

4-Layer Board Recommendations
Stack-Up Example
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 5
1 4-Layer Board Recommendations
This section provides board design recommendations for routing signals on a 4-layer PCB board,
and are based on the Marvell®88F682x device and on simulations that were implemented and
verified on a development board. These recommendations relate to the following topics:
Board stack up
Layout
Power
1.1 Stack-Up Example
Marvell®highly recommends designing a board layer stack up with impedance matching as close as
possible to the specific interface guidelines values.
Table 2 provides a 4-layer stack-up example based on the Marvell®reference design. It is the
customers responsibility to achieve signal impedance matching on their system.
Table 2: 4-Layer Stack Up Example
Layer Layer Name Thickness Width
(Space/Conductor/
Space)
(mil)
Signal Impedance
1Component Side
(Top)
1.5 oz
(2.1 mil)
5/5/5 Differential: 85
Single-ended: 53.4
5/12/5 Differential: 100
Single-ended: 53.4
6.3/12/6.3 Differential: 90
Single-ended: 48.4
Pre-preg 4.0 mil
2 L2 (ref. plan) 1.0 oz
(1.4mil)
Core 47 mil
3 L3 (ref plan) 1.0 oz
(1.4 mil)
Pre-preg 4.0 mil

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Hardware Design Guide
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1.2 General Guidelines
The 88F68xx device family was designed to allow usage of low cost technologies, such as 5 mil
traces and standard via diameters.
1.2.1 Board Escaping Methodology
This subsection provides escaping methodologies that apply to the TFBGA 17x17 mm package
devices. Following this methodology will allow the connection of the peripheral devices to these
Marvell®devices using a minimum number of layers. The following subsections describes the
device pinout structure and provides escaping examples that are relevant for all external interfaces.
Marvell recommends following these examples to ensure successful board design.
1.2.2 General Escape Routing Methodology
A general escape routing methodology is presented to support a 4-layer signal design, taking into
account the ball size, pitch, trace width, and trace spacing constraints.
This section provide guide lines for general trace routing.
The following sections provides escape routing methodology for specific interfaces (SDRAM,
SERDES, Clocks and IO’s) for both the top and bottom layer.
1.2.2.1 Escape Area
The escape area is a bounded area around the device.
The escape area is defined as 100 mils for the SDRAM interface area and 200 mils for all other
signals areas from the outer ball row of the device
4Print Side
(Bottom)
1.5 oz
(2.1mil)
5/5/5 Differential: 85
Single-ended: 53.4
5/12/5 Differential: 100
Single-ended: 53.4
6.3/12/6.3 Differential: 90
Single-ended: 48.4
NOTE:
• Via drill 10 mil, pad 20 mil, and anti pad 30 mil.
• The impedance was calculated with Er = 4. These values may vary depending on the
board manufacturer.
• Board Thickness = 1.6 mm
• Board Tolerance = ±10% (including plating and solder mask + ink)
Table 2: 4-Layer Stack Up Example (Continued)
Layer Layer Name Thickness Width
(Space/Conductor/
Space)
(mil)
Signal Impedance
Note
Pay special attention to the different ball patterns and how to route the traces to them.
Refer to the specific interface sections below for the recommended pin pattern breakout
methodology.

4-Layer Board Recommendations
88F6810, 88F6820 and 88F6828 Power Filtering
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
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Within the escape area, some of the layout guidelines may be compromised due to escape
considerations. For example, the recommended separation and trace width may not be feasible
within the escape area and may be compromised for this short escape distance.
Traces outside the escape area should be routed with the proper trace width and separation as
required by the board and as defined by the specific interface guidelines.
1.2.2.2 GND Guard Bands Guidelines
When routing the SERDES lanes on the outer layers (top or bottom), Marvell® recommends using
GND guard bands around the SERDES traces.
Provide at least 3 GND vias per inch on the GND guard bands.
Provide separation between the GND via and the adjacent signal of at least 3 times the distance
from the adjacent reference plane (the distance from the signal to its GND).
Place GND vias at the edges of the GND guard band plane.
Provide separation between adjacent SERDES pairs of at least 10 times the distance from
adjacent reference plane (the distance from the lane to its reference GND/power).
The differential pairs of the SERDES lines must be tightly coupled.
A minimum of 40 mil separation must be maintained between USB2.0 traces to other SERDES
traces.
1.3 88F6810, 88F6820 and 88F6828 Power Filtering
These high speed devices use high frequency clocks, with internal PLLs, to sustain an accurate
internal clock from the externally supplied clock.
To achieve and maintain a stable internal clock with minimal jitter, the following analog power pins
require quiet and stable power supplies:
CPU_PLL_AVDD
USB_AVDD
USB_AVDDL
SRD_AVDD
Note
For detailed PLL power supply filtering requirements, see Section 3.4, Analog Power
Filtering .

88F6810, 88F6820 and 88F6828
Hardware Design Guide
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1.3.1 Power Supply Decoupling
Table 3 lists the power domains, and shows the recommended number of decoupling capacitors and
vias per power rail to achieve good quality power decoupling and connectivity.
1.4 Routing Guidelines for the ISET Signal
Follow these guidelines for the interface ISET signal placement:
Place the ISET resistor up to 400 mil from the ISET pin.
For resistor parameters, refer to the Hardware Specifications.
1.5 Board Recommendations for Stripline Routing PCB
Break-out on the top layer where possible and place vias close to the device. Make sure to maintain
low crosstalk between vias.
Table 3: List of Capacitors
Power Domain Number
of Balls
Number
of Vias
Number of
Decoupling
Capacitors
Capacitor Value
VDD 15 13 8 1 x 22 nF
2 x 33 nF
5 x 220 nF
VDDO_M 13 20 7 100 nF
CPU_PLL_AVDD,
SRD_AVDD, USB_AVDDL
4 4 3 100 nF
VDDO_A, VDDO_B
VDDO_C, VDDO_D,
VDDO_E
11 9 11 100 nF
USB_AVDD 1 1 1 100 nF
RTC_AVDD 1 1 1 100 nF

Generic Guidelines for SERDES Interfaces
Insertion Loss and Loss Budget
Copyright © 2017 Marvell Doc. No. MV-S302310-U0 Rev. A
August 30, 2017 Document Classification: Public Page 9
2Generic Guidelines for SERDES
Interfaces
This section presents the generic design and routing guidelines for differential pairs of serial
interfaces. While the interface protocols vary, many of the electrical aspects are similar in most
high-speed serial differential interfaces.
This generic section refers to both BGA/QFP1packages and some of information may be irrelevant
to the package type used in a specific device. Some references to the package type can refer to
other chips that are on the board.
This section addresses the following issues that must be dealt with to ensure a robust, high-speed
serial interface board design:
Insertion Loss and Loss Budget
Inter-Symbol Interference (ISI)
Placement of Devices and Connectors on the Board
PCB Materials Selection
Crosstalk
Return Path Continuity
Target Routing Impedance
Capacitive Discontinuities
Selecting the Appropriate Components
Trace Symmetry and Matching—Mode Conversion
Via Structures
Every sub-section includes two parts. The first part provides theoretical background and motivation,
and the second part contains the actual design recommendations.
2.1 Insertion Loss and Loss Budget
In this section, the term insertion loss is referred to as the overall signal quality degradation factors
(not just to skin effect, dielectric loss, and surface roughness).
The insertion loss versus frequency curve describes the attenuation of the signal per frequency, in
terms of amplitude and phase. It is generally acceptable to measure the insertion amplitude loss
curve in units of dB - Insertion loss [dB] = 20 log (V far-end out/ V near-end in). For high-speed serial
interfaces, the differential insertion loss is usually measured, as it describes the attenuation of a
differential signal.
Most high-speed serial differential electrical specifications define the maximum allowed insertion
loss of specific sections of the system. This definition is referred to as insertion loss budget and is
usually defined in terms of differential insertion loss at predefined frequency points. The initial
1. Refer to the device Hardware Specifications to determine the device package type.
Note
If there is a mis-correlation between the data presented in this Generic Guidelines for
SERDES Interfaces section and data presented in a specific interface design guidelines
section, the rule to comply to is the data presented in the specific interface section.

88F6810, 88F6820 and 88F6828
Hardware Design Guide
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parameter to check, when designing a high-speed serial interface board, is the specific interface loss
budget.
The insertion loss and loss budget refer to the degradation of a high-speed signal propagating
through a printed circuit board trace or a stacking cable. The loss is mainly affected by:
Material and geometrical dimensions effects:
•Skin effect
•Dielectric loss
•Copper surface roughness
Other signal integrity effects: Impedance mismatches and discontinuities
To allow an end-to-end reliable link operating at a desired bit error rate (BER), the receiver sensitivity
and jitter tolerance characteristics requirements can be determined by the following—all of which will
determine the eye pattern at the receiver:
The transmitter eye characteristics
The interconnect loss characteristics
Crosstalk characteristics: The crosstalk effect for loss budget calculation is explained in
Section 2.5, Crosstalk.
Impedance mismatches, including manufacturing tolerance
Other disturbances such as RFI
It is important to have a smooth insertion-loss curve shape over the desired frequency range.
Notch-like behavior should be avoided (see Figure 1). Notch-like behavior indicates a major phase
shift of the insertion loss at the specific frequency. Phase changes between different signal symbols
can be a major contributor to jitter.
Figure 1: Insertion Loss Curve
Frequency
Differential insertion loss
Notch-like
behavior
Smooth
behavior
Fbaud/2
Fbaud/10
[Sdd]