Marvell Integrated Controller 88F6281 User manual

Marvell. Moving Forward Faster
Doc. No. MV-S104859-U0, Rev. E
December 2, 2008, Preliminary
Document Classification: Proprietary Information
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88F6281
Integrated Controller
Hardware Specifications

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88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 2 Document Classification: Proprietary Information December 2, 2008, Preliminary

88F6281
Integrated Controller
Hardware Specifications
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 3
PRODUCT OVERVIEW
The Marvell®88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell
proprietary, ARMv5TE-compliant, high-speed Sheeva™CPU core. The CPU core integrates a 256 KB L2 cache.
Sheeva™ CPU Core
16 KB-I, 16 KB-D
Up to 1.5 GHz
AES/DES/
3DES SHA-1/MD5
Processor
Memory
Security Engine
L2
Cache
256 KB
DDR
SDRAM
Controller
JTAG Interface PCI Express
SATA
USB 2.0
High Speed I/0
PCI Express x1
Dual SATA ports
USB 2.0 port
88F6281 Functional Block Diagram
External DDR
800 MHz
Misc
FXS / FXO
SPI, NAND, SDIO
Slow Bus
TDM
UART x2
GPIO, TWSI
Flash, SDIO
4 XOR/DMA channels
XOR Engine
Internal Bus
Gigabit Ethernet
IEEE 1588AVB support
GE
GE
MPEG2-TS
I2S / S/PDIF
Media Interfaces
MPEG TS
Audio

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 4 Document Classification: Proprietary Information December 2, 2008, Preliminary
FEATURES
The 88F6281 includes:
•High-performance CPU core, running at up to
1.5 GHz, with integrated, four-way, set-associative
L1 16-KB I-cache/16-KB D-cache and unified,
256-KB, four-way, set-associative L2 cache
•High-bandwidth dual-port DDR2 memory interface
(16-bit DDR2 SDRAM @ up to 800 MHz data rate)
•PCI Express (x1) port with integrated PHY
•Two Gigabit Ethernet (10/100/1000 Mbps) MACs
•USB 2.0 port with integrated PHY
•Two SATA 2.0 ports with integrated 3 Gbps SATA II
PHY
•Security Cryptographic engine
•S/PDIF (Sony/Philips Digital Interconnect Format) /
I2S (Integrated Interchip Sound) Audio in/out
interface
•SD/SDIO/MMC interface
•TDM SLIC/SLAC Codec interface
•Two XOR engines, each containing two XOR/DMA
channels (a total of four XOR/DMA channels)
•MPEG Transport Stream (TS) interface
•SPI port with SPI flash boot support
•8-bit NAND flash interface with boot support
•Two 16550 compatible UART interfaces
•TWSI port
•50 multi-purpose pins
•Internal Real Time Clock (RTC)
•Interrupt controller
•Timers
•128-bit eFuse (one-time programmable memory)
Sheeva™CPU core
•Up to 1.5 GHz
•32-bit and 16-bit RISC architecture
•Compliant with v5TE architecture, as published in
the ARM Architect Reference Manual, Second
Edition
•Includes MMU to support virtual memory features
•256-KB, four-way, set-associative L2 unified cache
•16-KB, four-way, set-associative I-cache
•16-KB, four-way, set-associative D-cache
•64-bit internal data bus
•Branch Prediction Unit
•Supports JTAG/ARM ICE
•Supports both Big and Little Endian modes
DDR2 SDRAM controller
•16-bit interface
•Up to 400 MHz clock frequency (800 MHz data
rate)
•DDR SDRAM with a clock ratio of 1:N and 2:N
between the DDR SDRAM and the CPU core,
respectively
•SSTL 1.8V I/Os
•Auto calibration of I/Os output impedance
•Supports four DRAM chip selects
•Supports all DDR devices densities up to 2 Gb
•Supports up to 32 open pages (page per bank)
•Up to 2 GB total address space
•Supports on-board DDR designs (no DIMM
support)
•Supports 2T mode, to enable high-frequency
operation under heavy load configuration
•Supports DRAM bank interleaving
•Supports up to a 128-byte burst per single memory
access
PCI Express interface (x1)
•PCI Express Base 1.1 compatible
•Integrated low-power SERDES PHY, based on
proven Marvell®SERDES technology
•Serves as a Root Complex or an Endpoint port
•x1 link width
•2.5 Gbps data rate
•Lane polarity reversal support
•Maximum payload size of 128 bytes
•Single Virtual Channel (VC-0)
•Replay buffer support
•Extended PCI Express configuration space
•Advanced Error Reporting (AER) support
•Power management: L0s and software L1 support
•Interrupt emulation message support
•Error message support
PCI Express master specific features
•Single outstanding read transaction
•Maximum read request of up to 128 bytes
•Maximum write request of up to 128 bytes
•Up to four outstanding read transactions in
Endpoint mode
PCI Express target specific features
•Supports up to eight read request transactions
•Maximum read request size of 4 KB
•Maximum write request of 128 bytes
•Supports PCI Express access to all of the
controller’s internal registers
Two Integrated GbE (10/100/1000) MAC ports
•Supports 10/100/1000 Mbps
•Dedicated DMA for data movement between
memory and port

Features
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 5
•Priority queuing on receive based on Destination
Address (DA), VLAN Tag, and IP TOS
•Layer 2/3/4 frame encapsulation detection
•TCP/IP checksum on receive and transmit
•Supports proprietary 200 Mbps Marvell MII (MMII)
interface
•Supports four modes:
-Port 0 RGMII, Port 1 RGMII
-Port 0 RGMII, Port 1 MII/MMII
-Port 0 MII/MMII, port 1 RGMII
-Port 0 GMII, Port 1 N/A
•DA filtering
Precise Timing Protocol (PTP)
•Supports precise time stamping for packets, as
defined in IEEE 1588 PTP v1 and v2 and IEEE
802.1AS draft standards
•Supports Flexible Time Application interface to
distribute PTP clock and time to other devices in
the system
•Optionally accepts an external clock input for time
stamping
Audio Video Bridging networks
•Supports IEEE 802.1Qav draft Audio Video
Bridging networks
•Supports time- and priority-aware egress pacing
algorithm to prevent bunching and bursting
effects—suitable for audio/video applications
•Supports Egress Jitter Pacer for AVB-Class A and
AVB-Class B traffic and strict priority for legacy
traffic queues
USB 2.0 port
•Serves as a peripheral or host
•USB 2.0 compliant
•Integrated USB 2.0 PHY
•Enhanced Host Controller Interface (EHCI)
compatible as a host
•As a host, supports direct connection to all
peripheral types (LS, FS, HS)
•As a peripheral, connects to all host types (HS, FS)
and hubs
•Up to four independent endpoints, supporting
control, interrupt, bulk, and isochronous data
transfers
•Dedicated DMA for data movement between
memory and port
Two Integrated Marvell 3 Gbps (Gen2i) SATA PHYs
•Compliant with SATA II Phase 1 specifications
-Supports SATA II Native Command Queuing
(NCQ), up to 128 outstanding commands per
port
-Fully supports first party DMA (FPDMA)
-Backwards compatible with SATA I devices
•Supports SATA II Phase 2 advanced features
-3 Gbps (Gen2i) SATA II speed
-Port Multiplier (PM)—Performs FIS-based
switching, as defined in SATA working group PM
definition
-Port Selector (PS)—Issues the protocol-based
Out-Of-Band (OOB) sequence for selecting the
active host port
•Supports device 48-bit addressing
•Supports ATA Tag Command Queuing
SATA II Host Controller
•Enhanced-DMA (EDMA) for the SATA ports
•Automatic command execution, without host
intervention
•Command queuing support, for up to 32
outstanding commands
•Separate SATA request/response queues
•64-bit addressing support for descriptors and data
buffers in system memory
•Read ahead
•Advanced interrupt coalescing
•Target mode operation—supports attaching two
88F6281 controllers through their Serial-ATA ports,
enabling data communication between the
88F6281 controllers
•Advanced drive diagnostics via the ATA SMART
command
Cryptographic engine
•Hardware implementation on encryption and
authentication engines, to boost packet processing
speed
•Dedicated DMA to feed the hardware engines with
data from the internal SRAM memory or from the
DDR memory
•Implements AES, DES, and 3DES encryption
algorithms
•Implements SHA1 and MD5 authentication
algorithms
S/PDIF / I2S Audio In/Out interface
•Either S/PDIF or I2S inputs can be active at one
time
•Both S/PDIF and I2S outputs can be
simultaneously active, transferring the same PCM
data
S/PDIF-specific features
•Compliant with 60958-1, 60958-3, and IEC61937
specifications
•Sample rates of 44.1/48/96 kHz
•16/20/24-bit depths

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 6 Document Classification: Proprietary Information December 2, 2008, Preliminary
I2S-specific features
•Sample rates of 44.1/48/96 kHz
•I2S input and I2S output operate at the same
sample rate
•16/24-bit depths
•I2S in and I2S out support independent bit depths
(16 bit/24 bit)
•Supports plain I2S, right-justified and left-justified
formats
SD/SDIO/MMC host interface
•1-bit/4-bit SDmem, SDIO, and MMC cards
•Up to 50 MHz
•Hardware generate/check CRC, on all command
and data transactions on the card bus
TDM SLIC/SLAC Codec interface
•Generic interface to standard SLIC/SLAC codec
devices
•Compatible with standard PCM highway formats
•TDM protocol support for two channels, up to
128 time slots
•Dedicated SPI interface for codec management
•Integrated DMA to transfer voice data to/from
memory buffer
Two XOR engines and DMA
•Two XOR/DMA channels per XOR engine (for a
total of four XOR/DMA channels)
•Chaining via linked-lists of descriptors
•Moves data from source interface to destination
interface
•Supports increment or hold on both Source and
Destination Addresses
•Supports XOR operation, on up to eight source
blocks—useful for RAID applications
•Supports iSCSI CRC-32 calculation
NAND flash controller
•8-bit NAND flash interface
•Glueless interface to CE Care and CE Don’t Care
NAND flash devices
•Boot support
Serial Peripheral Interface (SPI) controller
•Up to 50 MHz clock
•Supports direct boot from external SPI serial flash
memory
MPEG Transport Stream (TS) interface
•ISO/IEC 13818-1 standard compliant
•Supports any one of the following modes:
-Parallel (8 bit) input
-Parallel output
-Two independent serial interfaces
•Data rate up to 80 Mbps
Two UART Interfaces
•16550 UART compatible
•Two pins for transmit and receive operations
•Two pins for modem control functions
Two-Wire Serial Interface (TWSI)
•General purpose TWSI master/slave port
•Can also be used for serial ROM initialization
50 dedicated Multi-Purpose Pins (MPPs) for
peripheral functions and general purpose I/O
•Each pin can be configured independently.
•GPIO inputs can be used to register interrupts from
external devices, and to generate maskable
interrupts.
•Only two of the following multiplexed interfaces
may be configured simultaneously:
-Audio
-TS
-TDM
-GbE Port 0 in GMII mode or GbE Port 1
Interrupt Controller
Maskable interrupts to CPU core
(and PCI Express for a PCI Express endpoint)
Two general purpose 32-bit timers/counters
Internal architecture
•Mbus-L bus for high-performance, low-latency CPU
core to DDR SDRAM connectivity
•Advanced Mbus architecture
•Dual port DDR SDRAM controller connectivity to
both CPU and Mbus
Bootable from
•SPI flash
•SATA device
•NAND flash
•PCI Express
•UART (for debug purpose)
288-pin HSBGA package, 19 x 19 mm, 1 mm ball
pitch

Features
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December 2, 2008, Preliminary Document Classification: Proprietary Information Page 7
x16
x8
TDM
Usage Model Example: VoIP Gateway
PCI Express
Mini Card Wi-Fi
SD Card
USB Host
SATA Port
Multiplier HDD
Audio
A/D – D/A GbE PHY FXS FXO
NAND Flash
SPI Flash (op.)
On Board DDR2
88F6281

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 8 Document Classification: Proprietary Information December 2, 2008, Preliminary
Table of Contents
Product Overview.......................................................................................................................................3
Features.......................................................................................................................................................4
Preface.......................................................................................................................................................15
About this Document.......................................................................................................................................15
Related Documentation...................................................................................................................................15
Document Conventions...................................................................................................................................16
1 Pin and Signal Descriptions.......................................................................................................17
1.1 Pin Logic .........................................................................................................................................................18
1.2 Pin Descriptions ..............................................................................................................................................19
1.3 Internal Pull-up and Pull-down Pins................................................................................................................48
2 Unused Interface Strapping........................................................................................................49
3 88F6281 Pin Map and Pin List ....................................................................................................50
4 Pin Multiplexing...........................................................................................................................51
4.1 Multi-Purpose Pins Functional Summary........................................................................................................51
4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP..........................................................................................57
4.3 TSMP (TS Multiplexing Pins) on MPP.............................................................................................................59
5 Clocking .......................................................................................................................................60
5.1 Spread Spectrum Clock Generator (SSCG)....................................................................................................62
6 System Power Up/Down and Reset Settings............................................................................63
6.1 Power-Up/Down Sequence Requirements......................................................................................................63
6.2 Hardware Reset ..............................................................................................................................................64
6.3 PCI Express Reset..........................................................................................................................................66
6.4 Sheeva™CPU TAP Controller Reset..............................................................................................................66
6.5 Pins Sample Configuration..............................................................................................................................66
6.6 Serial ROM Initialization..................................................................................................................................70
6.7 Boot Sequence................................................................................................................................................71
7 JTAG Interface.............................................................................................................................73
7.1 TAP Controller.................................................................................................................................................73
7.2 Instruction Register .........................................................................................................................................73
7.3 Bypass Register..............................................................................................................................................74
7.4 JTAG Scan Chain ...........................................................................................................................................74
7.5 ID Register ......................................................................................................................................................74

Table of Contents
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 9
8 Electrical Specifications (Preliminary) ......................................................................................75
8.1 Absolute Maximum Ratings ............................................................................................................................75
8.2 Recommended Operating Conditions.............................................................................................................77
8.3 Thermal Power Dissipation .............................................................................................................................79
8.4 Current Consumption......................................................................................................................................80
8.5 DC Electrical Specifications............................................................................................................................81
8.6 AC Electrical Specifications ............................................................................................................................86
8.7 Differential Interface Electrical Characteristics..............................................................................................118
9 Thermal Data (Preliminary).......................................................................................................129
10 Package......................................................................................................................................130
11 Part Order Numbering/Package Marking ................................................................................132
11.1 Part Order Numbering...................................................................................................................................132
11.2 Package Marking ..........................................................................................................................................133
A Revision History ........................................................................................................................134

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 10 Document Classification: Proprietary Information December 2, 2008, Preliminary
List of Tables
1 Pin and Signal Descriptions ............................................................................................................17
Table 1: Pin Functions and Assignments Table Key ......................................................................................19
Table 2: Interface Pin Prefix Codes................................................................................................................19
Table 3: Power Pin Assignments....................................................................................................................21
Table 4: Miscellaneous Pin Assignments.......................................................................................................23
Table 5: DDR SDRAM Interface Pin Assignments .........................................................................................24
Table 6: PCI Express Interface Pin Assignments...........................................................................................26
Table 7: SATA Port Interface Pin Assignment................................................................................................27
Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments .......................................................................28
Table 9: Serial Management Interface (SMI) Pin Assignments......................................................................32
Table 10: USB 2.0 Interface Pin Assignments..................................................................................................33
Table 11: JTAG Pin Assignment.......................................................................................................................34
Table 12: RTC Interface Pin Assignments........................................................................................................35
Table 13: NAND Flash Interface Pin Assignment.............................................................................................36
Table 14: MPP Interface Pin Assignment.........................................................................................................37
Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment............................................................38
Table 16: UART Port 0/1 Interface Pin Assignment .........................................................................................39
Table 17: Audio (S/PDIF / I2S) Interface Signal Assignment............................................................................40
Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment .........................................................41
Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................42
Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................43
Table 21: Transport Stream (TS) Interface Signal Assignment........................................................................45
Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment............................................................47
Table 23: Internal Pull-up and Pull-down Pins..................................................................................................48
2 Unused Interface Strapping.............................................................................................................49
Table 24: Unused Interface Strapping..............................................................................................................49
3 88F6281 Pin Map and Pin List .........................................................................................................50
4 Pin Multiplexing ................................................................................................................................51
Table 25: MPP Functionality.............................................................................................................................52
Table 26: MPP Function Summary...................................................................................................................53
Table 27: Ethernet Ports Pins Multiplexing.......................................................................................................57
Table 28: TS Port Pin Multiplexing .................................................................................................................59
5 Clocking.............................................................................................................................................60
Table 29: 88F6281Clocks.................................................................................................................................60
Table 30: Supported Clock Combinations........................................................................................................61
6 System Power Up/Down and Reset Settings .................................................................................63
Table 31: I/O and Core Voltages......................................................................................................................63
Table 32: Reset Configuration..........................................................................................................................67

List of Tables
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 11
7 JTAG Interface ..................................................................................................................................73
Table 33: Supported JTAG Instructions............................................................................................................73
Table 34: IDCODE Register Map .....................................................................................................................74
8 Electrical Specifications (Preliminary) ...........................................................................................75
Table 35: Absolute Maximum Ratings..............................................................................................................75
Table 36: Recommended Operating Conditions...............................................................................................77
Table 37: Thermal Power Dissipation...............................................................................................................79
Table 38: Current Consumption........................................................................................................................80
Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................81
Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications.............................................................82
Table 41: SDRAM DDR2 Interface DC Electrical Specifications......................................................................83
Table 42: TWSI Interface 3.3V DC Electrical Specifications.............................................................................84
Table 43: SPI Interface 3.3V DC Electrical Specifications................................................................................84
Table 44: TDM Interface 3.3V DC Electrical Specifications..............................................................................85
Table 45: Reference Clock AC Timing Specifications ......................................................................................86
Table 46: SDRAM DDR2 Interface AC Timing Table .......................................................................................88
Table 47: SDRAM DDR2 Interface Address Timing Table...............................................................................89
Table 48: SDRAM DDR2 Clock Specifications.................................................................................................90
Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V ..................................................................................93
Table 50: RGMII 10/100 AC Timing Table at 3.3V ...........................................................................................93
Table 51: GMII AC Timing Table ......................................................................................................................95
Table 52: MII/MMII MAC Mode AC Timing Table.............................................................................................97
Table 53: SMI Master Mode AC Timing Table..................................................................................................99
Table 54: JTAG Interface AC Timing Table....................................................................................................101
Table 55: TWSI Master AC Timing Table.......................................................................................................103
Table 56: TWSI Slave AC Timing Table.........................................................................................................103
Table 57: S/PDIF AC Timing Table ................................................................................................................105
Table 58: Inter-IC Sound (I2S) AC Timing Table............................................................................................107
Table 59: TDM Interface AC Timing Table .....................................................................................................109
Table 60: SPI (Master Mode) AC Timing Table..............................................................................................111
Table 61: SDIO Host in High Speed Mode AC Timing Table .........................................................................113
Table 62: Transport Stream Output Interface AC Timing Table ....................................................................115
Table 63: Transport Stream Input Interface AC Timing Table........................................................................115
Table 64: PCI Express Interface Differential Reference Clock Characteristics ..............................................118
Table 65: PCI Express Interface Spread Spectrum Requirements.................................................................119
Table 66: PCI Express Interface Driver and Receiver Characteristics ...........................................................120
Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics...............................................123
Table 68: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics..............................................124
Table 69: USB Low Speed Driver and Receiver Characteristics....................................................................125
Table 70: USB Full Speed Driver and Receiver Characteristics.....................................................................126
Table 71: USB High Speed Driver and Receiver Characteristics...................................................................127
9 Thermal Data (Preliminary)............................................................................................................129
Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary).............................129

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 12 Document Classification: Proprietary Information December 2, 2008, Preliminary
10 Package ...........................................................................................................................................130
Table 73: HSBGA 288-pin Package Dimensions ...........................................................................................131
11 Part Order Numbering/Package Marking......................................................................................132
Table 74: 88F6281 Part Order Options ..........................................................................................................132
A Revision History .............................................................................................................................134
Table 75: Revision History..............................................................................................................................134

List of Figures
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 13
List of Figures
1 Pin and Signal Descriptions ........................................................................................................... 17
Figure 1: 88F6281 Pin Logic Diagram ............................................................................................................18
2 Unused Interface Strapping............................................................................................................ 49
3 88F6281 Pin Map and Pin List ........................................................................................................ 50
4 Pin Multiplexing ............................................................................................................................... 51
5 Clocking............................................................................................................................................ 60
6 System Power Up/Down and Reset Settings ................................................................................ 63
Figure 2: Power-Up Sequence Example..........................................................................................................64
Figure 3: Serial ROM Data Structure...............................................................................................................70
Figure 4: Serial ROM Read Example...............................................................................................................71
7 JTAG Interface ................................................................................................................................. 73
8 Electrical Specifications (Preliminary) .......................................................................................... 75
Figure 5: SDRAM DDR2 Interface Test Circuit................................................................................................91
Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................91
Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram.................................................92
Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram.........................................................................92
Figure 9: RGMII Test Circuit............................................................................................................................94
Figure 10: RGMII AC Timing Diagram...............................................................................................................94
Figure 11: GMII Test Circuit...............................................................................................................................95
Figure 12: GMII Output AC Timing Diagram......................................................................................................96
Figure 13: GMII Input AC Timing Diagram.........................................................................................................96
Figure 14: MII/MMII MAC Mode Test Circuit......................................................................................................97
Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram...................................................................97
Figure 16: MII/MMII MAC Mode Input AC Timing Diagram................................................................................98
Figure 17: MDIO Master Mode Test Circuit .......................................................................................................99
Figure 18: MDC Master Mode Test Circuit ......................................................................................................100
Figure 19: SMI Master Mode Output AC Timing Diagram ...............................................................................100
Figure 20: SMI Master Mode Input AC Timing Diagram..................................................................................100
Figure 21: JTAG Interface Test Circuit ............................................................................................................101
Figure 22: JTAG Interface Output Delay AC Timing Diagram .........................................................................102
Figure 23: JTAG Interface Input AC Timing Diagram ......................................................................................102
Figure 24: TWSI Test Circuit............................................................................................................................104
Figure 25: TWSI Output Delay AC Timing Diagram.........................................................................................104
Figure 26: TWSI Input AC Timing Diagram .....................................................................................................104
Figure 27: S/PDIF Test Circuit.........................................................................................................................106

88F6281
Hardware Specifications
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Page 14 Document Classification: Proprietary Information December 2, 2008, Preliminary
Figure 28: Inter-IC Sound (I2S) Test Circuit ....................................................................................................107
Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................108
Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................108
Figure 31: TDM Interface Test Circuit..............................................................................................................109
Figure 32: TDM Interface Output Delay AC Timing Diagram...........................................................................110
Figure 33: TDM Interface Input Delay AC Timing Diagram..............................................................................110
Figure 34: SPI (Master Mode) Test Circuit ......................................................................................................111
Figure 35: SPI (Master Mode) Output AC Timing Diagram .............................................................................112
Figure 36: SPI (Master Mode) Input AC Timing Diagram ................................................................................112
Figure 37: Secure Digital Input/Output (SDIO) Test Circuit .............................................................................113
Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram.........................................................114
Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram............................................................114
Figure 40: Transport Stream Interface Test Circuit..........................................................................................116
Figure 41: Transport Stream Output Interface AC Timing Diagram ................................................................116
Figure 42: Transport Stream Input Interface AC Timing Diagram ...................................................................117
Figure 43: PCI Express Interface Test Circuit..................................................................................................121
Figure 44: Low/Full Speed Data Signal Rise and Fall Time ............................................................................127
Figure 45: High Speed TX Eye Diagram Pattern Template.............................................................................128
Figure 46: High Speed RX Eye Diagram Pattern Template.............................................................................128
9 Thermal Data (Preliminary)........................................................................................................... 129
10 Package .......................................................................................................................................... 130
Figure 47: HSBGA 288-pin Package and Dimensions ...................................................................................130
11 Part Order Numbering/Package Marking..................................................................................... 132
Figure 48: Sample Part Number......................................................................................................................132
Figure 49: Commercial Package Marking and Pin 1 Location.........................................................................133

Preface
About this Document
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 15
Preface
About this Document
This datasheet provides the hardware specifications for the 88F6281 integrated controller. The
hardware specifications include detailed pin information, configuration settings, electrical
characteristics and physical specifications.
This datasheet is intended to be the basic source of information for designers of new systems.
In this document, the “88F6281” is often referred to as the “device”.
Related Documentation
The following documents contain additional information related to the 88F6281:
88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications,
Doc No. MV-S104860-U0
Sheeva™88SV131 ARM v5TE Processor Core with MMU and L1/L2 Cache Datasheet,
Doc No. MV-S104950-U0
Unified Layer 2 (L2) Cache for Sheeva™CPU Cores Addendum, Doc No. MV-S104858-U0
88F6180, 88F6190, 88F6192, and 88F6281 Functional Errata, Interface Guidelines, and
Restrictions, Doc No. MV-S501157-U0
88F6180, 88F6190, 88F6192, and 88F6281 Design Guide, Doc No. MV-S301398-001
AN-63: Thermal Management for Marvell Technology Products Doc No. MV-S300281-001
AN-179: TWSI Software Guidelines for Discovery™, Horizon™, and Feroceon®Devices,
Doc No. MV-S300754-001
AN-183: 88F5181 and 88F5281 Big Endian and Little Endian Support,
Doc No. MV-S300767-001
AN-249: Configuring the Marvell®SATA PHY to Transmit Predefined Test Patterns,
Doc No. MV-S301342-001
AN-260 System Power-Saving Methods for 88F6180, 88F6190, 88F6192, and 88F6281,
Doc No. MV-S301454-001
TB-227: Differences Between the 88F6190, 88F6192, and 88F6281 Stepping Z0 and A0,
Doc No. MV-S105223-001
White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Doc No. MV-S700019-00
ARM Architecture Reference Manual, Second Edition
PCI Express Base Specification, Revision 1.1
Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel,
Lucent, Microsoft, NEC, Philips
Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95,
November 2000, Intel Corporation
ARC USB-HS OTG High-Speed Controller Core reference V 4.0.1
Federal Information Processing Standards (FIPS) 46-2 (Data Encryption Standard)
FIPS 81 (DES Modes of Operation)
FIPS 180-1 (Secure Hash Standard)
FIPS draft - Advanced Encryption Standard (Rijndeal)
1. This document is a Marvell proprietary, confidential document, requiring an NDA and can be downloaded from the
Marvell Extranet.

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 16 Document Classification: Proprietary Information December 2, 2008, Preliminary
RFC 1321 (The MD5 Message-Digest Algorithm)
RFC 1851 – The ESP Triple DES Transform
RFC 2104 (HMAC: Keyed-Hashing for Message Authentication).
RFC 2405 – The ESP DES-CBC Cipher Algorithm With Explicit IV
IEEE standard, 802.3-2000 Clause 14
ANSI standard X3.263-1995
See the Marvell Extranet website for the latest product documentation.
Document Conventions
The following conventions are used in this document:
Signal Range A signal name followed by a range enclosed in brackets represents a range of logically related
signals. The first number in the range indicates the most significant bit (MSb) and the last
number indicates the least significant bit (LSb).
Example: DB_Addr[12:0]
Active Low Signals # An n letter at the end of a signal name indicates that the signal’s active state occurs when
voltage is low.
Example: INTn
State Names State names are indicated in italic font.
Example: linkfail
Register Naming
Conventions Register field names are indicated by angle brackets. Example: <RegInit>
Register field bits are enclosed in brackets.
Example: Field [1:0]
Register addresses are represented in hexadecimal format.
Example: 0x0
Reserved: The contents of the register are reserved for internal use only or for future use.
A lowercase <n> in angle brackets in a register indicates that there are multiple registers with
this name.
Example: Multicast Configuration Register<n>
Reset Values Reset values have the following meanings:
0 = Bit clear
1 = Bit set
Abbreviations Kb: kilobit
KB: kilobyte
Mb: megabit
MB: megabyte
Gb: gigabit
GB: gigabyte
Numbering Conventions Unless otherwise indicated, all numbers in this document are decimal (base 10).
An 0x prefix indicates a hexadecimal number.
An 0b prefix indicates a binary number.

Pin and Signal Descriptions
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 17
1Pin and Signal Descriptions
This section provides the pin logic diagram for the 88F6281 device and a detailed description of the
pin assignments and their functionality.

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 18 Document Classification: Proprietary Information December 2, 2008, Preliminary
1.1 Pin Logic
Figure 1: 88F6281 Pin Logic Diagram
NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock.
For details about MPP configuration options see Section 4.1, Multi-Purpose Pins Functional
Summary, on page 51.
Misc.
REF_CLK_XIN
Power
TP
XOUT
SYSRSTn
USB USB_DM
USB_DP
Gigabit Ethernet
GE_TXCLKOUT
GE_TXCTL
GE_TXD[3:0]
GE_RXD[3:0]
GE_RXCTL
GE_RXCLK
GE_MDC
GE_MDIO
SDRAM
M_CLKOUT
M_CLKOUTn
M_CKE
M_RASn
M_CASn
M_WEn
M_A[14:0]
M_BA[2:0]
M_CSn[3:0]
M_DQ[15:0]
M_DQS[1:0]
M_DQSn[1:0]
M_STARTBURST
M_STARTBURST_IN
M_PCAL
M_NCAL
M_DM[1:0]
M_ODT[1:0]
RTC
RTC_XIN
RTC_XOUT
SATA0/1
SATA0_T_P
SATA0_R_P
SATA0_R_N
SATA0_T_N
SATA1_T_P
SATA1_T_N
SATA1_R_P
SATA1_R_N
JTAG
JT_CLK
JT_TDI
JT_TDO
JT_TMS_CORE
JT_RSTn
JT_TMS_CPU
NAND
Flash
NF_CLE
NF_ALE
NF_CEn
NF_REn
NF_WEn
NF_IO[7:0]
MPP
MPP[49:0]
RESERVED
NC
ISET
MRn
CPU_PLL_AVDD
CORE_PLL_AVDD
XTAL_AVDD
SATA0_AVDD
SATA1_AVDD
CPU_PLL_AVSS
CORE_PLL_AVSS
XTAL_AVSS
VDD_M
VSS
VDDO
VDD_CPU
VDD
VDD_GE_A
PEX_AVDD
RTC_AVDD
USB_AVDD
SSCG_AVDD
SSCG_AVSS
RTC_AVSS
VHV
PCI Express PEX_TX_P
PEX_TX_N
PEX_RX_P
PEX_RX_N
PEX_ISET
PEX_CLK_N
PEX_CLK_P
VDD_GE_B

Pin and Signal Descriptions
Pin Descriptions
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 19
1.2 Pin Descriptions
This section details all the pins for the different interfaces providing a functional description of each
pin and pin attributes.
Table 1<Default ¬¹ Font> defines the abbreviations and acronyms used in the pin description tables.
Table 1: Pin Functions and Assignments Table Key
Term Definition
[n] n - Represents the SERDES pair number
<n> Represents port number when there are more than one ports
Analog Analog Driver/Receiver or Power Supply
Calib Calibration pad type
CML Common Mode Logic
CMOS Complementary Metal-Oxide-Semiconductor
DDR Double Data Rate
GND Ground Supply
HCSL High-speed Current Steering Logic
I Input
I/O Input/Output
O Output
o/d Open Drain pin
The pin allows multiple drivers simultaneously (wire-OR connection).
A pull-up is required to sustain the inactive value.
Power VDD Power Supply
SSTL Stub Series Terminated Logic for 1.8V
t/s Tri-State pin
XXXn n - Suffix represents an Active Low Signal
Table 2: Interface Pin Prefix Codes
Interface Prefix
Misc N/A
DDR SDRAM M_
PCI Express PEX_
SATA SATA0_
SATA1_
Gigabit Ethernet GE_
USB 2.0 USB_
JTAG JT_

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 20 Document Classification: Proprietary Information December 2, 2008, Preliminary
RTC RTC_
NAND Flash NF_
MPP N/A
TWSI TW_
UART UA0_
UA1_
Audio AU_
SPI SPI_
SDIO SD_
TDM TDM_
PTP PTP_
Table 2: Interface Pin Prefix Codes (Continued)
Interface Prefix