Marvell GT-64260A Guide

GT-64260A Design Guide
Doc. No. MV-S300165-00, Rev. A
May 21, 2002

Preliminary Information
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Document Status
A d v a n c e d
Information
This datasheet contains design specifications for initial product development. Specifications
may change without notice. Contact Marvell Field Application Engineers for more information.
Preliminary
Information
This datasheet contains preliminary data, and a revision of this document will be published at a
later date. Specifications may change without notice. Contact Marvell Field Application Engi-
neers for more information.
F i n a l
Information
This datasheet contains specifications on a product that is in final release. Specifications may
change without notice. Contact Marvell Field Application Engineers for more information.
Revision Code:
Preliminary Technical Publication: 0.x
Doc. No. MV-S300165-00, Rev. A CONFIDENTIAL Copyright © 2002 Marvell
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May 21, 2002, Preliminary Document Classification: Proprietary Information Page 3
Table of Contents
SECTION 1. INTRODUCTION...................................................................................... 11
1.1 Related Documentation............................................................................................................11
SECTION 2. GT-64260A OVERVIEW ........................................................................ 12
SECTION 3. CPU INTERFACE FUNCTIONAL OVERVIEW ............................................ 14
3.1 CPU Pinout Description ...........................................................................................................14
3.2 60x Bus Mode............................................................................................................................ 17
3.3 MPX Bus Mode ..........................................................................................................................18
3.4 Cache Coherency......................................................................................................................18
3.5 Specific CPUs Aspects.............................................................................................................21
3.6 Multi-GT or Multi-slave Modes.................................................................................................24
3.7 CPU Bus Multiple Masters .......................................................................................................26
3.8 PowerPC COP/JTG Interface ...................................................................................................31
SECTION 4. SDRAM INTERFACE FUNCTIONAL OVERVIEW ....................................... 33
4.1 Pinout Description ...................................................................................................................33
4.2 Memory Connection ................................................................................................................. 35
4.3 SDRAM Address Control..........................................................................................................39
4.4 SDRAM Initialization .................................................................................................................40
4.5 ECC Support.............................................................................................................................. 40
4.6 Memory Banks and Pages .......................................................................................................42
SECTION 5. PCI INTERFACE FUNCTIONAL OVERVIEW .............................................. 46
5.1 P2P Capability ...........................................................................................................................46
5.2 PCI Arbitration........................................................................................................................... 48
5.3 Delayed Read ............................................................................................................................49
5.4 32-bit PCI System......................................................................................................................49
5.5 Cache Coherency......................................................................................................................50
5.6 Message Signaled Interrupt (MSI) ...........................................................................................50

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SECTION 6. DEVICE INTERFACE FUNCTIONAL OVERVIEW ..........................................51
6.1 Device Connection ................................................................................................................... 51
6.2 8-bit Device ............................................................................................................................... 53
6.3 16-bit Device ............................................................................................................................. 55
6.4 32-bit Device ............................................................................................................................. 56
6.5 Signals Timing.......................................................................................................................... 58
6.6 Ready Support.......................................................................................................................... 59
6.7 Syncburst SRAM ...................................................................................................................... 60
SECTION 7. COMMUNICATION INTERFACE FUNCTIONAL OVERVIEW ...........................61
7.1 Ethernet Controllers................................................................................................................. 61
7.2 MPSC Controllers ..................................................................................................................... 62
7.3 Cache Coherency ..................................................................................................................... 62
7.4 MPSC and Ethernet SW Implications ..................................................................................... 63
7.5 I2C Interface .............................................................................................................................. 70
7.6 Baud Rate Generator................................................................................................................ 72
SECTION 8. MULTI-PURPOSE PIN INTERFACE FUNCTIONAL OVERVIEW ......................74
8.1 General Purpose Pin (GPP) ..................................................................................................... 74
8.2 Interrupt Outputs ...................................................................................................................... 75
8.3 PCI Arbiter................................................................................................................................. 76
8.4 DMA Request ............................................................................................................................ 76
8.5 DMA acknowledge.................................................................................................................... 76
8.6 Unified Memory Architecture Control.................................................................................... 77
8.7 DMA End of Transfer............................................................................................................... 77
8.8 Timer Counter Enable ............................................................................................................. 77
8.9 Initialization Active .................................................................................................................. 77
8.10 BRG Clock................................................................................................................................ 77

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SECTION 9. JTAG INTERFACE FUNCTIONAL OVERVIEW............................................ 78
SECTION 10. IDMA UNIT FUNCTIONAL OVERVIEW ..................................................... 79
10.1 Chain Mode................................................................................................................................81
10.2 Cache Coherency......................................................................................................................81
SECTION 11. INTERRUPT CONTROLLER FUNCTIONAL OVERVIEW................................. 82
11.1 Using External Interrupt Controller .........................................................................................86
SECTION 12. MESSAGING UNITS FUNCTIONAL OVERVIEW .......................................... 87
12.1 Messaging.................................................................................................................................87
12.2 Doorbell.....................................................................................................................................87
12.3 Circular Queue .........................................................................................................................88
SECTION 13. DESIGN CONSIDERATION OVERVIEW...................................................... 90
SECTION 14. CPU INTERFACE DESIGN CONSIDERATIONS........................................... 91
14.1 CPU Interface Connectivity ......................................................................................................91
14.2 Electrical Specification.............................................................................................................92
14.3 Termination Topology ..............................................................................................................92
14.4 Timing Requirements ...............................................................................................................92
14.5 Layout Instructions.................................................................................................................104
SECTION 15. SDRAM INTERFACE DESIGN CONSIDERATIONS ................................... 106
15.1 Interface Connectivity.............................................................................................................106
15.2 Electrical Specification..........................................................................................................106
15.3 Termination Topology ............................................................................................................106
15.4 Timing Requirements .............................................................................................................109
15.5 Layout Instructions.................................................................................................................126
SECTION 16. PCI INTERFACE DESIGN CONSIDERATIONS .......................................... 128
16.1 Interface Connectivity.............................................................................................................128
16.2 Electrical Definition.................................................................................................................128

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16.3 Termination Topology............................................................................................................ 128
16.4 Timing Requirements............................................................................................................. 128
16.5 Layout Instructions ................................................................................................................ 133
SECTION 17. ETHERNET INTERFACE DESIGN CONSIDERATIONS.................................134
17.1 Interface Connectivity ............................................................................................................ 134
17.2 Electrical Specification .......................................................................................................... 135
17.3 Termination Topology............................................................................................................ 135
17.4 Timing Requirements............................................................................................................. 135
17.5 Layout Instructions ................................................................................................................ 138
SECTION 18. POWER SUPPLY ..................................................................................140
18.1 De-coupling Recommendations............................................................................................ 140
SECTION 19. CLOCKS..............................................................................................143
SECTION 20. RESET ................................................................................................144
20.1 Reset Configurations ............................................................................................................. 144
SECTION 21. BRINGING UPTHE SYSTEM (DEBUGGING) ............................................145
21.1 Communication Unit .............................................................................................................. 145
SECTION 22. REVISION HISTORY .............................................................................146
APPENDIX A. I2C EEPROM EXAMPLE..................................................................... 147
APPENDIX B. SDRAM MODE REGISTER/CODE ......................................................... 149
APPENDIX C. ECC INITIALIZATION- EXAMPLE CODE ................................................. 150
C.1 Assembler Code150
C.2 C Code Example151
APPENDIX D. BIG AND LITTLE ENDIAN SUPPORT ...................................................... 152
D.1 Internal Register152
D.2 Communication Descriptors152

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D.3 PCI Interface ............................................................................................................................ 153
D.4 Swapping Options................................................................................................................... 153
APPENDIX E. COMMUNICATION EXAMPLE CODE ....................................................... 158
E.1 Ethernet Initialization.............................................................................................................. 158
E.2 Ethernet API............................................................................................................................. 159
E.3 MPSC API................................................................................................................................. 160

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List of Tables
Table 1: CPU Interface Pin Information.............................................................................................................. 14
Table 2: GT-64260A Supported Features in MPX Bus Mode ............................................................................18
Table 3: IDMA Address Base/Top Registers...................................................................................................... 19
Table 4: PCI Address Base/Top Registers......................................................................................................... 20
Table 5: Multi-GT Device ID ............................................................................................................................... 25
Table 6: Multi-GT Mode Transaction Translation ............................................................................................... 26
Table 7: SDRAM Interface Pinout Description ................................................................................................... 33
Table 8: SDRAM Interface Pinout Description ................................................................................................... 35
Table 9: SDRAM Memory Space ....................................................................................................................... 36
Table 10: ECC Bank Selection ............................................................................................................................. 39
Table 11: PCI P2P Configuration Register Initialization Example ....................................................................... 47
Table 12: Internal PCI Arbiter in Multiplexing ....................................................................................................... 48
Table 13: CPU Interface Configuration at Reset .................................................................................................. 91
Table 14: Typical CPU AC Timings ...................................................................................................................... 95
Table 15: Single-GT and Single CPU AC Timing ................................................................................................. 95
Table 16: Single-GT and Multiple CPU AC Timing............................................................................................... 98
Table 17: Multiple GT-64260As and a Single CPU AC Timing .......................................................................... 101
Table 18: Signal Topology Categories ............................................................................................................... 109
Table 19: Trace Length for Data Topologies ...................................................................................................... 114
Table 20: GT-64260A SDRAM Interface AC Timing .......................................................................................... 115
Table 21: Typical SDRAM Interface AC Timing ................................................................................................. 115
Table 23: GT-64260A CS AC Timing ................................................................................................................. 121
Table 24: Typical SDRAM CS AC Timing .......................................................................................................... 121
Table 22: Trace Length for Data Topologies ...................................................................................................... 121
Table 25: Trace Length for Double Cycle Signal Topologies ............................................................................. 124
Table 26: GT-64260A Double Cycle Signals AC Timing .................................................................................... 125
Table 27: Typical SDRAM CS AC Timing .......................................................................................................... 125
Table 28: PCI AC Timing for 33 MHz and 66 MHz (From the PCI Specification Document, Rev. 2.2).............. 129
Table 29: GT-64260A PCI Interface AC Timing ................................................................................................. 129
Table 30: RMII AC timing for 50 MHz (from RMII Specification Rev. 1.2 Document)......................................... 136
Table 31: Ethernet RMII Interface ...................................................................................................................... 136
Table 32: GT-64260A Voltages .......................................................................................................................... 140
Table 33: Revision History.................................................................................................................................. 146
Table 34: Big and Little Endian Bit Ordering ...................................................................................................... 152
Table 35: PCI Big Endian Bit Ordering ............................................................................................................... 153
Table 36: Data Swapping ................................................................................................................................... 154
Table 37: Master Swapping................................................................................................................................ 155
Table 38: Master Swapping (on the SDRAM bus............................................................................................... 156
Table 39: Swapping for All Eight Options ........................................................................................................... 156

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List of Figures
Figure 1: GT-64260A Interfaces ..........................................................................................................................12
Figure 2: Typical GT-64260A System Configuration ...........................................................................................13
Figure 3: PCI Reads from Cache Coherent Regions ..........................................................................................19
Figure 4: PPC750FX CPU Keeper ...................................................................................................................23
Figure 5: Multi-GT System Architecture ..............................................................................................................25
Figure 6: 2 CPUs Connection Through Internal 60x Arbiter ...............................................................................27
Figure 7: Two CPUs Connected Through an External Arbiter.............................................................................28
Figure 8: Interrupt Pins’ Connectivity...................................................................................................................30
Figure 9: CPU to CPU Cache Coherency Data Flow ..........................................................................................30
Figure 10: IBM RISCWatchTM JTAG to HRESET, TRST, and SRESET pin Connector ......................................31
Figure 11: Motorola JTAG to HRESET and TRST pin Connector.........................................................................31
Figure 12: JTAG/COP 16 Pin Connectors.............................................................................................................32
Figure 13: SDRAM Connection for Regular SDRAM/Heavy Load Mode ..............................................................37
Figure 14: SDRAM Connection for Registered SDRAM Mode..............................................................................38
Figure 15: Two Read Interleaving from Different Virtual Banks ..........................................................................43
Figure 16: Single Read Access to Non-open Page ............................................................................................44
Figure 17: Single Read Access to Open Page ...................................................................................................44
Figure 18: Typical P2P System Configuration.......................................................................................................46
Figure 19: I/O P2P Transaction Example ..............................................................................................................47
Figure 20: Three Device Connection Example .....................................................................................................52
Figure 21: 8-bit Device Connection Example .......................................................................................................54
Figure 22: 16-bit Device Connection Example .....................................................................................................55
Figure 23: 32-bit Device Connection Example .....................................................................................................57
Figure 24: Device Burst Read Example ................................................................................................................58
Figure 25: Device Burst Write Example.................................................................................................................59
Figure 26: SCD Pipeline Sync Burst SRAM Read Example ................................................................................60
Figure 27: DCD Pipeline Sync Burst SRAM Read Example ............................................................................60
Figure 28: SDMA Descriptor Format ............................................................................................................63
Figure 29: Rx Descriptor Chain ............................................................................................................................65
Figure 30: Disconnecting the Descriptor Chain .....................................................................................................66
Figure 31: Releasing the Descriptor Chain...........................................................................................................67
Figure 32: GT-64260A I2C Interface Connection to SDRAM DIMMS ..................................................................71
Figure 33: GPP Configured as Input .....................................................................................................................75
Figure 34: MPP Interrupt Outputs..........................................................................................................................76
Figure 35: DMA Controller General Flow ..............................................................................................................80
Figure 36: Interrupt Routing Example....................................................................................................................83
Figure 37: GT-64260A Interrupt Routing Architecture...........................................................................................84
Figure 38: Interrupt Handling Procedure ...............................................................................................................85
Figure 39: External Interrupt Controller .........................................................................................................86
Figure 40: Inbound Circular Queue .......................................................................................................................88
Figure 41: Outbound Circular Queue ....................................................................................................................89
Figure 42: GT-64260A Overshoot/Undershoot Voltage ..................................................................................90
Figure 43: GT-64260A Test Circuit (Cload = 15pf)................................................................................................92

GT-64260A Design Guide
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Figure 44: Test Circuit Results (Cload = 15pf) ..................................................................................................93
Figure 45: GT-64260A Test Circuit (Rload = 50 Ohm) ..........................................................................................94
Figure 46: Test Circuit Results (Rload = 50 Ohm) ................................................................................................94
Figure 47: GT-64260A to CPU Point-to-Point Configuration ...........................................................................95
Figure 48: 1 ns Delay Trace Simulation.................................................................................................................96
Figure 49: 0.8 ns Delay Trace Simulation .............................................................................................97
Figure 50: GT-64260A to Multiple CPU Configuration ..........................................................................................98
Figure 51: 0.5 ns Delay Trace Simulation (Maximum Distance 2.5 Inches) .........................................................99
Figure 52: 0.5 ns Delay Trace Simulation (Maximum Distance 4 Inches) ..........................................................100
Figure 53: Multiple GT-64260As to a Single CPU Configuration.........................................................................101
Figure 54: 1.1 ns Delay Trace Simulation ...........................................................................................................102
Figure 55: 0.8 ns Delay Trace Simulation ...........................................................................................................103
Figure 56: Layout for a Single GT-64260A to a Single CPU ...............................................................................104
Figure 57: Layout for a Single GT-64260A to Multiple CPUs ...........................................................................105
Figure 58: SDRAM Configuration Example .........................................................................................................107
Figure 59: SDRAM Simulation Example ......................................................................................................107
Figure 60: SDRAM Configuration Example (With Resistors) ........................................................................108
Figure 61: SDRAM Simulation Example (With Resistors) .................................................................................109
Figure 62: DIMM Clock Topology .......................................................................................................................111
Figure 63: GT-64260A Data Reference Point......................................................................................................112
Figure 64: SDRAM Data Reference Point ..........................................................................................................113
Figure 65: Selected Memory Configuration Data Topology ............................................................................114
Figure 66: DIMM Connector Package Model ....................................................................................................115
Figure 67: 0.8 ns Delay Trace Simulation (2.1 ns Fly Time Reference Point).....................................................116
Figure 68: 0.8 ns Delay Trace Simulation (1.54 ns Fly Time Reference Point) ................................................117
Figure 69: GT-64260A Test Circuit (Cload = 50pf) .............................................................................................118
Figure 70: GT-64260A Chip Select Reference Point..........................................................................................119
Figure 71: Chip Select Signal Routing on the DIMM Module ..............................................................120
Figure 72: 0.8 ns Delay Trace Simulation (2.8 ns Fly Time Reference Point).....................................................122
Figure 73: GT-64260A Double Cycle Signals AC Timing ...................................................................................123
Figure 74: Double Cycle Signal Routing on the DIMM Module ....................................................................124
Figure 75: 0.8 ns Delay Trace Simulation (2.0 ns Fly Time Reference Point) ..................................................126
Figure 76: Device Placement Example................................................................................................................127
Figure 77: GT-64260A Test Circuit (Cload = 20pf) .............................................................................................131
Figure 78: GT-64260A GNT* Signals Reference Point ......................................................................................132
Figure 79: 2.1 ns Fly Time Reference Point ........................................................................................................133
Figure 80: MII Interface Connection ....................................................................................................................134
Figure 81: RMII Interface Connection:.................................................................................................................135
Figure 82: GT-64260A RMII Signals Reference Point ........................................................................................137
Figure 83: 2.1 ns Fly Time Reference Point ........................................................................................................138
Figure 84: PHY Placement ..................................................................................................................................139
Figure 85: GT-64260A Power Supply Pin Map....................................................................................................142

Introduction
Related Documentation
Copyright © 2002 Marvell CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A
May 21, 2002, Preliminary Document Classification: Proprietary Information Page 11
Section 1. Introduction
This design guide provides information for designing a system using the GT-64260A. This guide is intended for
internal and external reference and is subject to future changes and modifications.
Use this document as an addition to the GT-64260A datasheet and evaluation/reference design schematics.
1.1 Related Documentation
The following documents are referenced by this design guide or provide additional information about working with
the GT-64260A. See the Marvell® website at http://www.marvell.com to access this material.
•GT-64260A Datasheet, Doc. No. MV-S100413-00
•EV-64260A-BP-xxxxx Reference Platform Schematics
•PCI 2.2 Local Bus Specification
•AN-66: Initializing Ethernet Ports
•AN-67: Powering Up /Powering Down Galileo Technology Devices with Multiple Power Supplies of Different
Voltages, Doc. No. MV-S300069-00
•AN-72: Operating the MPSC as a UART, Doc. No. MV-S300072-00
•AN-82: SDRAM Clocking Schemes in the GT-642xx/A Devices, Doc. No. MV-S300108-00
•BRG Settings Tool
•PCI Specification 2.2 - http://www.pcisig.com/specifications/conventional_pci

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Section 2. GT-64260A Overview
The GT-64260A is a bridge from the PowerPC processor to the PCI bus, as well as a high-speed memory control-
ler for external ROM and external peripherals. In addition, the GT-64260A integrates three 10/100 Mbps Ethernet
ports and two MPSC controllers.
The GT-64260A provides a single-chip solution for designers building systems for a PowerPC 64-bit bus CPU. It
has the following interfaces:
•A 64-bit interface to the CPU bus.
•A 64-bit interface to SDRAM.
•A 32-bit interface to devices (various types of memory and I/O devices).
•Two 64-bit PCI interfaces.
•Three RMII/MII interfaces.
•Two MPSC communication interfaces.
Figure 1 shows the GT-64260A interfaces.
Figure 1: GT-64260A Interfaces
PCI_1 PCI_0
SDRAM
CPU
Ethernet
ports
Device
Serial
ports
MPP
(Multi Purpose Pins)
64-bit 64-bit
64-bit32-bit
64-bit
32-bit
GT–64260A

GT-64260A Overview
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Figure 2: Typical GT-64260A System Configuration
PowerPC
CPU
2 Gigabyte
DRAM
Routing
Unit
8xIDMA 3x10/100
2xMPSC GPP
SDRAM i/f Device i/f
CPU I/f
PCI0 i/f
Boot
Flash
OC-48
Framing
ASIC
Box Mang.
Bus
UART
Monitor
Back Plane
Tranceiver
PCI0 i/f

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Section 3. CPU Interface Functional Overview
The GT-64260A supports PowerPC 64-bit bus CPUs. (See Section 3.5 "Specific CPUs Aspects" .) These include the
following:
•Motorola MPC603e/604e
•Motorola MPC740/750/755
•Motorola PowerQUICC II (MPC8260)
•Motorola MPC7400/7410/745x
•IBM PPC603e
•IBM PPC750/750cx/e/750FX
•Any 64-bit 60x or MPX compatible CPU
The CPU interface can work as a slave interface, responding to CPU transactions, or as a master interface, gen-
erating transactions on the CPU bus. The master interface is used for PowerPC snoop generation. It also allows
for access to MPC8260 local memory or GT-to-GT transfers in a multi-GT-64260A configuration.
3.1 CPU Pinout Description
The GT-64260A provides all the pins needed to interface between the PowerPC processor and other devices
(such as SDRAM, ROM, PCI, etc.). Generally, there is a point-to-point connection between the GT-64260A and
the CPU. In other cases, it depends on the system architecture, such as multi-GT-64260A, multiple CPU, or exter-
nal arbiter. The following table describes the pin information and details of the GT-64260A CPU interface.
Table 1: CPU Interface Pin Information
Pin Name Input/
Output
PowerPC CPU Pin
Connection
Required
External
Resistor
Description
A[0-31],
AP[0-4]
T/S I/O For address connection to
CPUs that support 36-bit
addressing, see 3.5.3
"MPC745x Extended Pins" on
page 22.
For all other CPUs with 32-bit
address, connect to
A[0-31], AP[0-4].
10K-Ohm Pull-up CPU address bus and
address parity bus.
To work with address parity
in the system, set the CPU
Configuration register’s
APValid bit [26], at offset
0x000 to ‘1’.
DH[0-31],
DL[0-31],
DP[0-7]
T/S I/O Some CPUs use D[0-63] for
the entire data bus. In this
case, use the following connec-
tion:
• DH[0-31] = D[0-31]
• DL[0-31]=D[32-63]
The GT-64260A
includes internal
Pull-ups.
CPU data bus and data par-
ity bus.
To work with data parity in
the system, set the CPU
Configuration register’s
DPValid bit [19], at offset
0x000 to ‘1’.

CPU Interface Functional Overview
CPU Pinout Description
Copyright © 2002 Marvell CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A
May 21, 2002, Preliminary Document Classification: Proprietary Information Page 15
SysClk I See Section 19. "Clocks" on
page 143.
When the CPU inter-
face is configured to
run with TClk instead
of SysClk, SysClk is
not used and must
be tied to GND.
CPU interface clock.
The CPU clock configuration
is selected by AD[5] value at
reset de-assertion.
0 = SysClk asynchronous to
TClk.
1 = CPU interface is running
with TClk.
SysRst* I See Section 20. "Reset" on
page 144.
The GT-64260A main reset
pin.
When in the reset state, all
output pins (except for
SDRAM address and control
pins) are put into tri-state.
TS* T/S I/O TS* 10K-Ohm Pull-up Address tenure start
TSIZ[0:2] T/S I/O TSIZ[0:2] 10K-Ohm Pull-up Transfer size
TBST* T/S I/O TBST* 10K-Ohm Pull-up Transfer burst
TT[0:4] T/S I/O TT[0:4] 10K-Ohm Pull-up Transfer type
TA* T/S I/O TA* In multi-GT mode,
requires 10K-Ohm
Pull-up.
Transfer acknowledge
AACK* T/S I/O AACK* In multi-GT mode,
requires 10K-Ohm
Pull-up.
Address acknowledge
ARTRY* T/S I ARTRY*. 10K-Ohm Pull-up Address retry.
Not sampled on the second
cycle after the AACK* asser-
tion.
ABB* T/S I/O When working with PowerPC
CPUs that use the ABB* pin as
input, ABB* must be con-
nected.
Otherwise, ABB* must be
pulled up.
10K-Ohm Pull-up Address bus busy
DBB* T/S I/O When working with PowerPC
CPUs that use the DBB* pin as
input, DBB* must be con-
nected.
Otherwise, DBB* must be
pulled up.
10K-Ohm Pull-up Data bus is busy
Table 1: CPU Interface Pin Information (Continued)
Pin Name Input/
Output
PowerPC CPU Pin
Connection
Required
External
Resistor
Description

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DTI[0-2] T/S O Only applicable on CPUs that
support MPX bus.
When using the MPC745x,
connect to DTI[1-3] of the
MPC745x. DTI[0] of the
MPC745x must be pulled low.
When using MPC741x, con-
nect to DTI[0-2].
MPC740x/741x plat-
forms:
DTI[0]/DBWO* must
be pulled up.
DTI[1:2] must be
pulled Low.
MPC75x/PPC75x
pin compatible to
MPC740x/741x plat-
forms:
DTI[0]/DBWO* must
be pulled up.
DTI[1]/ARTRY* must
be pulled up or con-
nected to HRESET*.
(See the MPC75x
user manual)
DTI[2] pulled down.
For all other configu-
rations 10K-Ohm
pull-down.
Data transfer index.
BR0*/
GT_BG*
I When using the GT-64260A
internal arbiter, connect to the
primary CPU BR* pin.
When using an external arbiter,
connect to the arbiter GT_BG*
pin.
NOTE: In single CPU systems
with the internal arbiter
enabled, must be used as
BR0*.
To avoid unstable
states at reset, a
10K-Ohm Pull-up is
recommended.
BG0* T/S O When using the GT-64260A
internal arbiter, connect to the
primary CPU BG* pin.
When using an external arbiter,
this pin can be left as not con-
nected (NC).
NOTE: In single CPU systems
with the internal arbiter
enabled, must be used as
BG0*.
To avoid unstable
states at reset or
when an external
arbiter is used, a
10K-Ohm Pull-up is
recommended.
Table 1: CPU Interface Pin Information (Continued)
Pin Name Input/
Output
PowerPC CPU Pin
Connection
Required
External
Resistor
Description

CPU Interface Functional Overview
60x Bus Mode
Copyright © 2002 Marvell CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A
May 21, 2002, Preliminary Document Classification: Proprietary Information Page 17
3.2 60x Bus Mode
The GT-64260A can act as master and slave on the 60x bus. In this mode, the GT-64260A 60x internal arbiter sup-
ports three masters on the bus; two external 60x compatible masters, and an internal 60x master. The GT-64260A
is configured to 60x bus mode by having the AD[7:6] signals sampled to b’00’ at reset de-assertion. The CPU bus
configuration can be read in the CPU Mode register’s (Offset: 0x120) CPUType bits [7:4].
DBG0* T/S O When using the GT-64260A
internal arbiter, connect the pri-
mary CPU DBG* pin.
When using an external arbiter,
this pin can be left as not con-
nected (NC).
NOTE: In single CPU systems
with the internal arbiter
enabled, must be used as CPU
DBG0*.
To avoid unstable
states at reset or
when an external
arbiter is used, a
10K-Ohm Pull-up is
recommended.
BR1*/
GT_DBG*
I When using single CPU sys-
tems, this pin can be left as not
connected (NC).
When using the GT-64260A
internal arbiter, connect to the
secondary CPU BR* pin.
When using an external arbiter,
connect to the arbiter
GT_DBG* pin.
To avoid unstable
states at reset or in a
single CPU configu-
ration, a 10K-Ohm
Pull-up is recom-
mended.
DBG1* T/S O When using an external arbiter
or single CPU systems, this pin
can be left as not connected
(NC).
When using the GT-64260A
internal arbiter, connect to the
secondary CPU DBG* pin.
To avoid unstable
states at reset or
when external arbiter
is used, a 10K-Ohm
Pull-up is recom-
mended.
BG1*/
GT_BR*
T/S O When using single CPU sys-
tems, this pin can be left as not
connected.
When using the GT-64260A
internal arbiter, connect to the
secondary CPU BG* pin.
When using an external arbiter,
connect to the arbiter GT_BR*
pin.
To avoid unstable
states at reset or
when external arbiter
is used, a 10K-Ohm
Pull-up is recom-
mended.
Table 1: CPU Interface Pin Information (Continued)
Pin Name Input/
Output
PowerPC CPU Pin
Connection
Required
External
Resistor
Description

GT-64260A Design Guide
Doc. No. MV-S300165-00, Rev. A CONFIDENTIAL Copyright © 2002 Marvell
Page 18 Document Classification: Proprietary Information May 21, 2002, Preliminary
On the 60x bus, the internal 60x master supports snoop and master capability for data transfers between the GT-
64260A and other agents on the 60x bus, such as another GT-64260A device.
3.3 MPX Bus Mode
Note
The GT-64260A does not support multi-GT mode in MPX bus mode.
The GT-64260A can act as master and slave on the MPX bus. In this mode, the GT-64260A 60x internal arbiter
supports two masters on the bus, one external MPX compatible master and the internal CPU bus master for
snoop transaction only. The GT-64260A is configured to MPX bus mode by AD[7:6] signals sampled to b’01’ at
reset de-assertion. The CPU bus configuration can be read in the CPU Mode Register (Offset: 0x120) bits CPU-
Type (bits 7:4).
Table 2 describes the MPX bus features that are supported by the GT-64260A.
3.4 Cache Coherency
The GT-64260A supports full cache coherency between the SDRAM and CPU caches.
Any access to the SDRAM (from PCI or IDMA) may result in a snoop transaction driven by the GT-64260A on the
CPU bus. The SDRAM access to a cache coherent region is always suspended until the snoop is resolved. In
case of a HIT in a modified line in CPU cache, the SDRAM access might be suspended until the line write-back to
SDRAM is completed.
Figure 3 describes the transaction flow for PCI reads from cache coherent regions.
Table 2: GT-64260A Supported Features in MPX Bus Mode
Features Description
Address streaming The CPU initiates a new address tenure the cycle after AACK* assertion without a
dead cycle between the two address tenures.
Data streaming If the data bus is driven by the same agent in both data tenures, no dead cycle is
required between two consecutive data tenures.
16 byte burst Load/store of AltiVec uncached operands.
Read out of order
completion
The CPU read response data of pipelined transactions in any order. The DTI[0-2] pins
indicates data tenure ID.
• 000 = data of the oldest pending read.
• 001 = the second oldest pending read.
• 010 = the third oldest pending read.
NOTE: To enable the read out of order completion, the CPU Configuration register’s
RdOOO bit [16] and Pipeline bit [13] must be set to ‘1’, at offset 0x000.

CPU Interface Functional Overview
Cache Coherency
Copyright © 2002 Marvell CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A
May 21, 2002, Preliminary Document Classification: Proprietary Information Page 19
Figure 3: PCI Reads from Cache Coherent Regions
The GT-64260A supports up to four SDRAM address windows in which IDMA cache coherency is maintained. The
address windows do not correlate to specific chip selects and may cross CS boundaries.
The GT-64260A also supports eight configurational address ranges (four for each PCI interface) that help maintain
PCI cache coherency.
Four pairs of base/top registers define the IDMA address regions.
Each channel has a programmable bit per source, destination, and next descriptor pointer to enable/disable
snoops in its Control (High) register’s
SrcSnoopEn , DestSnoopEn and NextSnoopEn bits. If these bits (or each
one of these bits) are set, each IDMA engine transaction address is compared against the four cache coherency
regions. If an address hits one of these regions, the DRAM access results in a snoop action, based on cache pol-
icy (WB/WT) as defined by the snoop regions registers Additionally, the CPU Master Control register’s
CleanBlock and FlushBlock bits [13:12] at offset: 0x160 must be set to the appropriate value depending on
the CPU type.
Table 3: IDMA Address Base/Top Registers
Register Offset
Snoop Base Address 0 0x380
Snoop Top Address 0 0x388
Snoop Base Address 1 0x390
Snoop Top Address 1 0x398
Snoop Base Address 2 0x3A0
Snoop Top Address 2 0x3A8
Snoop Base Address 3 0x3B0
Snoop Top Address 3 0x3B8
GT-64260A
SDRAM
CPU
Snoop
Queue
PCI bus
1. The PCI device initailizes
a read transaction to cache
coherent memory.
Transaction enters to the
snoop queue.
2. The GT-64260A 60x master
snoops the transaction on the
CPU bus to see if the cache
block is valid in the cache.
3. If there is a hit, the CPU
writes the cache block to
SDRAM (cache block
flush). Or, the snoop is
resolved without a CPU
write.
4. The PCI
receives the
updated data
from SDRAM.

GT-64260A Design Guide
Doc. No. MV-S300165-00, Rev. A CONFIDENTIAL Copyright © 2002 Marvell
Page 20 Document Classification: Proprietary Information May 21, 2002, Preliminary
The pairs of base/top registers define the PCI address regions as shown in the table below.
Each PCI transaction address is compared against the four cache coherency regions. If an address hits one of
these regions, the DRAM access results in a snoop action, based on cache policy (WB/WT) and as defined by the
snoop region registers. Additionally, the CPU Master Control registers
CleanBlock and FlushBlock bits [13:12]
at offset 0x160 must be set to the appropriate value depending on the CPU type.
3.4.1 Cache Coherency Initialization Sequence
The cache coherency initialization sequence is as follows:
1. The CPU Configuration register’s
AACK Delay bit [11], at offset 0x000, must be set to '1'. See the
latest GT-64260A errata and restrictions document for more information.
2. In the CPU Master Control at offset 0x160, set the
CleanBlock and FlushBlock bits [13:12] to
the correct value, depending on the CPU type. See the GT-64260A datasheet’s "CPU Interface" sec-
tion for more information.
3. Configure cache coherent windows for the desired interface with the PCI cache coherency registers
(0x1F00 - 0x1F38) and the IDMA cache coherency registers (0x380 - 0x3B8).
4. Confirm that the Snoop Control Base (Low) register’s Snoop bits [13:12] at offset 0x1F00–0x1F30
are set to the correct value, depends on the CPU cache policy (WB or WT).
NOTE: The cache coherency will not be enabled when these bits are set to No snoop (0x0).
5. When using the PCI access control registers (base smaller than top) 0x1E00 - 0x1E78, the MBurst
bits to the cache coherent memory must be set to 0x0 (four 64-bit words).
NOTE: Never configure the communication interface to work with cache coherent regions (see GT-
64260A errata and restriction document).
Table 4: PCI Address Base/Top Registers
Register PCI_0 Offset PCI_1 Offset
PCI Snoop Control Base 0 (Low) 0x1F00 0x1F80
PCI Snoop Control Base 0 (High) 0x1F04 0x1F84
PCI Snoop Control Top 0 0x1F08 0x1F88
PCI Snoop Control Base 1 (Low) 0x1F10 0x1F90
PCI Snoop Control Base 1 (High) 0x1F14 0x1F94
PCI Snoop Control Top 1 0x1F18 0x1F98
PCI Snoop Control Base 2 (Low) 0x1F20 0x1FA0
PCI Snoop Control Base 2 (High) 0x1F24 0x1FA4
PCI Snoop Control Top 2 0x1F28 0x1FA8
PCI Snoop Control Base 3 (Low) 0x1F30 0x1FB0
PCI Snoop Control Base 3 (High) 0x1F34 0x1FB4
PCI Snoop Control Top 3 0x1F38 0x1FB8