Maxim Integrated MAX3420E Operating instructions

AVAILABLE
MAX3420E
USB Peripheral Controller with
SPI Interface
Programming Guide
MISO
VCC
GND
D+
D-
XI XO
MOSI
SCK
SS#
INT
RES#
GPX
VBCOMP
VL
GND
GPIN0
GPIN1
GPIN2
GPIN3
GPOUT0
GPOUT1
GPOUT2
GPOUT3
For more information on the MAX3420E, please visit http://www.maxim-ic.com/max3420e.
For more information on USB and Maxim’s USB products, see http://www.maxim-ic.com/usb.
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc.
The Dallas Semiconductor logo is a registered trademark of Dallas Semiconductor Corp.
Copyright 2005Maxim Integrated Products, Inc. All rights reserved.
Rev. Sept 28, 2005

Register Map
Bits are shown in normal font, registers are shown in italics.
Each highlighted cell is a link to a page describing the register or bit. Use the browser left arrow to return to this page. The Index at
the end of this document is also linked to the descriptive pages.
Reg Name b7 b6 b5 b4 b3 b2 b1 b0 acc
R0 EP0FIFO b7 b6 b5 b4 b3 b2 b1 b0 RSC
R1 EP1OUTFIFO b7 b6 b5 b4 b3 b2 b1 b0 RSC
R2 EP2INFIFO b7 b6 b5 b4 b3 b2 b1 b0 RSC
R3 EP3INFIFO b7 b6 b5 b4 b3 b2 b1 b0 RSC
R4 SUDFIFO b7 b6 b5 b4 b3 b2 b1 b0 RSC
R5 EP0BC 0 b6 b5 b4 b3 b2 b1 b0 RSC
R6 EP1OUTBC 0 b6 b5 b4 b3 b2 b1 b0 RSC
R7 EP2INBC 0 b6 b5 b4 b3 b2 b1 b0 RSC
R8 EP3INBC 0 b6 b5 b4 b3 b2 b1 b0 RSC
R9 EPSTALLS 0 ACKSTAT STLSTAT STLEP3IN STLEP2IN STLEP1OUT STLEP0OUT STLEP0IN RSC
R10 CLRTOGS EP3DISAB EP2DISAB EP1DISAB CTGEP3IN CTGEP2IN CTGEP1OUT 0 0 RSC
R11 EPIRQ 0 0 SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ IN0BAVIRQ RC
R12 EPIEN 0 0 SUDAVIE IN3BAVIE IN2BAVIE OUT1DAVIE OUT0DAVIE IN0BAVIE RSC
R13 USBIRQ URESDNIRQ VBUSIRQ NOVBUSIRQ SUSPIRQ URESIRQ BUSACTIRQ RWUDNIRQ OSCOKIRQ RC
R14 USBIEN URESDNIE VBUSIE NOVBUSIE SUSPIE URESIE BUSACTIE RWUDNIE OSCOKIE RSC
R15 USBCTL HOSCSTEN VBGATE CHIPRES PWRDOWN CONNECT SIGRWU 0 0 RSC
R16 CPUCTL 0 0 0 0 0 0 0 IE RSC
R17 PINCTL EP3INAK EP2INAK EP0INAK FDUPSPI INTLEVEL POSINT GPXB GPXA RSC
R18 REVISION 0 0 0 0 Rev3 Rev2 Rev1 Rev0 R
R19 FNADDR 0 b6 b5 b4 b3 b2 b1 b0 R
R20 IOPINS GPIN3 GPIN2 GPIN1 GPIN0 GPOUT3 GPOUT2 GPOUT1 GPOUT0 RSC
Note: The acc (access) column indicates how the CPU can access the register. R=Read, RC=Read or Clear, RSC=Read, Set or Clear.

Accessing the MAX3420E Registers
An SPI™ master controls the MAX3420 by writing and reading twenty-one internal registers,
R0-R20. The SPI master begins every register access by asserting the MAX3420E SS# (slave
select, active low) pin, and clocking in eight bits that comprise the SPI command byte. Figure 1
shows the command byte format.
ACKSTAT
DIR
1=wr 0=rd
0Reg0Reg1Reg2Reg3Reg4
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1. SPI Command Byte. As for all SPI transfers, bit 7 is sent first.
Reg4:Reg0 set the register address, with valid values from 0-20. Values above 20 are ignored by
the MAX3420E. The direction bit sets the direction for the data transfer. The ACKSTAT bit
duplicates a USB control bit (R9 bit 6). ACKSTAT is provided in the control byte as a fast way
to set this often-used register bit.
After sending the command byte, the SPI master transfers one or more bytes in the direction
indicated by the DIR bit. Keeping SS# low, the SPI master provides additional bursts of eight
SCLK pulses for each byte. When the byte transfers are complete, the SPI master de-asserts SS#
(drives high) and the transfer terminates.
It is possible to truncate an SPI cycle after sending only the command byte. This feature allows
the SPI master to set the ACKSTAT bit without doing a full SPI access.
Note: The ACKSTAT bit tells the MAX3420E that the SPI master has finished servicing a USB
Control transfer. This causes the MAX3420E to ACKnowledge the next Control transfer
STATUS stage.
To set the ACKSTAT bit using the SPI command byte, the SPI master sets the register field to a
dummy value (it won’t be used), sets the DIR bit for a read operation (for example, read
Revision register R18), and sets the ACKSTAT bit. The SPI master then asserts SS#, clocks in
the 8 command bits, and then truncates the SPI cycle by de-asserting the SS# signal. This is the
fastest way to set the ACKSTAT bit.
The MAX3420E has two register types, FIFOS and control registers. Repeated reads or writes to
a register has different effects, depending on the register type.
SPI is a trademark of Motorola, Inc.

Registers R0-R4 access internal FIFOS. After selecting the register number R0-R4 with the
command byte, the SPI master loads or unloads consecutive FIFO bytes by repeating reads or
writes during the SPI transfer. For example, to read 8 bytes from the SUDFIFO, the SPI master
would perform the following steps:
1. Set SS#=0.
2. Send 00100000. This command byte selects R4 (SUDFIFO), for a read operation
(DIR=0).
3. Issue eight SCLK pulses, clock in a data byte, one bit per SCLK rising edge.
4. Repeat step 3 seven more times, clocking in and storing a total of 8 bytes.
5. Set SS#=1.
Registers R5-R20 are control registers. If the SPI master repeatedly reads or writes R5-R20
during the same SPI transfer (SS# low), every byte read or write automatically increments the
register address. This allows reading or writing registers in consecutive groups without writing a
new command byte to set each new register address. The register addresses continue to
increment until the last register, R20 is reached, where the register address “sticks” at R20. This
feature gives the uP a quick access method for the IO pins in R20. For example, to output a pre-
stored waveform on a GPIO pin, the SPI master can write the command byte 10100010 (R20,
Write) and then send multiple data bytes to R20 output the waveform.

ACKSTAT
Meaning: Acknowledge the STATUS stage of a CONTROL transfer.
Location: EPSTALLS.6
Set: The CPU sets this bit after it has finished servicing a CONTROL transfer request.
This instructs the SIE to send the ACK handshake to the status stage of the
current CONTROL transfer. Until the CPU sets this bit, the SIE responds to the
status stage of the CONTROL transfer with a NAK handshake.
Clear: The SIE clears this bit whenever a SETUP token arrives.
POR: ACKSTAT=0
Chip Reset: ACKSTAT=0
Bus Reset: ACKSTAT=0
Pwr Down: Read-only
FYI: A fast way to set the ACKSTAT register bit is to set bit 0 of the SPI command
byte. All Maxim example code uses this method.
Programming Notes:
When the CPU receives a Setup Data Available Interrupt Request (SUDAVIRQ bit, page 66), it
clears the SUDAVIRQ bit by writing “1” to it, and then reads the eight data bytes from the
SUDFIFO into memory. The CPU then inspects the eight bytes to determine the nature of the
USB request. If the request is in error or unknown, the CPU sets the STLSTAT bit to answer the
status stage with a STALL handshake (page 64).
If the CPU recognizes the request, it services the request, and when finished sets ACKSTAT=1
to tell the SIE to send the ACK handshake to the status stage to terminate the CONTROL
transfer. Until the CPU either acknowledges or stalls the transfer, the SIE automatically returns
the NAK handshake to the CONTROL transfer status stage.
A C program that interprets the 8 bytes of setup data usually consists of one or more case
statements that check for all the legal combination of bytes in the setup packet. A convenient
way to handle the STALL is to make the default case a statement that stalls the CONTROL
transfer. (see the STLSTAT bit, page 64).
1

BUSACTIE
Meaning: Bus Active Interrupt Enable.
Location: USBIEN.2
Set: The CPU sets this bit to enable the BUSACT IRQ (page 2).
Clear: The CPU clears this bit to disable the BUSACT IRQ.
POR: BUSACTIE=0
Chip Reset: BUSACTIE=0
Bus Reset: BUSACTIE=0
Pwr Down: Read-only
Programming Notes:
Because most of the Interrupt Enable bits are cleared during a USB bus reset, the initialization
routine that turns on the interrupt enable bits should be called as part of servicing a USB bus
reset.
2

BUSACTIRQ
Meaning: Bus Active Interrupt Request.
Location: USBIRQ.2
Set: The SIE sets this bit to indicate USB bus activity. An internal BUSACT signal is
set when the SIE receives a SYNC field, and reset after 32 bit time of a J-state, or
during a USB bus reset. The BUSACTIRQ bit is set when the internal BUSACT
signal makes a 0-1 transition.
Clear: The CPU clears this bit by writing a “1” to it.
POR: BUSACTIRQ=0
Chip Reset: BUSACTIRQ=0
Bus Reset: BUSACTIRQ=0
Pwr Down: Read-only
3

CHIPRES
Meaning: Chip Reset.
Location: USBCTL.5
Set: The CPU sets this bit to reset the chip. Its effect is identical to driving the RES#
pin low.
Clear: The CPU clears this bit to take the chip out of reset.
POR: CHIPRES=0
Chip Reset: No change
Bus Reset: No change
Pwr Down: Read-write
Programming Notes:
The CPU can clear this bit immediately after setting it.
4

CONNECT
Meaning: Connect to USB.
Location: USBCTL.3
Set: The CPU sets this bit to connect an internal 1500 Ohm resistor between the
DPLUS line and VCC.
Clear: The CPU clears this bit to disconnect an internal 1500 Ohm resistor between the
DPLUS line and VCC.
POR: CONNECT=0
Chip Reset: No change
Bus Reset: No change
Pwr Down: Read-write
Programming Notes:
The operation of the CONNECT bit depends on the setting of the VBGATE bit (page 76). If
CONNECT=1 and VBGATE=1, internal logic will not connect the pullup resistor unless VBUS is
detected to be valid on the VBUS pin. If VBGATE=0 the DPLUS pullup resistor is
unconditionally connected when CONNECT=1.
Only a power-on reset clears the CONNECT bit. If, during operation, an external reset is applied
to the MAX3420E via the INT pin, the CONNECT bit retains its state. This means that if a
device is connected to USB (CONNECT=1) when the RES# is asserted, it remains connected
throughout the reset and after the reset is removed (RES#=1).
5

CTGEP1OUT
Meaning: Clear Data Toggle for endpoint 1 OUT.
Location: CLRTOGS.2
Set: The CPU sets this bit to clear the data toggle for EP1-OUT to the DATA0 state.
Clear: The SIE automatically clears this bit.
POR: CTGEP1OUT=0
Chip Reset: CTGEP1OUT=0
Bus Reset: CTGEP1OUT=0
Pwr Down: Read-only
Programming Notes:
The SIE automatically clears all data toggles during a chip or USB bus reset. The CPU normally
needs to clear an individual endpoint data toggle under two conditions:
• The host issues a Set_Configuration request.
• The host issues a Clear_Feature (endpoint stall) request.
6

CTGEP2IN
Meaning: Clear Data Toggle for Endpoint 2 IN.
Location: CLRTOGS.3
Set: The CPU sets this bit to clear the data toggle for EP2-IN to the DATA0 state.
Clear: The SIE automatically clears this bit.
POR: CTGEP2IN=0
Chip Reset: CTGEP2IN=0
Bus Reset: CTGEP2IN=0
Pwr Down: Read-only
Programming Notes:
The SIE automatically clears all data toggles during a chip or USB bus reset. The CPU normally
needs to clear an individual endpoint data toggle under two conditions:
• The host issues a Set_Configuration request.
• The host issues a Clear_Feature (endpoint stall) request.
7

CTGEP3IN
Meaning: Clear Data Toggle for endpoint 3 IN.
Location: CLRTOGS.4
Set: The CPU sets this bit to clear the data toggle for EP3-IN to the DATA0 state.
Clear: The SIE automatically clears this bit.
POR: CTGEP3IN=0
Chip Reset: CTGEP3IN=0
Bus Reset: CTGEP3IN=0
Pwr Down: Read-only
Programming Notes:
The SIE automatically clears all data toggles during a chip or USB bus reset. The CPU normally
needs to clear an individual endpoint data toggle under two conditions:
• The host issues a Set_Configuration request.
• The host issues a Clear_Feature (endpoint stall) request.
8

EP0BC
Meaning: Endpoint 0 Byte Count Register. Since EP0 is a bi-directional endpoint, whereby
both IN and OUT transfers share the same FIFO (EP0FIFO, page 10), the action
of this register depends on the transfer direction.
Location: EP0BC[6:0]
Write (IN): For an IN transfer, the CPU writes the byte count to this register after loading the
EP0FIFO with data. Valid values are 0-64. When the CPU writes this register the
SIE arms the endpoint so that it returns a data packet instead of a NAK to the next
IN request to the endpoint.
Read (OUT): For an OUT transfer, the SIE loads the byte count to indicate the number of bytes
received in an OUT data transfer. When the OUT transfer is successful, the SIE
ACKS the transfer, updates the byte count register, and asserts the OUT0DAV
interrupt request bit (page 51).
POR: EP0BC=0
Chip Reset: EP0BC=0
Bus Reset: EP0BC=0
Pwr Down: No read or write
Programming Notes:
Bit 7 has no effect and reads as a 0.
The CPU writes the EP0FIFO as the response to the data stage of a CONTROL transfer.
The CPU reads the EP0FIFO to retrieve the data stage of a CONTROL transfer.
9

EP0FIFO
Meaning: Endpoint 0 FIFO. This 64 byte FIFO is used for OUT and IN transfers to and
from the bi-directional endpoint 0.
Location: EP0FIFO[7:0]
Write (IN): For an IN transfer, the CPU writes a series of bytes to this FIFO to fill it with IN
data. After filling the FIFO with a packet (0 to 64 bytes), the CPU writes the byte
count register (page 9) to arm the IN transfer and to tell the SIE how many bytes
to transfer when it receives the IN packet to endpoint 0.
Read (OUT): For an OUT transfer, the SIE fills the FIFO with USB data received from the host.
When the OUT transfer is verified to be error-free, the SIE loads the byte count
register (page 9) to indicate the number of bytes received in the OUT data
transfer. For a successful transfer the SIE also ACKS the OUT transfer and asserts
the OUT0DAV interrupt request bit (page 51).
POR: EP0FIFO[7:0]=0
Chip Reset: EP0FIFO[7:0]=0
Bus Reset: Unchanged
Pwr Down: No read or write
Programming Notes:
The SIE automatically retries packets that it finds to contain errors (CRC, bit stuff, etc.). This is
invisible to the CPU—no interrupt flags or registers are updated with less than perfect transfers.
10

EP0INAK
Meaning: EP0-IN NAK.
Location: PINCTL.5
Set: The SIE sets this bit when the EP0-IN endpoint receives an IN request and returns
the NAK handshake.
Clear: The CPU clears this bit by writing a 1 to it.
POR: EP0IBN=0
Chip Reset: EP0IBN=0
Bus Reset: EP0IBN=0
Pwr Down: Read-write
Programming Notes:
This bit may be polled to discover that the host is asking for IN data which is not yet available
from an IN endpoint because the CPU has not yet loaded and armed the endpoint. This bit is not
included in the interrupt system.
Note: The EP0INAK bit is informational only. It is normally not used by USB device firmware.
11

EP1DISAB
Meaning: Disable Endpoint 1-OUT.
Location: CLRTOGS.5
Set: The CPU sets this bit to disable traffic to Endpoint 1-OUT.
Clear: The CPU clears this bit to enable traffic to Endpoint 1-OUT.
POR: EP1DISAB=0
Chip Reset: EP1DISAB=0
Bus Reset: EP1DISAB=0
Pwr Down: Read-only
Programming Notes:
A disabled endpoint does not respond to any traffic. A host normally will never send traffic to an
endpoint that is not reported during enumeration, so this is a “safety” bit to guard against an
errant host.
Endpoint 0 has no disable bit because as the default CONTROL endpoint it must always be
active.
12

EP1OUTBC
Meaning: Endpoint 1-0UT Byte Count.
Location: EP1OUTBC[6:0]
Write: After successfully receiving an OUT transfer over Endpoint 1, the SIE ACKS the
transfer, updates this register with the received byte count, and asserts the
OUT1DAV interrupt request (page 51).
Read: The CPU reads this register after receiving an OUT1DAV interrupt request to
determine how many bytes to read from the EP1OUTFIFO (page 14).
POR: EP1OUTBC=0
Chip Reset: EP1OUTBC=0
Bus Reset: EP1OUTBC=0
Pwr Down: No read or write
Programming Notes:
EP1OUT is a double-buffered endpoint, meaning that there are two FIFOS and byte count
registers. Double buffering allows USB data simultaneously to move into one FIFO while the
CPU reads data from the other. This improves bandwidth performance in many systems. See the
OUT1DAVIRQ bit discussion (page 51) for a description of how the double buffering works for
an OUT endpoint.
The double buffering is invisible to the programmer because the OUT1DAVIRQ flag logic
accommodates the double buffering. For example, assume that both buffers are available and
therefore OUT1DAVIRQ=0. When an OUT packet arrives, OUT1DAVIRQ makes a 0-1
transition to indicate availability of the first packet. For a single-buffered endpoint, if another
OUT packet arrived over EP1-OUT before the CPU had time to drain the FIFO, the SIE would
respond with a NAK handshake to indicate that the endpoint was not available to accept data.
However with the double buffered endpoint, the second OUT packet is accepted and ACK’d
because the second buffer is available for data. If a third OUT packet arrives before either FIFO
is drained, the SIE NAKS the transfer to indicate that both FIFOS are full.
13

EP1OUTFIFO
Meaning: Double-buffered 64 byte FIFO for Endpoint 1-OUT.
Location: EP1OUTFIFO[7:0]
Write: The SIE fills the OUT FIFO with bytes transmitted from the host to endpoint 1-
OUT. After successfully receiving the OUT transfer, the SIE ACKS the transfer,
updates the byte count register (page 13), and asserts the OUT1DAV interrupt
request (page 51).
Read: When the CPU receives an OUT1DAV interrupt request, it reads the byte count
register to determine how many bytes are in the FIFO, and then reads that number
of bytes from this register.
POR: EP1OUTFIFO=0
Chip Reset: EP1OUTFIFO=0
Bus Reset: Unchanged
Pwr Down: No read or write
Programming Notes:
EP1OUT is a double-buffered endpoint, meaning that there are two FIFOS and byte count
registers. Double buffering allows USB data simultaneously to move into one FIFO while the
CPU reads data from the other. This improves bandwidth performance in many systems. See the
OUT1DAVIRQ bit discussion (page 53) for a description of how the double buffering works for
an OUT endpoint.
The double buffering is invisible to the programmer because the OUT1DAVIRQ flag logic
accommodates the double buffering. For example, assume that both buffers are available and
therefore OUT1DAVIRQ=0. When an OUT packet arrives, OUT1DAVIRQ makes a 0-1
transition to indicate availability of the first packet. For a single-buffered endpoint, if another
OUT packet arrived over EP1-OUT before the CPU had time to drain the FIFO, the SIE would
respond with a NAK handshake to indicate that the endpoint was not available to accept data.
However with the double buffered endpoint, the second OUT packet is accepted and ACK’d
because the second buffer is available for data. If a third OUT packet arrives before either FIFO
is drained, the SIE NAKS the transfer to indicate that both FIFOS are full.
14

EP2DISAB
Meaning: Disable Endpoint 2.
Location: CLRTOGS.6
Set: The CPU sets this bit to disable traffic to endpoint 2-IN.
Clear: The CPU sets this bit to enable traffic to endpoint 2-IN.
POR: EP2DISAB=0
Chip Reset: EP2DISAB=0
Bus Reset: EP2DISAB=0
Pwr Down: Read-only
Programming Notes:
A disabled endpoint does not respond to any traffic. A host normally will never send traffic to an
endpoint that is not reported during enumeration, so this is a “safety” bit to guard against an
errant host.
Endpoint 0 has no disable bit because as the default CONTROL endpoint it must always be
active.
15

EP2INAK
Meaning: Endpoint 2-IN NAK
Location: PINCTL.6
Set: The SIE sets this bit when the EP2-IN endpoint receives an IN request and the
SIE returns the NAK handshake.
Clear: The CPU clears this bit by writing a 1 to it.
POR: EP2INAK=0
Chip Reset: EP2INAK=0
Bus Reset: EP2INAK=0
Pwr Down: Read-write
Programming Notes:
This bit may be polled to discover that the host is asking for IN data which is not yet available
from an IN endpoint because the CPU has not yet loaded and armed the endpoint. This bit is not
included in the interrupt system.
Note: The EP2INAK bit is informational only. It is normally not used by USB device firmware.
16