MaxLinear XR17V354 User manual

MaxLinear Confidential
TBD/18 001UMR00 i
• www.maxlinear.com • 001UMR00
XR17V354 and XR17V358
Evaluation Board User Manual

XR17V354 and XR17V358 Evaluation Board User Manual Revision History
November 2018 001UMR00 ii
Revision History
Document No. Release Date Change Description
1.0.1 June 2011 Legacy Exar EVB Manual
001UMR00 November 2018 For updated board - complete re-write.

XR17V354 and XR17V358 Evaluation Board User Manual Table of Contents
November 2018 001UMR00 iii
Table of Contents
Introduction......................................................................................................................................................... 1
Reference Documentation ................................................................................................................................. 1
Ordering Information.......................................................................................................................................... 3
Evaluation Board Overview ............................................................................................................................... 4
MPIO Connections: .......................................................................................................................................................4
SPI Interface:.................................................................................................................................................................4
Transceiver Control Connections: .................................................................................................................................6
System Set-Up / Powering Up ........................................................................................................................... 7
Jumpers.........................................................................................................................................................................7
Pin-out Connectors........................................................................................................................................................7
MPIO Pins and Test Points ...........................................................................................................................................9
Power ............................................................................................................................................................................9
Software ........................................................................................................................................................................9
Software Drivers...................................................................................................................................................9
Windows Device Manager / Port Settings Tab...................................................................................................10
XR17V354 and XR17V358 EVB Schematics ................................................................................................... 11
XR17V354EVB / XR17V358EVB PCB............................................................................................................... 12
XR17V354 / XR17V358 EVB Bill of Materials .................................................................................................. 13

XR17V354 and XR17V358 Evaluation Board User Manual List of Figures
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List of Figures
Figure 1: Top View of the XR17V358IB-E8-EVB.................................................................................................. 1
Figure 2: Bottom View of the XR17V358IB-E8-EVB............................................................................................. 2
Figure 3: Top View of the XR17V358IB-0A-EVB.................................................................................................. 2
Figure 4: Bottom View of the XR17V358IB-0A-EVB............................................................................................. 2
Figure 5: PCIe and Expansion Interface............................................................................................................... 4
Figure 6: XR17V358IB-E8-EVB Block Diagram ................................................................................................... 5
Figure 7: DB68 Connector.................................................................................................................................... 7
Figure 8: Device Manager / Port Setting tab example ........................................................................................ 10
Figure 9: XR17V354 / XR17V358 EVB Top Silkscreen...................................................................................... 12

XR17V354 and XR17V358 Evaluation Board User Manual List of Tables
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List of Tables
Table 1: Evaluation Board Ordering Part Number ................................................................................................ 3
Table 2: XRA1405 to SP339 Connections............................................................................................................ 6
Table 3: Factory Settings...................................................................................................................................... 7
Table 4: DB68 Pin-out .......................................................................................................................................... 8
Table 5: RS485/422 Headers for Each Channel .................................................................................................. 8
Table 6: RS485/422 Header Pin-Out................................................................................................................... 8
Table 7: Test Points.............................................................................................................................................. 9
Table 8: XR17V358IB-0A-EVB Bill of Materials................................................................................................. 13
Table 9: XR17V358IB-E8-EVB Bill of Materials.................................................................................................. 15
Table 10: XR17V354IB-0A-EVB Bill of Materials................................................................................................ 17

XR17V354 and XR17V358 Evaluation Board User Manual Introduction
November 2018 001UMR00 1
Introduction
The XR17V354 and XR17V358 evaluation boards provide a platform to evaluate the features and performance of the
XR17V354 and XR17V358. The XR17V354 and XR17V358 are 4-channel and 8-channel PCIe UARTs, respectively. They
are available in the same package and are pin compatible, therefore they utilize the same evaluation board. The evaluation
board revision is 4.0. This user manual gives an overview of the evaluation board and its available configurations. The
available configurations are summarized in the ordering information section.
Please refer to the XR17V354 and XR17V358 datasheets for additional information about these devices.
Reference Documentation
Please refer to the XR17V354 and XR17V358 datasheets for additional information about these devices.
Figure 1: Top View of the XR17V358IB-E8-EVB

XR17V354 and XR17V358 Evaluation Board User Manual Reference Documentation
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Figure 2: Bottom View of the XR17V358IB-E8-EVB
Figure 3: Top View of the XR17V358IB-0A-EVB
Figure 4: Bottom View of the XR17V358IB-0A-EVB

XR17V354 and XR17V358 Evaluation Board User Manual Ordering Information
November 2018 001UMR00 3
Ordering Information
1. Refer to www.exar.com/XR17V354 and www.exar.com/XR17V358 for most up-to-date Ordering Information.
Table 1: Evaluation Board Ordering Part Number
Evaluation Board Description
XR17V354IB-0A-EVB A single 4-channel XR17V354 PCIe UART and four SP339 Transceivers are installed.
XR17V354IB-E4-EVB Two 4-channel XR17V354 PCIe UARTs and eight SP339 Transceivers are installed in a master / slave
configuration.
XR17V354IB-E8-EVB A master 4-channel XR17V354 PCIe UART, a slave 8-channel XR17V358 PCIe UART and twelve SP339
Transceivers are installed.
XR17V358IB-0A-EVB A single 8-channel XR17V358 PCIe UART and eight SP339 Transceivers are installed.
XR17V358IB-E4-EVB A master 8-channel XR17V358 PCIe UART, a slave 4-channel XR17V354 PCIe UART and twelve SP339
Transceivers are installed.
XR17V358IB-E8-EVB Two 8-channel XR17V358 PCIe UARTs and sixteen SP339 Transceivers are installed in a master / slave
configuration.

XR17V354 and XR17V358 Evaluation Board User Manual Evaluation Board Overview
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Evaluation Board Overview
This evaluation board has a x1 PCIe connector and will work in any x1, x4 or x16 PCI slot. Up to 16 UART ports can be
tested on this evaluation board when 2 XR17V358 are installed. The PCI interface of the master device is connected
directly to the PCIe connector. The master device communicates with the slave device via MaxLinear’s proprietary
expansion interface, illustrated in Figure 5. The PCIe interface on the slave device is not used and should be unconnected.
Figure 5: PCIe and Expansion Interface
With the configuration shown below, the XR17V35x Windows device driver allows the Device Manager / Port Settings tab
to control the transceiver modes, slew and termination settings. A block diagram of the XR17V358IB-E8-EVB that uses this
configuration is shown in Figure 6. The device Manager / Port Settings tab is shown in Figure 8.
MPIO Connections:
MPIO3 of both XR17V35x master and slave are pulled-up. Optionally, they connect to the EN pins of their respective
transceivers.
MPIO1 of master XR17V35x is connected to CS of first XRA1405
MPIO2 of master XR17V35x is connected to CS of second XRA1405
MPIO1 of slave XR17V35x is connected to CS of third XRA1405
MPIO2 of slave XR17V35x is connected to CS of fourth XRA1405
Optional: MPIO3 of master is connected to EN pin of transceivers on master ports and MPIO3 of slave is connected to EN
pin of transceivers on slave ports. These MPIO3 pins are pulled up and the Port Settings tab cannot be used to disable the
transceivers.
SPI Interface:
EECK pin of master XR17V35x is connected to SCL pin of all XRA1405
EEDI pin of master XR17V35x is connected to SI pin of all XRA1405
EEDO pin of master XR17V35x is connected to SO pin of all XRA1405
XR17V358/354
(Master)
XR17V358/354
(Slave)
CLK+
CLK-
RX+
RX-
TX+
TX-
D[7:0]
CLK
INT
SEL
MODE
PRES
MODE
PRES
X
R17V358/35
4
(
Master
)
XR17V358/354
(Master)
X
R17V358/354
(
Slave
)
XR17V358/354
(Slave)
CLK+
CLK-
RX+
RX-
TX+
TX-
D[7:0]
CLK
INT
SEL
MODE
PRES
MODE
PRES
3.3V
PCIe Bus
Expansion
Interface

XR17V354 and XR17V358 Evaluation Board User Manual SPI Interface:
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Figure 6: XR17V358IB-E8-EVB Block Diagram
PCIe
Bus
Expansion
Interface
Expansion
Interface
XR17V358
Master
XRA1405
XRA1405
Ch 1 SP339
Ch 3 SP339
UART
Channels
1-8
UART
Channels
9-16
EN
TERM
SLEW
MODE1 MODE0
P0-4
P4-7
P8-11
P12-15
Ch 2 SP339
EN
TERM
SLEW
MODE1 MODE0
CS
EN
TERM
SLEW
MODE1 MODE0
Ch 4 SP339
EN
TERM
SLEW
MODE1 MODE0
SPI
Interface
3.3V
EN_M
EN_M
EN_M
EN_M
EN_M
CS Ch 5 SP339 Ch 6 SP339
Ch 7 SP339 Ch 8 SP339
Ch 9 SP339 Ch 10 SP339
Ch 11 SP339 Ch 12 SP339
Ch 13 SP339 Ch 14 SP339
Ch 15 SP339 Ch 16 SP339
CS
CS
EN_S
(Ch 9-16)
To DB68
EECK
EEDI
EEDO
MPIO4-15
MPIO3
MPIO2
MPIO1
MPIO4-15
MPIO3
MPIO2
MPIO1
SCL
SI
SO
XRA1405
XRA1405
3.3V
Expansion
Interface
XR17V358
Slave
UART
Channels
9-16
MPIO4-15
MPIO3
MPIO2
MPIO1