MEDIATEK MT6252 Guide

MT6252MT6252 DesignDesign NoticeNotice
V0.1
2010/12/10
Copyright © MediaTek Inc. All rights reserved.

Baseband design noticeBaseband design notice
Copyright © MediaTek Inc. All rights reserved.

MT6252 Design notice Quick ViewMT6252 Design notice Quick View
Function
MT6253
MT6252
Importance Quick view
Function
MT6253
MT6252
Importance
Quick
view
BB 2 HW trapping pins 3 HW trapping pins 1.Pin HW notice
2.SRCLKENAI notice
Memory ADMUX NOR+PSRAM Serial Flash 1.Pin connection
PMU BackLight with booster BackLight with VBAT 1.Low bat LCM flicker
Charge
r
Linear charge
r
Pulse charge
r
1.Pulse charge
r
2.Important SW setting
3.Nokia Charger support
Adi
Cl
D/AB
A
Cl
AB A
12
i1 li ti
A
u
di
o
Cl
ass-
D
/
AB
A
mp
Cl
ass-
AB
A
mp
1
.
2
i
n
1
app
li
ca
ti
on
2. Important part placement
Speech SW algorithm Same with 53 1. Important part placement
Camera 2M VGA 1.Reference design
LCM 2.8V IO LCM 1.8V IO LCM 1. 1.8V IO LCM
MSDC 4 bit IO 1 bit IO 1.IOT
2.DAT3 as Card detect
RF Quad band SOC Same with 53 1.Schematic notice
2011/1/17Copyright © MediaTek Inc. All rights reserved. 2
2.Layout notice
3.BPI modification

Placement noticePlacement notice
TXM(PRF88144B)
+Rx SAWs
26MHz crystal ,
must close to BB
MT6252 SOC
C-load,
Must close 32.768KHz
Serial Flash ,
32.768KHz crystal ,
must close to BB
must close to BB
2008/06Copyright © MediaTek Inc. All rights reserved. 3

MT6252 Chip configuration design notice (BB)MT6252 Chip configuration design notice (BB)
1.1.TESTMODETESTMODE(Pin(Pin J6) should be connected to ground.J6) should be connected to ground.
2.2.PMU_TESTMODEPMU_TESTMODE(Pin(Pin H5) should be connected to ground.H5) should be connected to ground.
3.3.VMSELVMSEL(Pin J3) should be connected to ground.(Pin J3) should be connected to ground.
2011/1/17Copyright © MediaTek Inc. All rights reserved. 4

MT6252 Chip configuration design notice (BB)MT6252 Chip configuration design notice (BB)
1.There should be a 100K ohm resistor connected to ground on1.There should be a 100K ohm resistor connected to ground on PWMPWM if PWM isif PWM is
used.used.
2.You can connect2.You can connect PWMPWM to
g
round directl
y
if PWM is not used. But
p
leaseto
g
round directl
y
if PWM is not used. But
p
lease
2011/1/17Copyright © MediaTek Inc. All rights reserved. 5
gy pgy p
must configure this as GPIO input mode and pull up should not be enabled.must configure this as GPIO input mode and pull up should not be enabled.

MT6252 Chip configuration design notice (BB)MT6252 Chip configuration design notice (BB)
1.There should be a 100K ohm resistor connected to VIO on DAIRST and DAISYNC.1.There should be a 100K ohm resistor connected to VIO on DAIRST and DAISYNC.
2.You can connect2.You can connect DAIRST and DAISYNCDAIRST and DAISYNC to VIO directly if these 2 pin areto VIO directly if these 2 pin are
t d f th f ti B t l t fi thi GPIOt d f th f ti B t l t fi thi GPIO
2011/1/17Copyright © MediaTek Inc. All rights reserved. 6
no
t
use
d
f
or any o
th
er
f
unc
ti
on.
B
u
t
p
l
ease mus
t
con
fi
gure
thi
s as
GPIO
no
t
use
d
f
or any o
th
er
f
unc
ti
on.
B
u
t
p
l
ease mus
t
con
fi
gure
thi
s as
GPIO
input mode and pull down should not be enabled.input mode and pull down should not be enabled.

MT6252 Chip configuration design notice (BB)MT6252 Chip configuration design notice (BB)
1V81V8
1.1.VM_SELVM_SEL connected to groundconnected to ground ÎÎ VM = 1.8V.VM = 1.8V.
MT6252 onl
y
su
pp
ort 1.8V memor
y
. VMSEL should alwa
y
s be low.MT6252 onl
y
su
pp
ort 1.8V memor
y
. VMSEL should alwa
y
s be low.
ypp y yypp y y
2011/1/17Copyright © MediaTek Inc. All rights reserved. 7

MT6252 Chip configuration design notice (BB)MT6252 Chip configuration design notice (BB)
1.1.FSOURCEFSOURCE should be connected to ground.should be connected to ground.
2011/1/17Copyright © MediaTek Inc. All rights reserved. 8

MT6252 Chip configuration design notice (MSDC)MT6252 Chip configuration design notice (MSDC)
1.MT6252 only support 1 bit MSDC. If1.MT6252 only support 1 bit MSDC. If DAT3 is not used as card detectionDAT3 is not used as card detection , DAT1~3, DAT1~3 onon
memory card socket side should be pulled to VIO by 47Kohmmemory card socket side should be pulled to VIO by 47Kohm
memory
card
socket
side
should
be
pulled
to
VIO
by
47Kohm
.
memory
card
socket
side
should
be
pulled
to
VIO
by
47Kohm
.
2.You also can enable internal pull up but reserving SMT space for external pull2.You also can enable internal pull up but reserving SMT space for external pull
up resistors is recommended.up resistors is recommended.
2011/1/17Copyright © MediaTek Inc. All rights reserved. 9

MT6252 Chip configuration design notice(4 SIM)MT6252 Chip configuration design notice(4 SIM)
Not used but still need bypassNot used but still need bypass
Not
used
but
still
need
bypass
Not
used
but
still
need
bypass
capacitors.capacitors.
Power of SIM comes from 6302Power of SIM comes from 6302
1. Please remember to add bypass capacitors on VSIM1 and VSIM2 even1. Please remember to add bypass capacitors on VSIM1 and VSIM2 even
th 2 LDO t d ith 2 LDO t d i
4 SIM li ti4 SIM li ti
2011/1/17Copyright © MediaTek Inc. All rights reserved. 10
th
ese
2
LDO
s are no
t
use
d
i
n
th
ese
2
LDO
s are no
t
use
d
i
n
4
SIM
app
li
ca
ti
on
4
SIM
app
li
ca
ti
on..

MT6252 Chip configuration design notice (MT6252 Chip configuration design notice (SRCLKENAISRCLKENAI))
1. Please remember1. Please remember to enable internal Pull downto enable internal Pull down when this pin is used as 26MHz clockwhen this pin is used as 26MHz clock
request from 6252 (In general this is used by BT)request from 6252 (In general this is used by BT)
request
from
6252
.
(In
general
,
this
is
used
by
BT)request
from
6252
.
(In
general
,
this
is
used
by
BT)
2011/1/17Copyright © MediaTek Inc. All rights reserved. 11

Memory design noticeMemory design notice
Copyright © MediaTek Inc. All rights reserved.

EMI andEMI and NandNand interface difference between MT6253/53D and MT6252interface difference between MT6253/53D and MT6252
MT6253 MT6253D MT6252
Interface
NOR+PSRAM NOR+PSRAM Serial Flash with
stacked PSRAM
Mode
1.Async
2.Sync Burst
1.Async
2.Sync Burst Sync QPI
Clock Rate
104MHz
52MHz
Serial Flash : 78MHz / 104MHz
Clock
Rate
104MHz
52MHz
PSRAM : 104MHz
EMI voltage
1.8V 1.8V 1.8V
1.MT6252 support 78MHz and 104MHz QPI mode Serial Flash.1.MT6252 support 78MHz and 104MHz QPI mode Serial Flash.
2.The power domain2.The power domain of Serial flash is same as internal stackedof Serial flash is same as internal stacked PSRAM.SoPSRAM.So , please use, please use
1.8V serial flash instead of 3V.1.8V serial flash instead of 3V.
2011/1/17Copyright © MediaTek Inc. All rights reserved. 13

MT6252 Chip memory configuration design noticeMT6252 Chip memory configuration design notice
1V81V8
62526252
Serial FlashSerial Flash
(tb18V)(tb18V)
62526252
(
mus
t
b
e
1
.
8V)(
mus
t
b
e
1
.
8V)
Please connect the pins according to following table.Please connect the pins according to following table.
6252 Serial flash
SHOLD DQ3
SSWP DQ2
SIN DQ1
SOUT DQ0
SCS Chip enable
SCK
CLK
Interface
2011/1/17Copyright © MediaTek Inc. All rights reserved. 14
SCK
CLK
EN25S64 U1006 / EN25S64
64M 1.8v EON
Contact: Bull Tang
[email protected] 13502888931

MT6252 Memory Layout design noticeMT6252 Memory Layout design notice
MT6252MT6252
Serial FlashSerial Flash
Memory should be placed as close to MT6252 as possible.Memory should be placed as close to MT6252 as possible.
2011/1/17Copyright © MediaTek Inc. All rights reserved. 15

MT6252 Memory Layout design noticeMT6252 Memory Layout design notice
There are 2
p
acka
g
es
(
There are 2
p
acka
g
es
(
WSON and TSOPWSON and TSOP
)
on serial flash.
)
on serial flash.
WSONWSON TSOPTSOP
pg(pg(
))
It’s recommended that these 2 packages should be reserved on your PCB.It’s recommended that these 2 packages should be reserved on your PCB.
Their pins are fully compatible but pin locations are slightly shifted.Their pins are fully compatible but pin locations are slightly shifted.
Please overlap the pins for SMT compatible.Please overlap the pins for SMT compatible.
2011/1/17Copyright © MediaTek Inc. All rights reserved. 16

MT6252 Memory Layout design noticeMT6252 Memory Layout design notice
The traces of memory should not be crossed by other traces or power.The traces of memory should not be crossed by other traces or power.
(Nice to have)(Nice to have)
2011/1/17Copyright © MediaTek Inc. All rights reserved. 17

MT6252 Memory Layout design noticeMT6252 Memory Layout design notice
MT6252MT6252
Ground
p
laneGround
p
lane
6565
pp
Serial FlashSerial Flash
There should be a ground plane beneath the Serial Flash and QPI traces ofThere should be a ground plane beneath the Serial Flash and QPI traces of
MT6252 (Ni t h )MT6252 (Ni t h )
2011/1/17Copyright © MediaTek Inc. All rights reserved. 18
MT6252
.
(Ni
ce
t
o
h
ave
)
MT6252
.
(Ni
ce
t
o
h
ave
)

MT6252 PMU Design NoticeMT6252 PMU Design Notice
2010/12
Copyright © MediaTek Inc. All rights reserved.