Cypress CY62146DV30 User manual

4-Mbit (256K x 16) Static RAM
CY62146DV30
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05339 Rev. *A Revised February 2, 2005
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62146CV30
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA and 44-pin TSOPII
• Also available in Lead-free packages
Functional Description[1]
The CY62146DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0through
I/O15) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8through I/O15) is written into the location
specified on the address pins (A0through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62146DV30 is available in a 48-ball VFBGA, 44-pin
TSOPII packages.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
256K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12 A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BLE
BHE
A16
A0
A1
A17
A9
A
10
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CY62146DV30
Document #: 38-05339 Rev. *A Page 2 of 11
Notes:
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating or tied to VSS to ensure proper application.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA= 25°C.
Pin Configuration[2, 3, 4]
VFBGA (Top View) 44 TSOP II (Top View)
WE
A11
A10
A6
A0
A3CE
I/O
10
I/O
8
I/O
9
A4
A5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A9
A8
OE
Vss
A7
I/O
0
BHE
NC
A17
A2
A1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5I/O
6
I/O
7
A15
A14
A13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
DNU
Vcc
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
VCC
A17
A16
A15
A14
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21
23
24
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A13 A12
NC
Product Portfolio
Product
VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA)
Standby ISB2 (µA)f = 1MHz f = fmax
Min. Typ.[5] Max. Typ.[5] Max. Typ.[5] Max. Typ.[5] Max.
CY62146DV30L 2.20V 3.0 3.60 45 1.5 3 10 20 2 12
CY62146DV30LL 8
CY62146DV30L 2.20V 3.0 3.60 55 1.5 3 8 15 2 12
CY62146DV30LL 8
CY62146DV30L 2.20V 3.0 3.60 70 1.5 3 8 15 2 12
CY62146DV30LL 8
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CY62146DV30
Document #: 38-05339 Rev. *A Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground
Potential......................................–0.3V to + VCC(MAX) + 0.3V
DC Voltage Applied to Outputs
in High-Z State[6, 7].........................–0.3V to VCC(MAX) + 0.3V
DC Input Voltage[6, 7] .....................–0.3V to VCC(MAX) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
Device Range
Ambient Tem-
perature (TA)V
CC[8]
CY62146DV30L Industrial –40°C to +85°C 2.20V to 3.60V
CY62146DV30LL
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
CY62146DV30-45 CY62146DV30-55 CY62146DV30-70
UnitMin. Typ.[5] Max. Min. Typ.[5] Max. Min. Typ.[5] Max.
VOH Output HIGH
Voltage
IOH = –0.1 mA VCC = 2.20V 2.0 2.0 2.0 V
IOH = –1.0 mA VCC = 2.70V 2.4 2.4 2.4 V
VOL Output LOW
Voltage IOL = 0.1 mA VCC = 2.20V 0.4 0.4 0.4 V
IOL = 2.1 mA VCC = 2.70V 0.4 0.4 0.4 V
VIH Input HIGH
Voltage
VCC = 2.2V to 2.7V 1.8 VCC +
0.3V
1.8 VCC +
0.3V
1.8 VCC +
0.3V
V
VCC= 2.7V to 3.6V 2.2 VCC +
0.3V
2.2 VCC +
0.3V
2.2 VCC +
0.3V
V
VIL Input LOW
Voltage
VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 –0.3 0.6 V
VCC= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Leakage
Current
GND < VI< VCC –1 +1 –1 +1 –1 +1 µA
IOZ Output
Leakage
Current
GND < VO <VCC, Output
Disabled
–1 +1 –1 +1 –1 +1 µA
ICC VCC
Operating
Supply
Current
f = fMAX =
1/tRC
VCC = VCCmax
IOUT = 0 mA
CMOS levels
10 20 8 15 8 15 mA
f = 1 MHz 1.5 3 1.5 3 1.5 3 mA
ISB1 Automatic
CE
Power-down
Current —
CMOS
Inputs
CE > VCC−0.2V,
VIN>VCC–0.2V, VIN<0.2V)
f = fMAX (Address and Data
Only),
f = 0 (OE, WE, BHE and
BLE), VCC = 3.60V
L212 212 212µA
LL 8 8 8
ISB2 Automatic
CE
Power-down
Current —
CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN <
0.2V,
f = 0, VCC = 3.60V
L212 212 212µA
LL 8 8 8
Notes:
6. VIL(min.) = –2.0V for pulse durations less than 20 ns.
7. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
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Document #: 38-05339 Rev. *A Page 4 of 11
Capacitance (for all packages)[9]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Thermal Resistance[9]
Parameter Description Test Conditions BGA TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
72 75.13 °C/W
ΘJC Thermal Resistance
(Junction to Case)
8.86 8.95 °C/W
AC Test Loads and Waveforms[10]
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.[5] Max. Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current VCC= 1.5V
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
L9µA
LL 6
tCDR[9] Chip Deselect to Data Retention Time 0 ns
tR[11] Operation Recovery Time tRC ns
VCC
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Data Retention Waveform
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Test condition for the 45 ns part is a load capacitance of 30 pF.
11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
VCC
CE
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CY62146DV30
Document #: 38-05339 Rev. *A Page 5 of 11
Switching Characteristics Over the Operating Range [12]
Parameter Description
45 ns[10] 55 ns 70 ns
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 45 55 70 ns
tAA Address to Data Valid 45 55 70 ns
tOHA Data Hold from Address Change 10 10 10 ns
tACE CE LOW to Data Valid 45 55 70 ns
tDOE OE LOW to Data Valid 25 25 35 ns
tLZOE OE LOW to LOW Z[13] 55 5ns
tHZOE OE HIGH to High Z[13, 14] 15 20 25 ns
tLZCE CE LOW to Low Z[13] 10 10 10 ns
tHZCE CE HIGH to High Z[13, 14] 20 20 25 ns
tPU CE LOW to Power-Up 0 0 0 ns
tPD CE HIGH to Power-Down 45 55 70 ns
tDBE BLE/BHE LOW to Data Valid 25 25 35 ns
tLZBE BLE/BHE LOW to Low Z[13] 10 10 10 ns
tHZBE BLE/BHE HIGH to HIGH Z[13, 14] 15 20 25 ns
Write Cycle[15]
tWC Write Cycle Time 45 55 70 ns
tSCE CE LOW to Write End 40 40 60 ns
tAW Address Set-up to Write End 40 40 60 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-up to Write Start 0 0 0 ns
tPWE WE Pulse Width 35 40 45 ns
tBW BLE/BHE LOW to Write End 40 40 60 ns
tSD Data Set-up to Write End 25 25 30 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE WE LOW to High-Z[13, 14] 15 20 25 ns
tLZWE WE HIGH to Low-Z[13] 10 10 10 ns
Notes:
12. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2,
input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedence state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
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CY62146DV30
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Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[16, 17]
Read Cycle No. 2 (OE Controlled)[17, 18]
Notes:
16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE t
LZOE
ADDRESS
t
DBE
t
DOE
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CY62146DV30
Document #: 38-05339 Rev. *A Page 7 of 11
Write Cycle No. 1 (WE Controlled)[15, 19, 20]
Write Cycle No. 2 (CE Controlled)[15, 19, 20]
Notes:
19. Data I/O is high impedance if OE = VIH.
20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
21. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN
NOTE 21
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
DATAIN
CE
ADDRESS
WE
DATA I/O
OE
NOTE 21
BHE/BLE tBW
tSA
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Document #: 38-05339 Rev. *A Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW)[20]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[20]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 21
tBW
BHE/BLE
DATA I/O
ADDRESS
t
SD
t
SA
t
HA
t
AW
tWC
CE
WE
DATA
IN
NOTE 21
t
BW
BHE/BLE
tSCE
t
PWE
tHZWE tHD
tLZWE
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Document #: 38-05339 Rev. *A Page 9 of 11
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
L X X H H High Z Output Disabled Active (ICC)
L H L L L Data Out (I/OO–I/O15) Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15) Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
45 CY62146DV30LL-45BVI BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial
CY62146DV30LL-45BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free)
CY62146DV30LL-45ZSXI ZS-44 44-pin TSOP II (Pb-free)
55 CY62146DV30L-55BVI BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial
CY62146DV30L-55BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30LL-55BVI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
CY62146DV30LL-55BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30L-55ZSXI ZS-44 44-pin TSOP II (Pb-free)
CY62146DV30LL-55ZSXI
70 CY62146DV30L-70BVI BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial
CY62146DV30L-70BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30LL-70BVI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
CY62146DV30LL-70BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30L-70ZSXI ZS-44 44-pin TSOP II (Pb-free) Industrial
CY62146DV30LL-70ZSXI
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CY62146DV30
Document #: 38-05339 Rev. *A Page 10 of 11
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
44-Pin TSOP II ZS44
51-85087-*A
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