Microchip Technology USB5744 User manual

2015-2017 Microchip Technology Inc. DS00001855E-page 1
Highlights
• USB Hub Feature Controller IC with 4 USB 3.1
Gen 1 / USB 2.0 downstream ports
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• USB Link Power Management (LPM) support
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• Available in 56-pin (7 x 7 mm) VQFN lead-free,
RoHS compliant package
• Commercial and industrial grade temperature
support
• Configuration Straps: Predefined configuration of
system level functions
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• Multi-function USB 3.1 Gen 1 Peripherals
Key Benefits
• USB 3.1 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps and 1.5 Mbps operation
- 5 V tolerant USB 2.0 pins
- 1.32 V tolerant USB 3.1 Gen 1 pins
- Integrated termination & pull-up/pull-down resistors
• Supports per port battery charging of most popu-
lar battery powered devices
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
-Apple
portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Support for Microchip USC100x family of battery
charging controllers
- Supports additional portable devices
• Smart port controller operation
- Firmware handling of companion port controllers
• On-chip microcontroller
- Manages I/Os, VBUS, and other signals
• 8 KB RAM, 64 KB ROM
• 8 KB One Time Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM, SPI
ROM, or SMBus
•PortSwap
- Configurable differential intro-pair signal swapping
•PHYBoost
™
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense™
- Programmable USB receiver sensitivity
• Compatible with Microsoft Windows 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and
low thermal dissipation
• Package
- 56-pin VQFN (7 x 7 mm)
• Environmental
- 3 kV HBM JESD22-A114F ESD protection
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
USB5744
4-Port SS/HS USB Controller Hub

USB5744
DS00001855E-page 2 2015-2017 Microchip Technology Inc.
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2015-2017 Microchip Technology Inc. DS00001855E-page 3
USB5744
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 6
3.0 Pin Description and Configuration .................................................................................................................................................. 8
4.0 Device Connections ...................................................................................................................................................................... 17
5.0 Modes of Operation ...................................................................................................................................................................... 19
6.0 Device Configuration ..................................................................................................................................................................... 22
7.0 Device Interfaces .......................................................................................................................................................................... 23
8.0 Functional Descriptions ................................................................................................................................................................. 24
9.0 Operational Characteristics ........................................................................................................................................................... 30
10.0 Package Information ................................................................................................................................................................... 39

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1.0 PREFACE
1.1 General Terms
TABLE 1-1: GENERAL TERMS
Term Description
ADC Analog-to-Digital Converter
Byte 8 bits
CDC Communication Device Class
CSR Control and Status Registers
DWORD 32 bits
EOP End of Packet
EP Endpoint
FIFO First In First Out buffer
FS Full-Speed
FSM Finite State Machine
GPIO General Purpose I/O
HS Hi-Speed
HSOS High Speed Over Sampling
Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2CInter-Integrated Circuit
LS Low-Speed
lsb Least Significant Bit
LSB Least Significant Byte
msb Most Significant Bit
MSB Most Significant Byte
N/A Not Applicable
NC No Connect
OTP One Time Programmable
PCB Printed Circuit Board
PCS Physical Coding Sublayer
PHY Physical Layer
PLL Phase Lock Loop
RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK Software Development Kit
SMBus System Management Bus
UUID Universally Unique IDentifier
WORD 16 bits

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USB5744
1.2 Reference Documents
1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
2. Universal Serial Bus Revision 3.1 Specification, http://www.usb.org
3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
4. I2C-Bus Specification, Version 1.1, http://www.nxp.com
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs

USB5744
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2.0 INTRODUCTION
2.1 General Description
The Microchip USB5744 hub is low-power, OEM configurable, USB 3.1 Gen 1 hub feature controller with 4 downstream
ports and advanced features for embedded USB applications. The USB5744 is fully compliant with the Universal Serial
Bus Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB5744 supports 5 Gbps
SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB down-
stream devices on all enabled downstream ports.
The USB5744 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub feature controller that is
the culmination of five generations of Microchip hub feature controller design and experience with proven reliability,
interoperability, and device compatibility. The SuperSpeed hub feature controller operates in parallel with the USB 2.0
controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5744 supports downstream battery charging. The USB5744 integrated battery charger detection circuitry sup-
ports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5744 provides the bat-
tery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A with data)
• Custom profiles loaded via SMBus or OTP
Additionally, the USB5744 includes many powerful and unique features such as:
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
The USB5744 can be configured for operation through internal default settings. Custom OEM configurations are sup-
ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5744 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5744 is shown in Figure 2-1.

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USB5744
FIGURE 2-1: INTERNAL BLOCK DIAGRAM

USB5744
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3.0 PIN DESCRIPTION AND CONFIGURATION
3.1 Pin Assignments
Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configurations
traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Config-
uration Straps and Programmable Functions" for additional information.
FIGURE 3-1: 56-VQFN PIN ASSIGNMENTS
Note:Exposed pad(VSS) on bottomof package must be connected to ground with a via field.
(Connectexposed pad to ground with a via field)
VSS
USB5744
56-VQFN
(Top View)
4
5
6
7
8
9
10
11
18 19 20 21 22 23 24 25
39
38
37
36
35
34
33
32
53 52 51 50 49 48 47 46
USB3DN_RXDM1
USB3DN_RXDP1
USB2DN_DP2/PRT_DIS_P2
USB2DN_DM2/PRT_DIS_M2
USB3DN_TXDP2
USB3DN_TXDM2
VDD12
USB3DN_RXDP2
SPI_CE_N/CFG_NON_REM
SPI_DI/CFG_BC_EN
SPI_CLK/SMCLK
VDD12
VDD33
USB3DN_RXDM4
USB3UP_RXDP
VDD12
VDD12 USB3UP_RXDM USB3UP_TXDM
USB2DN_DM4/PRT_DIS_M4
USB3DN_RXDP3 USB3DN_TXDP3
USB2DN_DM3/PRT_DIS_M3
USB2DN_DP3/PRT_DIS_P3
VDD33
USB2UP_DP
VBUS_DET
USB2UP_DM
USB3DN_TXDP4
USB3UP_TXDP
VDD12
SPI_DO/SMDAT
45 44 55 54
2
3
12
13
16 17 26 27
31
30
41
40
USB3DN_TXDM3 USB3DN_RXDM3
USB2DN_DP4/PRT_DIS_P4
USB3DN_TXDM4
VDD12
USB3DN_TXDM1
USB3DN_TXDP1
USB2DN_DM1/PRT_DIS_M1
ATEST XTALO XTALI/CLK_IN VDD33
PRT_CTL1
PRT_CTL2
PRT_CTL3
PRT_CTL4/GANG_PWR
1
USB2DN_DP1/PRT_DIS_P1
14USB3DN_RXDM2
15
VDD12 VDD12 28
29 USB3DN_RXDP4
RESET_N
42
43
VDD33 RBIAS
56

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USB5744
Table 3-1 details the package pin assignments in table format.
TABLE 3-1: 56-VQFN PIN ASSIGNMENTS
Pin
Number Pin Name Pin Number Pin Name
1USB2DN_DP1/PRT_DIS_P1 29 USB3DN_RXDP4
2USB2DN_DM1/PRT_DIS_M1 30 USB3DN_RXDM4
3USB3DN_TXDP1 31 VDD33
4USB3DN_TXDM1 32 PRT_CTL4/GANG_PWR
5VDD12 33 VDD12
6USB3DN_RXDP1 34 PRT_CTL3
7USB3DN_RXDM1 35 PRT_CTL2
8USB2DN_DP2/PRT_DIS_P2 36 PRT_CTL1
9USB2DN_DM2/PRT_DIS_M2 37 VBUS_DET
10 USB3DN_TXDP2 38 SPI_CLK/SMCLK
11 USB3DN_TXDM2 39 SPI_DO/SMDAT
12 VDD12 40 SPI_DI/CFG_BC_EN
13 USB3DN_RXDP2 41 SPI_CE_N/CFG_NON_REM
14 USB3DN_RXDM2 42 RESET_N
15 VDD12 43 VDD12
16 VDD33 44 VDD33
17 USB2DN_DP3/PRT_DIS_P3 45 USB2UP_DP
18 USB2DN_DM3/PRT_DIS_M3 46 USB2UP_DM
19 USB3DN_TXDP3 47 USB3UP_TXDP
20 USB3DN_TXDM3 48 USB3UP_TXDM
21 VDD12 49 VDD12
22 USB3DN_RXDP3 50 USB3UP_RXDP
23 USB3DN_RXDM3 51 USB3UP_RXDM
24 USB2DN_DP4/PRT_DIS_P4 52 ATEST
25 USB2DN_DM4/PRT_DIS_M4 53 XTALO
26 USB3DN_TXDP4 54 XTALI/CLK_IN
27 USB3DN_TXDM4 55 VDD33
28 VDD12 56 RBIAS

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3.2 Pin Descriptions
This section contains descriptions of the various USB5744 pins. This pin descriptions have been broken into functional
groups as follows:
•USB 3.1 Gen 1 Pin Descriptions
•USB 2.0 Pin Descriptions
•USB Port Control Pin Descriptions
•SPI/SMBus Pin Descriptions
•Miscellaneous Pin Descriptions
•Power and Ground Pin Descriptions
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “Active high” signals. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-
tive.
Note: The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables. A
description of the buffer types is provided in Section 3.3, "Buffer Types," on page 14.
For additional information on configuration straps and configurable pins, refer to Section 3.4, "Configuration
Straps and Programmable Functions".
TABLE 3-2: USB 3.1 GEN 1 PIN DESCRIPTIONS
Num
Pins Symbol Buffer Type Description
1USB3UP_TXDP IO-U USB 3.1 Gen 1 upstream SuperSpeed transmit data plus.
1USB3UP_TXDM IO-U USB 3.1 Gen 1 upstream SuperSpeed transmit data minus.
1USB3UP_RXDP IO-U USB 3.1 Gen 1 upstream SuperSpeed receive data plus.
1USB3UP_RXDM IO-U USB 3.1 Gen 1 upstream SuperSpeed receive data minus.
4USBDN_TXDP[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed transmit data plus.
4USBDN_TXDM[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed transmit data
minus.
4USBDN_RXDP[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed receive data plus.
4USBDN_RXDM[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed receive data
minus.
TABLE 3-3: USB 2.0 PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1USB2UP_DP IO-U USB 2.0 upstream data plus (D+).
1USB2UP_DM IO-U USB 2.0 upstream data minus (D-).