Micron Technology MT29F1G08ABB Instruction Manual

TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Overview
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Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All
information discussed herein is provided on an “as is” basis, without warranties of any kind.
Technical Note
Boot-from-NAND Using Micron®MT29F1G08ABB NAND Flash
with the Texas Instruments™ (TI) OMAP2420 Processor
Overview
NAND Flash memory devices are designed for applications requiring nonvolatile, high-
density,solid-statestoragemedia.Historically,NANDFlashhasbeenusedextensivelyin
applications such as mass storage cards and digital cameras.With its lowcost and high
performance, NAND Flash is beginning to make its way into more complex embedded
systems where NOR Flash has dominated in the past—for example, in mobile phones.
In complex embedded systems, one of the challenges associated with a change from
NOR Flash to NAND Flash has been the boot process.NOR Flash has been a popular
choice for these systems because it contains a traditional memory interface (including
bothaddressanddatabuses),makingitcapableofexecute-in-place (XIP) operation.XIP
memory enables the system CPU to execute code directly from the memory device
because the boot code is stored on and executed from a single device.
NAND Flash is a page-oriented memory device that does not inherently support XIP, at
least not in the same manner as a typical XIP memory device. Operating system and
boot code can be stored in NAND Flash memory, but the code must be copied (or shad-
owed) to DRAM before it can be executed. This requires system designers to modify the
boot process for their systems when using NAND Flash. The payofffor this modification
isthatthesystembenefitsfromthelowercostofNANDFlashasthestoragesolutionand
the higher performance of DRAM as the XIP memory.

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Scope
Scope
This technical note discusses a boot-from-NAND solution for applications using the
Texas Instruments™ (TI) OMAP2420 processor and the Micron®MT29F1G08ABB
NAND Flash device. The technical note provides a four-stage boot sequence. Stages 1
and2areindependentoftheoperatingsystem(OS);however, theyarehighlydependent
on system hardware. Thus, the primary focus of this technical note is on stage 1 and
stage 2 boot processes.
Additional system details:
• TI OMAP2420 H4 with processor daughter card “Menelaus ES 2.0”;
S/N: 750-0006, Rev C.
• The boot-from-NAND concepts discussed are OS independent; however, the Linux
OS is used as an example in some explanations.
Notethatsecurebootingviathe OMAP™ high-security (HS) deviceisnot in thescope of
this document. However, NAND Flash booting for HS and GP differs only in the genera-
tion of the X-Loader. Thus, the solution discussed here is generally applicable to both
the HS and GP processors.
Terms used in the technical note are provided in Table 1.
Table 1: Glossary of Terms and Abbreviations
Abbreviation Description
ECC Error correction code
GP General purpose OMAP device
GPMC General purpose memory controller
HS High-security OMAP device
ICE TRACE32®in-circuit emulator by Lauterbach, Inc.
JTAG JTAG standard (from the Joint Test Action Group)
OMAP2420 TI processor
OS Operating system
OST tools TI OMAP software tools
TI Texas Instruments™
U-boot Linux OS boot loader
XIP Execute in place
X-Loader Pre-OS bootstrap code

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Boot-from-NAND Overview
Boot-from-NAND Overview
Figure 1 provides an overview of the boot sequence for an OMAP2420-based system
using boot-from-NAND.
Figure 1: Boot-from-NAND Stages
Boot Stages
Stage 1: Processor ROM Code
During power-on, or after a RESET operation, the OMAP2420 processor runs its internal
ROM code. Note that only NAND Flash devices supported by the OMAP2420 processor
ROM can be used for the boot process (see Table 2 on page 4).
Stage 2: Bootstrap
X-Loader is an example of stage 2 bootstrap code. The X-Loader code is stored in the
NAND Flash, and the ROM code copies it to the OMAP processor SRAM for execution.
Stage 3: Boot Loader
Stage 3 is the boot loader, which is used to copy the operating system code from the
NAND Flash to the DRAM; in this case U-Boot is the boot loader code. The U-Boot code
is stored in NAND Flash, and the stage 2 code copies it to the DRAM for execution.
Stage 4: Operating System
The OS code, such as the Linux kernel, is storedin the NAND Flash, and the stage 3 code
copiesit to the DRAM, whereitisexecuted. The boot process is complete after this stage
as the OS takes control of the system.
Stage 4
Operating System
Focus
of this
Technical
Note
Stage 3
Boot Loader
Stage 2
Boot-strap
Stage 1
Processor ROM Code

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 1: Processor ROM Code
If the device ID of the NAND Flash is not supported by the ROM, an attempt is made to
determine the configuration of the NAND Flash device by performing a READ ID2 oper-
ation. Contact yourMicron representative for READ ID2 operation details.If both the
READ ID and READ ID2 operations fail, the ROM code performs a software reset on the
system.
Stage 1: Processor ROM Code
Stage 1 is the execution of the OMAP2420 processor ROM code. This ROM code cannot
be modified by the system designer. Only NAND Flash devices supported by the ROM
code can be used for boot-from-NAND with the OMAP2420 device.If the ROM code
does not support a particular NAND Flash device,contacta TexasInstrumentsrepresen-
tative to determine if additional ROM code is available that will support the Micron
NAND Flash device.
After a power-on-reset is initiated, the ROM code reads the SYS.BOOT register to deter-
mine the memory interface configurationand programs the general-purpose memory
controller(GPMC)accordingly.ThentheROMcodeissuesaRESET(FFh)command(see
Figure 2) tothe NANDFlashdevice, followed byaREADID(90h)command(seeFigure 3
on page 5). The READ ID operation enables theOMAP2420 processor to determine how
the NAND Flash device is configured and whether this device is supported by the ROM
code.
Table 3 shows the required SYS.BOOT register settings to support boot-from-NAND.
Micron NAND Flash devices are available in both x8 and x16 configurations; the Micron
NAND Flash device referenced in this technical note, MT29F1G08ABB, has a x8 inter-
face.
Table 2: Micron NAND Flash Devices Supported by the OMAP2420 Processor
Micron Part Number Density Device ID Bus Width Page Size (bytes)
MT29F1G08ABB 1Gb A1h x8 2,112
MT29F1G16ABB 1Gb B1h x16 2,112
MT29F2G08AAD 2Gb AAh x8 2,112
MT29F2G16AAD 2Gb BAh x16 2,112
Table 3: SYS.BOOT Register
SYS.BOOT[3:0]
Device Type3 2 1 0
1100
x8 NAND Flash
1101
x16 NAND Flash

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 1: Processor ROM Code
Figure 2: NAND Flash Reset (FFh) Command
Figure 3: NAND Flash READ ID Command
Bad Blocks
The ROM code expects the X-Loader to be in block 0, 1, 2, or 3 of the NAND Flash device
and can use any of these blocks in the boot process. After the NAND Flash device config-
uration has been determined, the OMAP2420 processor ROM code performs a bad-
block check on these blocks.
Block 0 of the MT29F1G08ABB device is guaranteed to be goodfor 1,000 PROGRAM/
ERASE cycles, so in themajority of cases, the ROM code will not haveto look beyond
block 0 for a bootable image.
CLE
CE#
WE#
R/B#
I/Ox
RESET command
FFh
Device ID Don't Care
CLE
CE#
WE#
ALE
RE#
I/Ox 90h 00h
Manufacturer ID
Byte 0 Byte 0 Byte 2 Byte 3Byte 1

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 1: Processor ROM Code
Code Shadowing to the OMAP Processor SRAM
After the NAND Flash device configuration has been verified and the bad blocks have
been checked, the process of copying (shadowing) the X-Loader from the NAND Flash
device to the internal SRAM of the OMAP2420 processor begins.
First, the ROM code reads bytes 1 through 4 of the X-Loader to determine the size of the
file; then it readsbytes 5 through 8 of the X-Loader, which contain the destination
address in SRAM where the X-Loader will be shadowed (see Figure 6 on page 8). The
ROM code then shadows the X-Loader from the NAND Flash device to the OMAP2420
processorSRAM(seeFigure 4),andfinally,thesystemjumpstotheSRAM address where
the first byte of the X-Loader is stored.
Figure 4: Shadowing X-Loader Code from NAND Flash to SRAM
Error Correction Code
TheROMcodecontainserrorcorrection code andchecksforerrorsinthe X-Loader. The
ECC scheme is a Hamming code capable of detecting 2-bit errors and correcting one
1-bit error per 512 bytes.
• When a 1-bit error is detected in a 512-byte sector, the ROM code will use the ECC to
correct the error, and the boot process will continue from thatblock.
• When a 2-bit error is detected in a 512-byte sector, the ROM code will skip this block
and attempt to boot from the next block.
• When an error of 3 bits or more is detected, effects on the system may vary and may
include hanging.
Figure 7 onpage 9depictshow theX-Loader,badblock marking,and ECC arestoredina
typical page of the MT29F1G08ABB NAND Flash device programmed for boot-from-
NAND in an OMAP2420-based system.
Micron NAND Flash
U-Boot
U-Boot
environment data
OS kernel Micron DRAM
OMAP2420 processor ROM
OMAP2420 processor SRAM
ROM process
Block 0 = X-Loader
Block 1 = X-Loader
Block 2 = X-Loader
Block 3 = X-Loader X-Loader
X-Loader
ROM code
File system

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 2: Bootstrap
Stage 2: Bootstrap
Stage 2 of the boot processis dependent on NAND Flash in the sensethat the X-Loader
is stored in the NAND Flash. It is important to remember that this X-Loader is executed
in the OMAP processor SRAM, so the image must fit in the available SRAM.
In a Linux-based system, the stage 2 boot consists of an X-Loader that bootstraps
U-Boot. This bootstrap includes:
• Information for each supported CPU architecture
• A configuration file for each supported board
• NAND Flash driver code
• Serial driver code (to support debug and development efforts)
Building the X-Loader
Building the X-Loader is a critical step in developing a boot-from-NAND system.
Figure 5 on page 8 shows the process for converting source code to a raw binary
X-Loader that can be stored in the Micron NAND Flash device. The “Boot_image” prefix
in the file names is provided only as an example; actual file names can be designated by
the system designer. Figure 6 on page 8 illustrates how the Boot_image.bin code is laid
out in the NAND Flash.
1. Compile the X-Loader source code into an executable format. The example in
Figure 5 on page 8 shows how the source code comprises Boot_image.c and
Boot_image.h; the executable is Boot_image.out.
2. Execute the OST Tools to sign the target file Boot_image.out. When this process is
complete, an 8-byte header is included in the Boot_image.ift file. Bytes 1 through 4 of
Boot_image.ift contain the file size. Bytes 5 through 8 contain the OMAP processor
SRAM address where the X-Loader will be loaded and executed (see Figure 6 on
page 8).OSTTools areavailablefromTI. (SeeOST Toolsdocumentationforadditional
details.)
3. Format the Boot_image.ift file resulting from step 2 for 2KB/page NAND Flash. Code
must be developed for this purpose if it is not available from TI.
To format the Boot_image.ift file, calculate the ECC for each 512-byte sector. Then
storethe resultin theappropriateareaof thefile.SeeFigure 7onpage 9 forboot code,
bad block marking, and ECC storage in a typical page of an MT29F1G08ABB NAND
Flash device programmed for boot-from-NAND in an OMAP2420-based system.
4. Program a copy of the Boot_image.bin file to each of the first four good blocks of the
NAND Flash device. The MT29F1G08ABB device identifies a good block as one that
has 0xFF data at byte 0x800 in both page 0 and page 1.

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 2: Bootstrap
Figure 5: Preparing the X-Loader
Notes: 1. OST Tools is a TI program. Contact a TI representative to obtain a copy.
2. Micron.exe converts ASCII to binary code. Other ASCII-to-binary programs can be used in its
place.
3. Some OST versions do not support Micron MT29F1G08ABB NAND Flash. See “Writing Binary
Images to NAND Flash with Limited OST Tools Support” on page 12 for instructions regard-
ing alternatives.
Figure 6: X-Loader Layout
Develop code to format image
for 2KB page NAND;
include ECC, and extend file size
to 128KB by appending “0s” to file.
Source code:
Boot_image.c
Boot_image.h
Boot_image.out
Boot_image.ift
Executable
Boot_image.out
Boot_image.bin
ARM cross compiler
OST Tools1
NAND FlashOST Tools3 Boot_image.bin
Step 1
Step 2
Step 3
Step 4
Boot_image.ift
X-Loader
4 bytes
(file size)
4 bytes
(SRAM
address)
4 bytes
(file size) 4 bytes
(SRAM address)
Badblock
marking
& ECC
Badblock
marking
& ECC
Badblock
marking
& ECC
Boot_image.bin
Boot_image.bin
Boot_image.bin
Block 0
Page 0
Block 0
Page 1
Block 0
Page 63
Bytes
0–2,047 Bytes 2,048–2,111

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 2: Bootstrap
Figure 7: Page-Level Boot Code Storage
Shadowing U-Boot Code from NAND Flash to DRAM
In an OMAP2420 system, X-Loader shadows the U-Boot code from NAND Flash to
DRAM (see Figure 8). Then the system jumps to the address in DRAM where the first
byte of the U-Boot code resides.
Figure 8: Shadowing U-Boot Code from NAND Flash to DRAM
Byte
2,111
…
BadBlock
Marking
Byte
2,048
Sector A ECC
3 bytes
Bytes
2049, 2050, 2051
Sector B ECC
3 bytes
Bytes
2052, 2053, 2054
Sector CECC
3 bytes
Bytes
2055, 2056, 2057
Sector D ECC
3 bytes
Bytes
2058, 2059, 2060
Typical
2KB PageSector A 512 bytes Sector B 512 bytes Sector C 512 bytes Spare 64 bytes
Sector D
512 bytes
Micron NAND Flash
X-Loader
U-Boot
environment data
OS kernel
File system
Micron DRAM
OMAP2420 processor ROM
OMAP2420 processor SRAM
ROM code
X-Loader
process
U-Boot
X-Loader
U-Boot

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TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 3: Boot Loader
Stage 3: Boot Loader
Stage3of the bootprocessisheavilydependenton the OS.Ina Linuxsystem, the stage 3
bootconsists of U-Boot, the OSboot loader forLinux. U-Boot residesin the NAND Flash
but is shadowed to DRAM for execution (as mentioned in the stage 2 boot description).
U-Boot Considerations • The memory map must be configured to support boot-from-NAND.
• U-Boot must contain NAND Flash support such that it can read and write to the
NAND Flash device.
• U-Boot environment data should be written such that it can be stored in a single
block (128KB) of the Micron MT29F1G08ABB NAND Flash device.
• The CFG_NAND_BOOT configuration label is stored in a board configuration file and
is used to differentiate NAND U-Boot from NOR U-Boot.
U-Boot shadows the OS kernel code from NAND Flash to DRAM (see Figure 9) and then
jumps to the address in DRAM where the first byte of the OS code is stored.
Figure 9: Shadowing OS Kernel Code from NAND Flash to DRAM
Micron NAND Flash
X-Loader
U-Boot
U-Boot
environment data
File system
Micron DRAM
OMAP2420 processor SRAM
OS kernel
U-Boot
process
X-Loader
OMAP2420 processor ROM
Rom code
OS kernel U-Boot