Micron MT9V012 User manual

MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Features
Preliminary‡
PDF: 814eb99f/Source: 8175e929 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V012_1.fm - Rev. B 2/05 EN 1©2004 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron
to meet Micron’s production data sheet specifications.
1/6-Inch VGA CMOS Digital Image Sensor
PART NUMBER: MT9V012
Features
• DigitalClarity™CMOS Imaging Technology
•Highframerate
• Superior low-light performance
•Lowdarkcurrent
• Simple two-wire serial interface
• Auto black level calibration
• Operating Modes: Snapshot and flash control, high
frame rate preview, electronic panning
• Programmable Controls: Gain, frame size/rate,
exposure, left–right and top–bottom image reversal,
window size, and panning
• DataInterfaces:parallelandlow-voltagedifferential
signaling (LVDS)
• Applications
• Cellular Phones
•PCCameras
•PDAs
• Toys and other battery-powered products
General Description
The Micron®Imaging MT9V012 is an oversize VGA-
format CMOS active-pixel digital image sensor with a
pixel array of 649H x 489V. It incorporates sophisti-
cated on-chip camera functions such as windowing,
mirroring, column and row skip modes, and snapshot
mode. It is programmable through a simple two-wire
serial interface and has very low power consumption.
The VGA CMOS image sensor features DigitalClarity—
Micron’s breakthrough low-noise CMOS imaging tech-
nology that achieves CCD image quality (based on sig-
nal-to-noise ratio and low-light sensitivity) while
maintaining the inherent size, cost, and integration
advantages of CMOS.
When operated in its default mode, the sensor gener-
ates a VGA image at 30 frames per second (fps). An on-
chip analog-to-digital converter (ADC) generates a 10-
bit value for each pixel. The pixel data is output on a
10-bit output bus and qualified by an output data
clock (PIXCLK), together with LINE_VALID and
FRAME_VALID signals. A FLASH output strobe is pro-
vided to allow an external Xenon or LED light source to
synchronize with thesensor exposure time. The sensor
can be programmed by the user to control the frame
size, exposure, gain setting and other parameters.
Table 1: Key Performance Parameters
Parameter Typical Value
Optical Format 1/6-inch VGA (4:3)
Active Imager Size 2.30mm(H) x 1.77mm(V),
2.88mm Diagonal
Active Pixels 640H x 480V
Pixel Size 3.6µm x 3.6µm
Color Filter Array RGB Bayer Pattern
Shutter Type Electronic Rolling Shutter (ERS)
Maximum Data Rate/
Master Clock 13.5 MPS/27 MHz
Frame
Rate VGA (640 x 480) Programmable up to 30 fps
CIF
(352 x 288) Programmable up to 60 fps
ADC Resolution 10-bit, on-chip
Responsivity 1.0 V/lux-sec (550nm)
Dynamic Range >71dB
SNRMAX 44dB
Supply
Voltage Analog 2.50V–3.10V (2.80V nominal)
I/O and
Digital 1.70V–1.90V (1.80V nominal) or 2.50V–3.10V (2.80V nominal)
Power Consumption <55mW at 2.8V, 27 MHz,
30 fps and VGA resolution
Operating
Temperature -30°C to +70°C

PDF: 814eb99f/Source: 8175e929 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V012TOC.fm - Rev. B 2/05 EN 2©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Table of Contents
Preliminary‡
Table of Contents
Features. . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . .1
General Description . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . .1
Functional Overview. . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . .6
Operating Modes. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . .7
Default Mode. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . ..7
Serial Mode . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . ..8
Pixel Array Structure. . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . .9
Default Readout Order . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .10
Output Data Format (Default Mode) . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . .10
Output Data Timing (Default Mode) . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . .11
Output Data Format (Serial Mode) . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .13
Output Data Timing (Serial Mode). . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .13
Two-Wire Serial Interface . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . .15
Protocol . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . .15
Sequence . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . .15
Bus Idle State. . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .15
Start Bit. . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .15
Stop Bit . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . .15
Slave Address. . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .16
Data Bit Transfer. . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .16
Acknowledge Bit. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .16
No-Acknowledge Bit . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . .16
Page Register . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . .16
Two-Wire Serial Interface Sample Write and Read Sequences. . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .17
16-Bit Write Sequence. . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .17
16-Bit Read Sequence . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . .17
8-Bit Write Sequence. . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . .18
8-Bit Read Sequence . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .18
Registers . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . .19
Register Description . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . .21
Double-Buffered Registers . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .21
Bad Frames. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . .21
Changes to Integration Time . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .22
Changes to Gain Settings. . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . .22
Feature Description . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .32
Window Control . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .32
Window Start . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .32
Window Size. . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .32
Pixel Border . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . .32
Context Switching . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .. . .32
Readout Modes.. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .33
Column Mirror Image. . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .33
Row Mirror Image . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .33
Column and Row Skip . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . .33
Digital Zoom. . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . .34
Frame Rate Control . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . .35
Minimum Horizontal Blanking . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . .35
Valid Data Signals Options. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . .36
LINE_VALID Signal . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .36
Integration Time. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .36
Maximum Shutter Delay . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .37

PDF: 814eb99f/Source: 8175e929 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V012TOC.fm - Rev. B 2/05 EN 3©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Table of Contents
Preliminary‡
Flash Strobe. . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . .37
Analog Signal Path . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .38
Stage-by-Stage Transfer Functions . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .39
VREFD . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . .39
Gain Settings: G1, G2, G3. . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .39
Offset Voltage: VOFFSET. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . .39
Recommended Gain Settings . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .40
Black Level Calibration . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .40
Row-Wise Noise Cancellation . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .. . .41
Digital Signal Path . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .41
Output Enable Control . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . .41
Power Saving Modes . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .. . .42
Floating Inputs . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .42
Dark Row/Column Display . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .43
Clock Control . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .44
Electrical Specifications. . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .45
Propagation Delay for FRAME_VALID and LINE_VALID . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .49
Propagation Delay for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . .49
Two-wire Serial Bus Timing. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .50
Mechanical Specifications . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . .52
Data Sheet Designation . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .52
Revision History. . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . .53

PDF: 814eb99f/Source: 8175e929 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V012LOF.fm - Rev. B 2/05 EN 4©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
List of Figures
Preliminary‡
List of Figures
Figure 1: Block Diagram . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . .6
Figure 2: Typical Configuration: Default Mode . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . .7
Figure 3: Typical Configuration: Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . ..8
Figure 4: Pixel Array . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . .9
Figure 5: Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . .9
Figure 6: Imaging a Scene . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .10
Figure 7: Spatial Illustration of Image Readout . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . .10
Figure 8: Pixel Data Timing Example. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . .11
Figure 9: Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . .11
Figure 10: Start of Frame: Serial Mode . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . .13
Figure 11: Start of Line: Serial Mode . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .14
Figure 12: Timing Diagram Showing a Write to Reg0x09, Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 13: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . .. . . . . . . .17
Figure 14: Timing Diagram Showing a Write to Reg0x09, Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . .. . . . . . . .18
Figure 16: Six Pixels in Normal and Column Mirror Readout Modes . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . .33
Figure 17: Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .33
Figure 18: Eight Pixels in Normal and Column Skip 2X Readout Modes . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .34
Figure 19: Sixteen Pixels in Normal and Column Skip 4X Readout Modes . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . .34
Figure 20: Eight Pixels in Normal and Zoom 2X Readout Modes . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . .34
Figure 21: LINE_VALID Formats . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .36
Figure 22: Xenon Flash Enabled . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . .37
Figure 23: LED Flash Enabled . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .38
Figure 24: LED Flash Enabled Following Forced Restart . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . .38
Figure 25: Analog Signal Path . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .38
Figure 26: Propagation Delay for FRAME_VALID and LINE_VALID . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .49
Figure 27: Propagation Delays for PIXCLK and DOUT Signals . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .49
Figure 28: Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 29: Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .50
Figure 30: Serial Host Interface Data Timing for Write . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .50
Figure 31: Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .50
Figure 32: Acknowledge Signal Timing After an 8-Bit Write to the Sensor . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .51
Figure 33: Acknowledge Signal Timing After an 8-Bit Read from the Sensor. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .51
Figure 34: Typical Spectral Characteristics . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .51
Figure 35: Image Center Offset . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .52

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
List of Tables
Preliminary‡
List of Tables
Table 1: Key Performance Parameters. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . .1
Table 2: Functional Mode Selection. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . .7
Table 3: Frame Time . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .12
Table 4: Frame—Long Integration Time. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . .12
Table 5: Register List and Default Value . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . .19
Table 6: Register Description. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . .23
Table 7: Offset Gain . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .40
Table 8: Recommended Gain Settings. . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . .40
Table 9: Output Enable Control . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .41
Table 10: Signal State During Standby. . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . .42
Table 11: On-chip Pull-ups/Pull-downs . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . .43
Table 12: DC Electrical Characteristics: 2.50V–3.10V . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .45
Table 13: DC Electrical Characteristics: 1.70V–1.90V . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .46
Table 14: AC Electrical Characteristics: 2.50V–3.10V . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .47
Table 15: AC Electrical Characteristics: 1.70V–1.90V . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .48

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Functional Overview
Preliminary‡
Figure 1: Block Diagram
Functional Overview
TheMT9V012 is a progressive-scan sensor that generatesastreamofpixeldataqualified
by LINE_VALID and FRAME_VALID signals. It uses an input master clock of 27 MHz
(nominal). The data rate (pixel clock) is one half of the master clock frequency, which
means that one pixel is generated every two master clock cycles. Figure 1 shows the sen-
sor block diagram.
The coreof the sensor is an active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row in turn. In
the time interval between resetting a row and reading that row, the pixels in that row
integrate incident light. The exposure is controlled by varying the time interval between
reset and readout. Once a row has been read, the data from the columns is sequenced
through an analog signal chain (providing offset correction and gain), and then through
an ADC. The output from the ADC is a 10-bit valuefor each pixel in the array. The ADC
output passes through a digital processing signal chain (which provides further offset
correction, applies digital gain, and may perform pixel defect correction).
The pixel array contains optically active andlight shielded (“black”) pixels. The black
pixels are used to provide data for on-chip offset correction algorithms (“black level”
control).
The sensor contains a set of 16-bit control and status registers that can be used to con-
trol many aspects of the sensor behavior. These registers can be accessed through a two-
wire serial interface. In this document, registers are specified either by name (e.g., col-
umn start) or by register address (e.g., Reg0x04). Fields within a register are specified by
bit or by bit range (e.g., Reg0x20[0] or Reg0x0B[13:0]). Table 6, RegisterDescription, on
page 23, describes the control and status registers.
The output from the sensor is a Bayer pattern: alternate rows are a sequence of either
green/red pixels or blue/green pixels. The offset and gain stages of the analog signal
chain provide per-color control of the pixel data.
The MT9V012 supports two different functional modes of operation:
• Default mode: the sensor generates a VGA-sized image by default, with 10 parallel
data outputs per pixel, and separate LINE_VALID, FRAME_VALID, and PIXCLK out-
puts. All timing control is performed on-chip.
• Serialmode: the sensor generatesa VGA-sized image by default. Pixel data,
LINE_VALID, and FRAME_VALID are encoded into a single serial data stream that
uses a two-signal low-voltage differential signalling (LVDS) interface. All timing con-
trol is performed on-chip.
Active-Pixel
Sensor (APS)
Array
Serial
I/O
Data
Out
Sync
Signals
Timing and Control
Control Register
Analog Processing ADC

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Operating Modes
Preliminary‡
Operating Modes
The functional operating mode of the MT9V012 is controlled by the MODE1 and
MODE0 inputs (Table 2). These inputsshould be driven to a static logic 1 or static logic 0
level during normal operation.
Default Mode This section shows a typical configuration schematic for the MT9V012 operating in
default mode.
Figure 2: Typical Configuration: Default Mode
Notes: 1. All power supplies should be adequately decoupled.
2. Resistor value 1.5KΩis recommended, but may be greater for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all
times.
Table 2: Functional Mode Selection
Mode1 Mode0 Description
00
Selects default mode
01
Selects serial mode
10
Not used
11
Not used
VDD VAA VAAPIX
MASTER CLOCK
(27 MHz)
10µF
1.5KΩ2
1.5KΩ2, 3
STANDBY
S DATA
SCLK
RESET#
TEST
FRAME_VALID
FLASH
PIXCLK
LINE_VALID
DOUT(9:0)
CLKIN
MODE1
MODE0
1KΩ
DGND AGND
Digital
Ground Analog
Ground
Digital
Power1Analog
Power1
To
Controller
From
Controller

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Operating Modes
Preliminary‡
Serial Mode This section shows a typical configuration schematic, including theball diagram and
ball description, for the MT9V012 operating in serial mode. This mode operates only at
2.5V to 3.1V VDD range.
Figure 3: Typical Configuration: Serial Mode
Notes: 1. All power supplies should be adequately decoupled.
2. Resistor value 1.5KΩis recommended, but may be greater for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all
times.
4. Connect to digital ground directly or through a 10K resistor. Some of these signals have
on-die pull-down resistors in this mode and could be left unconnected.
VDD VAA VAAPIX
MASTER CLOCK
(162 MHz)
10µF
1.5KΩ2
1.5KΩ2, 3
STANDBY
S DATA
SCLK
RESET#
TEST
FRAME_VALID4
LINE_VALID4
DOUT (9:0)4
CLKIN
MODE1
MODE0
1KΩ
DGND AGND
Digital
Ground
Digital
Ground Analog
Ground
Digital
Power1Analog
Power1
From
Controller
DOUTN
FLASH
DOUTPTo
Controller

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Pixel Array Structure
Preliminary‡
Pixel Array Structure
The MT9V012 pixel array is configured as 695 columns by 504 rows (shown in Figure4).
The first 34 columns and the first 14 rows of pixels are optically black, and are used for
the automatic black level adjustment (“Black Level Calibration” on page 40). The last 12
columns and the last row of pixels are also optically black. The optically active pixels are
used as follows:
A VGA image (640 columns by 480 rows) is generated, starting at row 18, column 38. A
four-pixelboundaryofactivepixelscan be enabledaroundthe image to avoidboundary
effects during color interpolation and correction. An additional row and column of
active pixels is also provided for use during horizontally- and/or vertically mirrored
readout. During mirrored readout, the region of active pixels that is used to generate the
image is offset by one pixel in each mirrored direction so that the readout always starts
on the same color pixel.
Figure 4: Pixel Array
The MT9V012 uses a Bayer color pattern, as shown in Figure 5. The even-numbered
rows contain green and red color pixels; odd-numbered rows contain blue and green
color pixels. Even-numbered columns contain green and blue color pixels; odd-num-
bered columns contain red and green color pixels.
Figure 5: Pixel Color Pattern Detail (Top Right Corner)
34 black columns
1 black row
14 black rows (0,0)
12 black columns
Oversize VGA
(640 x 480)
+ 4 pixel border
+1 row/column for mirroring
= 649 x 489 active pixels
Black Pixels
Column Readout Direction
.
.
.
...
Row
Readout
Direction
G1
B
G1
B
G1
B
R
G2
R
G2
R
G2
G1
B
G1
B
G1
B
R
G2
R
G2
R
G2
G1
B
G1
B
G1
B
R
G2
R
G2
R
G2
G1
B
G1
B
G1
B
Pixel
(34,14)

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Output Data Format (Default Mode)
Preliminary‡
Default Readout Order
By convention, the MT9V012 pixel array is shown with pixel (0,0) in the top right-hand
corner (see Figure 5). This reflects the actual layout of the array on the die. When the
sensor is imaging, the active surface of the sensor faces the scene, as shown in Figure 6.
When the image is read out of the sensor, it is read onerow at a time, with the rows and
columns sequenced as shown in Figure 5. By convention, data from the sensor is shown
with the first pixel read out—pixel (34,14) in the case of the MT9V012—in the top left-
hand corner (Figure 7).
Figure 6: Imaging a Scene
Output Data Format (Default Mode)
The MT9V012 image data is read out in a progressive scan. In default mode, valid image
data is surrounded by horizontal blanking and vertical blanking, as shown in Figure 7.
Theamountof horizontal blankingandverticalblankingisprogrammable;LINE_VALID
isHIGHduringtheshadedregionof the figure.FRAME_VALIDtimingisdescribedinthe
next section.
Figure 7: Spatial Illustration of Image Readout
Lens
Pixel (0,0)
Row
Readout
Order
Column Readout Order
Scene
Sensor (rear view)
P
0,0
P
0,1
P
0,2
.....................................P
0,n-1
P
0,n
P
1,0
P
1,1
P
1,2
.....................................P
1,n-1
P
1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P
m-1,0
P
m-1,1
.....................................P
m-1,n-1
P
m-1,n
P
m,0
P
m,1
.....................................P
m,n-1
P
m,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VALID IMAGE HORIZONTAL
BLANKING
VERTICAL BLANKING VERTICAL/HORIZONTAL
BLANKING

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Output Data Format (Default Mode)
Preliminary‡
Output Data Timing (Default Mode)
The MT9V012 output data is synchronized with the PIXCLK output. When LINE_VALID
is HIGH, one pixel datum is output on the 10-bit DOUT output every PIXCLK period. By
default, the PIXCLK signal runs at one-half the frequency of the masterclock, CLKIN,
and its rising edges occur one-half of a master clock period after transitions on
LINE_VALID, FRAME_VALID, and DOUT (see Figure 8). This allows PIXCLK to be used as
a clock to sample the data. PIXCLK is continuously enabled, even during the blanking
period.TheMT9V012can be programmedtodelaythePIXCLKedgerelativeto the DOUT
transitions from 0 to3.5 master clocks,insteps ofone-half of amasterclock. This canbe
achieved by programming the corresponding bits in Reg0x0A. The parameters P, A, and
Q in Figure 9 are defined in Table 3 on page 12.
Figure 8: Pixel Data Timing Example
Figure 9: Row Timing and FRAME_VALID/LINE_VALID Signals
P
0[9:0]
P
1[9:0]
P
2[9:0]
P
3[9:0]
P
4[9:0]
P
5
P
n-2
P
n-1 [9:0]
P
n[9:0]
Valid Image DataBlanking Blanking
LINE_VALID
PIXCLK
D
OUT [9:0]
FRAME_VALID
LINE_VALID
Number of master clocks P AQ AQAP

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Output Data Format (Default Mode)
Preliminary‡
The sensor timing (Table 3) is shown in terms of pixel clock and master clock cycles (see
Figure 8 on page 11). The recommended master clock frequency is 27 MHz. The vertical
blanking and total frame time equations assume that the number of integration rows
(Reg0x09) is less than the number of active rows, plus blanking rows (Reg0x03 +
VBLANK_REG). If this is not the case, thenumber of integration rows must be used
instead, to determine the frame time, as shown in Table 4.
Table 3: Frame Time
Parameter Name Equation Default Timing at 27 MHz
HBLANK_REG Horizontal Blanking Register Reg0x07 if Reg0xC8[0] = 0
Reg0x05 if Reg0xC8[0] = 1 0xF4 = 244 pixels
VBLANK_REG Vertical Blanking Register Reg0x8 if Reg0xC8[1] = 0
Reg0x6 if Reg0xC8[1] = 1 0x1D = 29 rows
PIXCLK_PERIOD Pixel Clock Period Reg0x0A[2:0] * 2 1 pixel clock
= 2 master
= 37.04ns
S Skip Factor For skip 2x mode: S = 2
For skip 4x mode: S = 4
otherwise, S = 1
1
A Active Data Time (Reg0x04/S) * PIXCLK_PERIOD 640 pixel clocks
= 1,280 master
= 47.41µs
P Frame Start/End Blanking 6 * PIXCLK_PERIOD 6 pixel clocks
= 12 master
= 0.44µs
Q Horizontal Blanking HBLANK_REG * PIXCLK_PERIOD 244 pixel clocks
= 488 master
= 18.07µs
A + Q Row Time ((Reg0x04/S) + HBLANK_REG) * PIXCLK_PERIOD 884 pixel clocks
= 1,768 master
= 65.48µs
V Vertical Blanking VBLANK_REG * (A + Q) + (Q - 2*P) 25,868 pixel clocks
= 51,736 master
= 1.91ms
Nrows * (A+Q) Frame Valid Time (Reg0x03/S) * (A + Q) - (Q - 2*P) 424,088 pixel clocks
= 848,176 master
= 31.41ms
F Total Frame Time ((Reg0x03/S) + VBLANK_REG) * (A + Q) 449,956 pixel clocks
= 899,912 master
= 33.33ms
Table 4: Frame—Long Integration Time
Parameter Name Equation (master clock) Default Timing
V’ Vertical Blanking (long integration
time) (Reg0x09 – (Reg0x03)/S)) * (A + Q) + (Q - 2*P) 25,868 pixel clocks = 51,736 master
= 1.91ms
F’ Total Frame Time (long integration
time) (Reg0x09) * (A + Q) 449,956 pixel clocks = 899,912 master
= 33.33ms

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Output Data Format (Serial Mode)
Preliminary‡
Output Data Format (Serial Mode)
The MT9V012 image data is read out in a progressive scan. In serial mode, valid image
data is surroundedbyhorizontal blanking and verticalblanking,asshownin Figure 7on
page 10. However, unlike default mode, serial mode provides pixel data and timing
strobes combined into a single serial bit stream. Electrically, this bit stream uses LVDS
on the DOUTP and DOUTN output signals.
Inserial mode,eachpixelisencodedasa12-bitvaluebyadding a startbitand a stop bit.
The sensor CLKIN input runs at the serial bit-rate and is used within the sensor to clock
adataserializercircuit;itisdividedwithinthesensor so that mostofthecircuitry runsat
the same rate as in default mode. In serial mode, the pixel rate is fixed at one-half the
input frequency; therefore, CLKIN runs at 6 x 27 MHz = 162 MHz.
Output Data Timing (Serial Mode)
The default frame timing in serial mode is identical to the frame timing in default mode.
A special three-character “start-of-frame” sequence—0x3FF, 0x0, and 0x3FF—is trans-
mitted to indicate the assertion of FRAME_VALID. Pixel data, LINE_VALID, and
FRAME_VALID can be reconstructed externally by detecting the start-of-frame
sequence, and using a state machine and counters to identify the active regions of the
frame.
Figure 10 on page 13 shows the beginning of a start-of-frame sequence. It shows the
latency introduced in the parallel-to-serial conversion, and the way in which start and
stop bits are used to frame 10-bit pixel data. Figure 11 on page 14 shows the serial data
stream at the start of a line. In this figure, each 12-bit serial character is represented by
its 10-bit payload. In both figures,the LINE_VALID and FRAME_VALID signals are
shown for reference only; these signals are not available in serial mode.
The most effective method for detecting the start-of-frame sequence is tolook for a con-
tinuous sequence of idle (0x0) characters before looking for the 0x3FF, 0x0, 0x3FF
sequence. The start-of-frame sequence indicates the start of a frame without ambiguity,
as it can never occur as part of a pixel data stream.
In addition, correct operation in serial mode requires that various register settings are
left at their default values. For example, Reg0x0A and Reg0x20[15:14].
The sensor timing in serial mode is calculated in exactly the same way as for default
mode. See “Output Data Timing (Default Mode)” on page 11.
Figure 10: Start of Frame: Serial Mode
Notes: 1. Latency between parallel event and equivalent serial event.
2. First character in start-of-frame sequence.
CLKIN
FRAME_VALID
DOUTP
DOUTN
Start
Bit Stop
Bit
LSB MSB
0x0
(Idle) 0x0 (Idle) 0x3FF
2
12-Clock Latency1
(1 character-time)

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Output Data Format (Serial Mode)
Preliminary‡
Figure 11: Start of Line: Serial Mode
FRAME_VALID
LINE_VALID
SERIAL DATA
Idle Start-of-Frame
Sequence Idle Pixel Data
0x000 0x000 0x000 0x3FF 0x3FF0x000 0x000 0x000 0x000 Pixel 0 Pixel 1

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MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Two-Wire Serial Interface
Preliminary‡
Two-Wire Serial Interface
The two-wire serial register interface enables read/write access to control and status
registers withinthe MT9V012.
The interface protocol uses a master/slave model in which a master controls one or
moreslave devices. Thesensor acts as a slave device. The master generates a clock
(SCLK) that is an input to the sensor and used to synchronize transfers. Data is trans-
ferredbetween the master and theslave on a bidirectional signal (SDATA). The SDATA sig-
nal is pulled up to VDD off-chip by a 1.5KΩresistor. Either the slave or master device can
drive the SDATA line LOW—the interface protocol determines which device is allowed to
drive the SDATA line at any given time.
Protocol The two-wire serial interface defines several different transmission codes, as follows:
•astartbit
• the slave device 8-bit address
• a(an) (no) acknowledge bit
• an 8-bit message
•astopbit
Sequence A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the 8-bit slave-deviceaddress. The last bit of the address deter-
mines if the request will be a read or a write, where a “0” indicates a write and a “1” indi-
cates a read. The slave device acknowledges receipt of the address by sending an
acknowledge bit back to the master.
If the request was a write,the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledgebit to indicate that the register
address has been received. The master then transfers the data, 8 bitsat a time, with the
slave sending an acknowledge bit after each 8 bits. The MT9V012 uses 16-bit data for its
internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits
are transferred, the register address is automatically incremented, so that the next 16
bits are written to the next register address.The master stops writing by sending a start
or stop bit.
A typical read sequence is executed as follows. The master sends the write mode slave
address and 8-bit register address, just as in the write request. The master then sends a
start bit and the read mode slave address, and clocks out the register data, 8 bits at a
time.The master sends an acknowledgebit after each 8-bit transfer.Theregisteraddress
is auto-incremented after every 16 bits is transferred. The data transfer is stopped when
the master sends a no-acknowledge bit.
Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, andthe bus is releasedwithastopbit. Only the master cangenerate
the start and stop bits.
Start Bit The start bit is defined as a HIGH-to-LOW data line transition while the clock line is
HIGH.
Stop Bit The stop bit is defined as a LOW-to-HIGH data line transition while the clock line is
HIGH.

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MT9V012_2.fm - Rev. B 2/05 EN 16 ©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Two-Wire Serial Interface
Preliminary‡
Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1
bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates
read mode. The default slave addresses used by the MT9V012 are 0xBA (write address)
and0xBB(read address).Reg0x0D[10] can be used to selectthe alternateslaveaddresses
0x90 (write address) and 0x91 (read address).
Writes to Reg0x0D[10] areinhibited when STANDBY is asserted (all otherwritesproceed
normally). This allows two sensors to co-exist as slaves on this interface, but they must
be addressed independently. Enable this capability as follows:
• After RESET# is negated, both sensors will use the default slave address. Reads or
writes on the serial register interface to the default slave address will be decoded by
both sensors simultaneously.
• After reset, assert STANDBY to one sensor and negate STANDBY to the other sensor.
Perform a write to Reg0x0D with bit 10 set. The sensor with STANDBY asserted will
ignore the write to bit 10 and will continue to decode at the default slave address. The
sensor with STANDBY negated will have its Reg0x0D[10] set and will respond to the
alternate slave address for all subsequent READ and WRITE operations.
Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the high period of the two-wire
serial interface clock—it can only change when the serial clock is LOW. Data is trans-
ferred 8 bits at atime, followed by an acknowledgebit.
Acknowledge Bit Themastergeneratestheacknowledge clock pulse.Thetransmitter(whichisthe master
when writing, or the slave when reading) releases the data line, and the receiver indi-
cates an acknowledge bit by driving the data line LOW during the acknowledge clock
pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not driven LOW by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
Page Register The MT9V012 two-wire serial interface and its associated protocols support an address
space of 256 16-bit locations. This address space can be extended by a 3-bit page prefix,
and controlled through accesses to Reg0xF0.
The paging mechanism is intended to allow access to other sets of registers when the
sensoris embeddedaspartofamore complexintegrated sub-system(forexample,in an
SOC). All of the registers within the MT9V012 are accessible on page 0 (the default page).

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MT9V012_2.fm - Rev. B 2/05 EN 17 ©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences
Preliminary‡
Two-Wire Serial Interface Sample Write and Read Sequences
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 12. A start bit
givenby the masterstartsthesequence, followedbythewriteaddress.Theimagesensor
then sends an acknowledge bit and expects the register address to come first, followed
by the 16-bit data. After each 8-bit transfer, the image sensor sends an acknowledge bit.
All16bitsmust be written beforethe registeris updated. After 16bitsaretransferred,the
register address is automatically incremented so that the next 16 bits are written to the
next register. The master stops writing by sending a start or stop bit.
Figure 12: Timing Diagram Showing a Write to Reg0x09, Value 0x0284
16-Bit Read Sequence
A typical read sequence is shown in Figure 13. First the master writes the register
address, as in a write sequence. Then a start bit and the read address specify that a read
is about to happen from the register. The master clocks out the register data 8 bits at a
time.The master sends an acknowledgebit after each 8-bit transfer.Theregisteraddress
should be incremented after every 16 bits is transferred. The data transfer is stopped
when the master sends a no-acknowledge bit.
Figure 13: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA
0xBA Address
Start Stop
ACK ACK ACK ACK
Reg0x09 0000 0010 1000 0100
SCLK
SDATA
0xBA Address
Start Start Stop
ACK ACK ACK ACK NACK
Reg0x09 0xBB Address 0000 0010 1000 0100

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MT9V012_2.fm - Rev. B 2/05 EN 18 ©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences
Preliminary‡
8-Bit Write Sequence
To be able to write one byte at a time to the register, a special register address is added.
The8-bitwrite is done bywritingtheupper8bits to the desiredregister,thenwriting the
lower 8 bits to the special register address (Reg0xF1). The register is not updated until all
16 bits have been written. It is not possible to update just half of a register. Figure 14
shows a typical sequence for 8-bit writes. The second byte is written to the special regis-
ter (Reg0xF1).
Figure 14: Timing Diagram Showing a Write to Reg0x09, Value 0x0284
8-Bit Read Sequence
To read one byte at a time, the same special register address is used for the lower byte.
Theupper 8 bitsareread fromthe desiredregister. Byfollowingthis with areadfromthe
special register (Reg0xF1), the lower 8 bits are accessed (Figure 15). The master sets the
no-acknowledge bits.
Figure 15: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA
0xBA Address 0xBA Address Reg0xF1 1000 0100
Start Start Stop
ACK ACK ACK ACK ACK ACK
Reg0x09 0000 0010
SCLK
SDATA
0xBA Address
Start Start
ACK ACK ACK NACK
Reg0x09 0xBB Address 0000 0010
SCLK
SDATA
0xBA Address
Start Start Stop
ACK ACK ACK NACK
Reg0xF1 0xBB Address 1000 0100
• •
• •

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MT9V012_2.fm - Rev. B 2/05 EN 19 ©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Registers
Preliminary‡
Registers The MT9V012 provides a register address space of 256 locations.
Register Map Table 5 shows the locations used within the address space. Locations that are not shown
in the table are reserved for future use; they should not be read from or written to. The
effectofreadingfromorwriting to “Reserved” registersis UNDEFINEDandmayinclude
the possibility of causing permanent electrical damage to the sensor.
Table 5: Register List and Default Value
Register Number
(Hex) Description Data Format (Binary) Default Value (Hex)
0x00 Chip Version 0001 0010 0010 0010 (LSB) 0x1222
0x01 Row Start 0000 000d dddd dddd 0x000E
0x02 Column Start 0000 00dd dddd dddd 0x0026
0x03 Row Width 0000 000d dddd dddd 0x01E0
0x04 Column Width 0000 00dd dddd dddd 0x0280
0x05 Horizontal Blanking B 00dd dddd dddd dddd 0x00F4
0x06 Vertical Blanking B 0ddd dddd dddd dddd 0x001D
0x07 Horizontal Blanking A 00dd dddd dddd dddd 0x0234
0x08 Vertical Blanking A 0ddd dddd dddd dddd 0x010D
0x09 Shutter Width dddd dddd dddd dddd 0x01FD
0x0A Row Speed ddd0 000d dddd 0ddd 0x0011
0x0B Extra Delay 00dd dddd dddd dddd 0x0000
0x0C Shutter Delay 00dd dddd dddd dddd 0x0000
0x0D Reset d000 0ddd dddd dd0d 0x0008
0x20 Read Mode B dd00 00dd dddd dddd 0x0400
0x21 Read Mode A 0000 0000 0000 dd00 0x040C
0x22 Dark Col/Rows 0000 00dd dddd dddd 0x012B
0x23 Flash 00dd dddd dddd dddd 0x0608
0x24 Extra Reset 0d00 0000 0000 0000 0x4000
0x2B Green1 Gain 0000 dddd dddd dddd 0x0020
0x2C Blue Gain 0000 dddd dddd dddd 0x0040
0x2D Red Gain 0000 dddd dddd dddd 0x0020
0x2E Green2 Gain 0000 dddd dddd dddd 0x0020
0x2F Global Gain 0000 dddd dddd dddd 0x0020
0x30 Row Noise dddd dddd dddd dddd 0x042A
0x31 Reserved — 0x1C00
0x32 Reserved — 0x002A
0x33 Reserved — 0x0341
0x34 Reserved — 0xC009
0x35 Reserved — 0x2022
0x36 Reserved — 0xF0F0
0x37 Reserved — 0x0000
0x3B Reserved — 0x0021
0x3C Reserved — 0x1A20
0x3D Reserved — 0x201E
0x3E Reserved — 0x2020

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MT9V012_2.fm - Rev. B 2/05 EN 20 ©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Registers
Preliminary‡
0x3F Reserved — 0x1020
0x40 Reserved — 0x2000
0x41 Reserved — 0x00D7
0x42 Reserved — 0x0777
0x58 Reserved — 0x0000
0x59 Black Rows 0000 0000 dddd dddd 0x000C
0x5A Reserved — 0xE00A
0x5B Dark G1 Average 0000 0000 0??? ????
0x5C Dark B Average 0000 0000 0??? ????
0x5D Dark R Average 0000 0000 0??? ????
0x5E Dark G2 Average 0000 0000 0??? ????
0x5F Calib Threshold 0ddd dddd 0ddd dddd 0x231D
0x60 Calib Control d000 000d dddd dddd 0x0080
0x61 Calib Green1 0000 000d dddd dddd 0x0000
0x62 Calib Blue 0000 000d dddd dddd 0x0000
0x63 Calib Red 0000 000d dddd dddd 0x0000
0x64 Calib Green2 0000 000d dddd dddd 0x0000
0x65 Reserved — 0x0000
0x70 Reserved — 0x7B0A
0x71 Reserved — 0x7B0A
0x72 Reserved — 0x190E
0x73 Reserved — 0x750F
0x74 Reserved — 0x5732
0x75 Reserved — 0x5634
0x76 Reserved — 0x7335
0x77 Reserved — 0x3012
0x78 Reserved — 0x3012
0x79 Reserved — 0x7506
0x7A Reserved — 0x770A
0x7B Reserved — 0x7809
0x7C Reserved — 0x7D06
0x7D Reserved — 0x3110
0x7E Reserved — 0x007E
0x7F Reserved — 0x7C01
0x80 Reserved — 0x5904
0x81 Reserved — 0x5904
0x82 Reserved — 0x570A
0x83 Reserved — 0x2D0B
0x84 Reserved — 0x580B
0x85 Reserved — 0x480E
0x86 Reserved — 0x5B02
0x87 Reserved — 0x005C
0xC8 Context Control 0000 0000 d000 dddd 0x000B
0xF0 Page Map 0000 0000 0000 0ddd 0x0000
0xF1 Bytewise Address 0000 0000 0000 0000 0x0000
Table 5: Register List and Default Value (continued)
Register Number
(Hex) Description Data Format (Binary) Default Value (Hex)