Micron Xccela Flash User manual

Micron®Xccela™Flash User Guide for ZedBoard™
This development kit (including daughterboard with FPGA software code) contains confidential information of Micron
Technology, Inc. It is provided for evaluation purposes only and is not authorized or licensed for any other use. This
development kit is provided “as is” without any warranties of any kind whatsoever. By your acceptance and use of
this development kit, you acknowledge, agree, and accept that Micron expressly disclaims all warranties, whether
written or implied by law, including warranties as to title, merchantability or fitness for a particular purpose, warranties
against infringement of intellectual property rights of a third party, warranties arising by custom, trade usage, course
of dealing, or otherwise. Micron makes no warranty of any kind, and hereby disclaims any warranty, that the
development kit will meet your or any other person’s requirements, achieve any intended result, or be secure,
accurate, complete, free of harmful code or error free. Any open source components or other third-party materials
are provided “as is” and without any representation or warranty from Micron.
Micron®Xccela™ Flash (MT35X)
Development Kit
User Guide for ZedBoard
™

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Contents
1Introduction .............................................................................................................................................................3
1.1 Block Diagram................................................................................................................................................4
1.2 Zynq Bank Pin Assignments ..........................................................................................................................4
2Daughterboard Support ..........................................................................................................................................5
2.1 Daughterboard with TBGA-24 Socket (FMC_0007_SNOR_TBGA_V2.0)......................................................5
3Set Up and Installation............................................................................................................................................6
3.1 Boot File.........................................................................................................................................................6
3.2 Jumpers and Connections .............................................................................................................................6
3.3 Power Up .......................................................................................................................................................7
4. Test Routines..........................................................................................................................................................9
4.1 Command Operation......................................................................................................................................9
4.2 Key Notes Before Testing ..............................................................................................................................9
4.2 Timing Tuning ..............................................................................................................................................10
4.3 Programmer-Like Tool .................................................................................................................................10
4.3.1 Program ............................................................................................................................................11
4.3.2 Read..................................................................................................................................................11
5Revision History ....................................................................................................................................................12
Appendix A: Command List...................................................................................................................................13
Appendix B: Example Command Sequence .........................................................................................................16
Appendix C: FMC_0007_SNOR_TBGA_V2.0 Schematic.....................................................................................19

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1 Introduction
The ZedBoard is an evaluation and development board based on the Xilinx Zynq™-7000 All
Programmable SoC (AP SoC). Combining a dual Cortex-A9 processing system (PS) with 85,000
Series-7 programmable logic (PL) cells, the Zynq-7000 AP SoC can be targeted for broad use in
many applications. The ZedBoard’s mix of on-board peripherals and expansion capabilities make it
an ideal platform for both novice and experienced designers. The features provided by the
ZedBoard consist of the following:
Feature
Description
Xilinx® XC7Z020-1CLG484CES
Zynq-7000 AP SoC
Primary configuration = QSPI flash
Auxiliary configuration options:
-Cascaded JTAG
-SD card
Memory -512MB DDR3 (128M x 32)
-256Mb QSPI flash
Interfaces -USB-JTAG programming using Digilent SMT1-equivalent circuit
-Accesses PL JTAG
-PS JTAG pins connected through PS Pmod
-10/100/1G Ethernet
-USB OTG 2.0
-SD card
-USB 2.0 FS USB-UART bridge
-Five Digilent Pmod™ compatible headers (2x6) (1 PS, 4 PL)
-One LPC FMC
-One AMS header
-Two reset buttons (1 PS, 1 PL)
-Seven push buttons (2 PS, 5 PL)
-Eight dip/slide switches (PL)
-Nine user LEDs (1 PS, 8 PL)
-DONE LED (PL)
Onboard Oscillators -33.333 MHz (PS)
-100 MHz (PL)
Display/Audio -HDMI output
-VGA (12-bit color)
-128x32 OLED display
-Audio line-in, line-out, headphone, microphone
Power -On/off switch
-12V @ 5A AC/DC regulator

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1.1 Block Diagram
Figure 1: ZedBoard Block Diagram
1.2 Zynq Bank Pin Assignments
Figure 2: ZedBoard Z7020 CLG484 Bank Assignments

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2 Daughterboard Support
A 24-ball TBGA (TBGA-24B) package for Xccela Flash is supported on a dedicated daughterboard,
which can be connected to the ZedBoard for testing.
2.1 Daughterboard with TBGA-24 Socket (FMC_0007_SNOR_TBGA_V2.0)
TBGA-24B (6mm x 8mm, 5x5 ball grid array) is supported on FMC_0007_SNOR_TBGA_V2.0, while
signal test port is also reserved on the daughterboard.
Figure 3: Daughterboard with TBGA-24 Socket
SW1 and SW2 are used for pull-up/pull-down for HOLD# and WP#. These two switches must be
configured as follows:
FMC_0007_SNOR_TBGA V2.0 Setting
SW Description Setting
SW1 HOLD# pull up/down SW1-1 on, SW1-2 off (pull-up on, pull-down off)
SW2 WP# pull up/down SW1-1 off, SW1-2 on (pull-up on, pull-down off)
IMPORTANT: The two sub-switches on SW1 and SW2 cannot be enabled at the same time;
this would cause the power to be short to ground.

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3 Set Up and Installation
3.1 Boot File
The software file (config-MT35X_1.8.zip for MT35XU series or config-MT35X_3.0.zip for MT35XL series)
contains seven files required to boot up the ZedBoard. These files must be stored in a FAT32-formatted SD
card: Linux kernel, Ramdisk rootfs, device tree, boot images and testing bench-related files.
Figure 4: Boot File Contents
IMPORTANT: Do not rename the boot files; these file names must remain as displayed.
3.2 Jumpers and Connections
To boot the ZedBoard, several jumpers and connections must be configured as described below.
Follow these instructions before powering on the board.
Figure 5: ZedBoard Jumpers and Connections
1. Connect J2.
2. Configure JP7, JP8, JP10 and JP11 as follows:
Jumper
JP7
JP8
JP9
JP10
JP11
Setting
GND
GND
3V3
3V3
GND
3. Set J18 to 1V or 3V according to the operating power of your sNOR device.
Figure 6: J18 Power Setting

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3.3 Power Up
1. Plug in the SD card, USB cable (for the serial port), and DC adapter as shown below.
Figure 7: SD Card, USB Cable, DC Adapter Connections
2. Switch on power by SW8.
3. If this is the first time inserting the USB port, the driver automatically downloads and installs. After
the driver installs successfully, the USB port maps to a serial port (for example, COM11).
Figure 8: Driver Software Successfully Installed
4. Open the serial port tool, and then configure the port number to the USB serial port mapped in the
previous step (for example, COM 11).
5. Set the baud rate to 115200.
Figure 9: Baud Rate Setting

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ZedBoard OLEDs after boot
MT35X logo indicates the DUT
is under testing
6. If this is the first time booting the ZedBoard, run the following two commands to set up the system
boot environment, and then power down the board. Skip these three steps if you've previously
booted the ZedBoard.
•Press any key when the message Hit any key to stop autoboot appears.
•env default -f -a
•env save
Figure 10: Setting the System Boot Environment
7. Power on the ZedBoard.
When the XCCELA>> prompt appears after the Micron welcome screen (it may take a few
seconds), the system boots successfully and enters the SPI NOR test bench.
Figure 11: Xccela Flash Test Bench
Figure 12: LEDs After Booting
If another vendor’s memory is detected (instead of Micron’s Xccela family memory), or if no
memory is detected, the system hangs at the boot stage with the following message:

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4. Test Routines
4.1 Command Operation
Type HELP and then press enter to obtain all supported commands for the Xccela device.
Figure 13: Xccela Commands
Type -H and then press enter to obtain command details. (For example, type FRD -H to obtain
information for the page program command.)
Figure 14: Xccela Command Details
See Appendix A: Command List for detailed command usage.
4.2 Key Notes Before Testing
Before testing, review the following important notes:
•There are three types of predefined data patterns (select by argument [pattern]) in PP commands:
-Fixed pattern: fixed data could be full 0x0 ~ 0xFF relying on value set for [pattern]
-Counter Pattern: 0x0, 0x1, 0x2, … 0xFF, 0x0, 0x1, 0x2, …
-Tuning Data Pattern (TDP): See Timing Tuning section for details
•The tuning operation is always required with the Xccela ZedBoard tool if you want to change the
frequency or data rate mode (SDR to DDR, DDR to SDR, Extended to Octal, Octal to Extended).
See the Timing Tuning section for instructions.
•The highest frequency is up to 200 MHz DDR mode; other typical frequencies are supported by
the TUNING command.
•TUNING Dxxx xx should be issued before entering Octal DDR mode.
•TUNING Sxxx xx is required before switching from Octal DDR mode to Extended mode.
•The OCTALVFY command is implemented to verify program and read functions under Octal
DDR mode, before which Octal DDR mode must be enabled.
•With the MSE command, only the SECTOR ERASE feature is enabled for multisector erase
operation. SECTOR, SUBSECTOR and BULK ERASE are all enabled in the SE command.
•No security features are supported in the current version.

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4.2 Timing Tuning
After power up, the Xccela ZedBoard runs at 25 MHz SDR mode by default. The system enters 25 MHz
SDR mode as well once RESET is executed or the tuning operation is unsuccessful.
The TUNING [mode+freq] [sectornum] command tunes DUT with the expected mode (SDR or DDR)
and frequency for the SPI controller with the following options:
•S50: SDR 50MHz
•D50: DDR 50MHz
•S133: SDR 133MHz
•D133: DDR 133MHz
•S166: SDR 166MHz
•D166: DDR 166MHz
•D200: DDR 200MHz
Below is the TDP used for the Xccela ZedBoard tool:
FF0F FF00 FFCC C3CC C33C CCFF FEFF FEEF
FFDF FFDD FFFB FFFB BFFF 7FFF 77F7 BDEF
FFF0 FFF0 0FFC CC3C CC33 CCCF FEFF FFEE
FFFD FFFD DFFF BFFF BBFF F7FF F77F 7BDE
See Appendix B Example Command Sequence for a sample of the entire sequence.
4.3 Programmer-Like Tool
1. Press any key once you see the Hit any key to stop autoboot message.
2. When the Zynq> prompt appears, type run programmer
Figure 15: Running the Programmer-Like Tool
3. The programmer tool is ready when the welcome screen appears:
Figure 16: Programmer Tool Welcome Screen