Silicon Laboratories C8051F00 DK Series User manual

Rev. 0.6 9/06 Copyright © 2006 by Silicon Laboratories C8051F00x/01x-DK
C8051F00x/01x-DK
C8051F00X/01XDEVELOPMENT KIT USER’SGUIDE
1. Kit Contents
The C8051F00x/01x Development Kit contains the following items:
• C8051F005 Target Board
• C8051Fxxx Development Kit Quick-Start Guide
• Silicon Laboratories IDE and Product Information CD-ROM. CD content includes:
• Silicon Laboratories Integrated Development Environment (IDE)
• Keil Software 8051 Development Tools (macro assembler, linker, evaluation ‘C’ compiler)
• Source code examples and register definition files
• Documentation
• C8051F00x/01x Development Kit User’s Guide (this document)
• AC to DC Power Adapter
• USB Debug Adapter (USB to Debug Interface)
• USB Cable
2. Hardware Setup using a USB Debug Adapter
The target board is connected to a PC running the Silicon Laboratories IDE via the USB Debug Adapter as shown
in Figure 1.
1. Connect the USB Debug Adapter to the JTAG connector on the target board with the 10-pin ribbon cable.
2. Connect one end of the USB cable to the USB connector on the USB Debug Adapter.
3. Connect the other end of the USB cable to a USB Port on the PC.
4. Connect the ac/dc power adapter to power jack P1 on the target board.
Notes:
•UsetheReset button in the IDE to reset the target when connected using a USB Debug Adapter.
• Remove power from the target board and the USB Debug Adapter before connecting or disconnecting the
ribbon cable from the target board. Connecting or disconnecting the cable when the devices have power can
damage the device and/or the USB Debug Adapter.
Figure 1. Hardware Setup using a USB Debug Adapter
PC
USB
Cable
USB Debug Adapter
AC/DC
Adapter
Target Board
SILICON LABORATORIES
PWR
P1.6
P3.7RESET
Port 4Port 3Port 1
Port 2 Port 0
MCU
Silicon Laboratories
USB DEBUG ADAPTER
Run
StopPower

C8051F00x/01x-DK
2 Rev. 0.6
3. Software Setup
The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE), Keil software
8051 tools and additional documentation. Insert the CD-ROM into your PC’s CD-ROM drive. An installer will auto-
matically launch, allowing you to install the IDE software or read documentation by clicking buttons on the Installa-
tion Panel. If the installer does not automatically start when you insert the CD-ROM, run autorun.exe found in the
root directory of the CD-ROM. Refer to the readme.txt file on the CD-ROM for the latest information regarding
known IDE problems and restrictions.
4. Silicon Laboratories Integrated Development Environment
The Silicon Laboratories IDE integrates a source-code editor, source-level debugger and in-system Flash program-
mer. The use of third-party compilers and assemblers is also supported. This development kit includes the Keil
Software A51 macro assembler, BL51 linker and evaluation version C51 ‘C’ compiler. These tools can be used
from within the Silicon Laboratories IDE.
4.1. System Requirements
The Silicon Laboratories IDE requirements:
• Pentium-class host PC running Microsoft Windows 98SE or later.
• One available COM or USB port.
• 64 MB RAM and 40 MB free HD space recommended.
4.2. Assembler and Linker
A full-version Keil A51 macro assembler and BL51 banking linker are included with the development kit and are
installed during IDE installation. The complete assembler and linker reference manual can be found under the Help
menu in the IDE or in the “SiLabs\MCU\hlp” directory (A51.pdf).
4.3. Evaluation C51 ‘C’ Compiler
An evaluation version of the Keil C51 ‘C’ compiler is included with the development kit and is installed during IDE
installation. The evaluation version of the C51 compiler is the same as the full professional version except code
size is limited to 4 kB and the floating point library is not included. The C51 compiler reference manual can be
found under the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (C51.pdf).
4.4. Using the Keil Software 8051 Tools with the Silicon Laboratories IDE
To perform source-level debugging with the IDE, you must configure the Keil 8051 tools to generate an absolute
object file in the OMF-51 format with object extensions and debug records enabled. You may build the OMF-51
absolute object file by calling the Keil 8051 tools at the command line (e.g. batch file or make file) or by using the
project manager built into the IDE. The default configuration when using the Silicon Laboratories IDE project
manager enables object extension and debug record generation.
Refer to Applications Note AN104 - Integrating
Keil 8051 Tools Into the Silicon Labs IDE
in the “SiLabs\MCU\Documentation\Appnotes” directory on the CD-
ROM for additional information on using the Keil 8051 tools with the Silicon Laboratories IDE.
To build an absolute object file using the Silicon Laboratories IDE project manager, you must first create a project. A
project consists of a set of files, IDE configuration, debug views, and a target build configuration (list of files and tool
configurations used as input to the assembler, compiler, and linker when building an output object file).
The following sections illustrate the steps necessary to manually create a project with one or more source files, build
a program and download the program to the target in preparation for debugging. (The IDE will automatically create a
single-file project using the currently open and active source file if you select
Build/Make Project before a project is
defined.)

C8051F00x/01x-DK
Rev. 0.6 3
4.4.1. Creating a New Project
1. Select ProjectNew Project to open a new project and reset all configuration settings to default.
2. Select FileNew File to open an editor window. Create your source file(s) and save the file(s) with a rec-
ognized extension, such as .c, .h, or .asm, to enable color syntax highlighting.
3. Right-click on “New Project” in the Project Window. Select Add files to project. Select files in the file
browser and click Open. Continue adding files until all project files have been added.
4. For each of the files in the Project Window that you want assembled, compiled and linked into the target
build, right-click on the file name and select
Add file to build . Each file will be assembled or compiled as
appropriate (based on file extension) and linked into the build of the absolute object file.
Note: If a project contains a large number of files, the “Group” feature of the IDE can be used to organize.
Right-click on “New Project” in the
Project Window . Select Add Groups to project . Add pre-defined
groups or add customized groups. Right-click onthe group name and choose
Add file to group . Select files
to be added. Continue adding files until all project files have been added.
4.4.2. Building and Downloading the Program for Debugging
1. Once all source files have been added to the target build, build the project by clicking on the Build/Make
Project button in the toolbar or selecting ProjectBuild/Make Project from the menu.
Note: After the project has been built the first time, the Build/Make Project command will only build the
files that have been changed since the previous build. To rebuild all files and project dependencies, click
on the Rebuild All button in the toolbar or select ProjectRebuild All from the menu.
2. Before connecting to the target device, several connection options may need to be set. Open the
Connection Options window by selecting Options  Connection Options... in the IDE menu. First, select
the appropriate adapter in the “Serial Adapter” section. Next, the correct “Debug Interface” must be selected.
C8051F00x/01x family devices use the JTAG debug interface. Once all the selections are made, click the OK
button to close the window.
3. Click the
Connect button in the toolbar or select Debug  Connect from the menu to connect to the device.
4. Download the project to the target by clicking the Download Code button in the toolbar.
Note: To enable automatic downloading if the program build is successful select Enable automatic con-
nect/download after build in the ProjectTarget Build Configuration dialog. If errors occur during the
build process, the IDE will not attempt the download.
5. Save the project when finished with the debug session to preserve the current target build configuration,
editor settings and the location of all open debug views. To save the project, select Project->Save Project
As... from the menu. Create a new name for the project and click on Save.

C8051F00x/01x-DK
4 Rev. 0.6
5. Example Source Code
Example source code and register definition files are provided in the “SiLabs\MCU\Examples\ C8051F0xx ” directory
during IDE installation. These files may be used as a template for code development. Example applications include
a blinking LED example which configures the green LED on the target board to blink at a fixed rate.
5.1. Register Definition Files
Register definition files C8051F000.inc and C8051F000.h define all SFR registers and bit-addressable
control/status bits for the C8051F00x/01x device family. They are installed into the
“SiLabs\MCU\Examples\C8051F0xx” directory during IDE installation. The register and bit names are identical to
those used in the C8051F00x/01x data sheet. Both register definition files are also installed in the default search
path used by the Keil Software 8051 tools. Therefore, when using the Keil 8051 tools included with the
development kit (A51, C51), it is not necessary to copy a register definition file to each project’s file directory.
5.2. Blinking LED Example
The example source files blink.asm and blinky.c show examples of several basic C8051F00x/01x functions. These
include; disabling the watchdog timer (WDT), configuring the Port I/O crossbar, configuring a timer for an interrupt
routine, initializing the system clock, and configuring a GPIO port. When compiled/assembled and linked this pro-
gram flashes the green LED on the target board about five times a second using the interrupt handler with a timer.

C8051F00x/01x-DK
Rev. 0.6 5
6. Target Board
The C8051F00x/01x Development Kit includes a target board with a C8051F005 device pre-installed for evaluation
and preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyp-
ing using the target board. Refer to
Figure 2 for the locations of the various I/O connectors.
P1 Power connector (accepts input from 7 to 15 VDC unregulated power adapter)
J1 Connects SW2 to port pin P1.7
J2 64-pin I/O connector providing access to all I/O signals
J3 Connects LED D3 to port pin P1.6
J4 JTAG connector for Debug Adapter interface
J6 Analog I/O configuration connector
X1 Analog I/O terminal block
Figure 2. C8051F005 Target Board
J3
J1
P1
Proto AreaProto Area
J2
Pin 1
Prototyping Area I/O Connection Points
J6
Pin 2
P1.7 RESET
PWRP1.6
Pin 1
JTAG
C8051F005
Pin 1
Pin 2
X1

C8051F00x/01x-DK
6 Rev. 0.6
6.1. System Clock Sources
The C8051F005 device installed on the target board features a internal oscillator which is enabled as the system
clock source on reset. After reset, the internal oscillator operates at a frequency of 2 MHz (±2%) by default but may
be configured by software to operate at other frequencies. Therefore, in many applications an external oscillator is
not required. However, an external crystal may be installed on the target board for additional applications. The tar-
get board is designed to facilitate the installation of an external crystal at the pads marked Q1. Refer to the
C8051F005 datasheet for more information on configuring the system clock source. Following are a few part num-
bers of suitable crystals:
Freq (MHz) Digikey P/N ECS P/N
18.432 X146-ND ECS-184-20-1 (20 pF loading capacitance)
11.0592 X089-ND ECS-110.5-20-1 (20 pF loading capacitance)
6.2. Switches and LEDs
Two switches are provided on the target board. Switch SW1 is connected to the RESET pin of the C8051F005
device on the target board. Pressing SW1 puts the device into its hardware-reset state. The device will leave the
reset state after SW1 is released. Switch SW2 is connected to the device’s general purpose I/O (GPIO) pin through
headers. Pressing SW2 generates a logic low signal on the port pin. Remove the shorting block from the header to
disconnect SW2 from the port pins. The port pin signal is also routed to a pin on the J2 I/O connector. See Table 1
for the port pins and headers corresponding to each switch.
Two LEDs are also provided on the target board. The red LED labeled PWR is used to indicate a power connection
to the target board. The green LED labeled with a port pin name is connected to the device’s GPIO pin through a
header. Remove the shorting block from the header to disconnect the LED from the port pin. The port pin signal is
also routed to a pin on the J2 I/O connector. See Table 1 for the port pins and headers corresponding to each LED.
6.3. Target Board JTAG Interface (J4)
The JTAG connector (J4) provides access to the JTAG pins of the C8051F005. It is used to connect the Serial
Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming. Table 2
shows the
JTAG pin definitions.
Table 1. Target Board I/O Descriptions
Description I/O Header
SW1 Reset none
SW2 P3.7 J1
Green LED P1.6 J3
Red LED PWR none
Table 2. JTAG Connector Pin Descriptions
Pin # Description
1 +3VD(+3.3VDC)
2, 3, 9 GND (Ground)
4TCK
5TMS
6TDO
7TDI
8, 10 Not Connected

C8051F00x/01x-DK
Rev. 0.6 7
6.4. Analog I/O (J6, Terminal Block)
An Analog I/O Configuration connector (J6) provides the ability to route analog I/O signals from the C8051F005
device to a terminal block by installing two shorting blocks on J6. It also allows the DAC outputs to be connected to
Comparator 0 inputs or to two ADC inputs. Analog signals may be routed to the AIO 0 and AI01 posts of the termi-
nal block by installing a shorting block between two adjacent pins on J6. Refer to Figure 3 to determine the shorting
block installation positions required to connect the desired analog signal to the terminal block. Refer to Table 3 for
terminal block connections and Table 4 for J6 pin definitions.
Figure 3. J6 Analog I/O Configuration Connector
Table 3. Terminal Block Pin Descriptions
Pin # Description
1AIO1
2AIO0
7 AGND (Analog Ground)
8VREF
Table 4. J6 Connector Pin Descriptions
Pin # Description
1CP0+
2CP0-
3, 9, 15 AIO1
4, 10, 16 AIO0
5DAC0
6DAC1
7AIN0
8AIN1
11 AIN2
12 AIN3
13 AIN4
14 AIN5
17 AIN6
18 AIN7
J6
CP0-
DAC0
AIN0
AIN2
AIN4
AIN6
Pin 1
Pin 2
AIO1
AIO0
GNDA
Vref
CP0+
DAC1
AIN1
AIN3
AIN5
AIN7

C8051F00x/01x-DK
8 Rev. 0.6
6.5. Expansion I/O Connector (J2)
The 64 -pin expansion I/O connector J1 provides access to most signal pins of the C8051F005 device on the target
board. A small through-hole prototyping area is also provided. All I/O signals routed to connector J2 are also routed to
through-hole connection points between J2 and the prototyping area (see
Figure 4 on page 9 ). The signal layout pat-
tern of these connection points is identical to the adjacent J2 connector pins
. See Table 5 for a list of pin descrip-
tions for J2
.
Table 5: J2 Pin Descriptions
Pin Description Pin Description
1 +VD (digital voltage supply) 28 P3.7
2XTAL1 29P3.4
3 P1.6 30 P3.5
4 P1.7 31 P3.2
5 P1.4 32 P3.3
6 P1.5 33 P3.0
7 P1.2 34 P3.1
8P1.3 36/RST
9 P1.0 39,41,42 GND (digital ground)
10 P1.1 45,47,63 GNDA (analog ground)
11 P0.6 46,64 +VA (analog voltage supply)
12 P0.7 48 DAC0
13 P0.4 49 CP1-
14 P0.5 50 DAC1
15 P0.2 51 CP1+
16 P0.3 52 CP0-
17 P0.0 53 VREF
18 P0.1 54 CP0+
19 P2.6 55 AIN0
20 P2.7 56 AIN1
21 P2.4 57 AIN2
22 P2.5 58 AIN3
23 P2.2 59 AIN4
24 P2.3 60 AIN5
25 P2.0 61 AIN6
26 P2.1 62 AIN7
27 P3.6

C8051F00x/01x-DK
Rev. 0.6 9
7. Schematic
Figure 4. C8051F005 Target Board Schematic

C8051F00x/01x-DK
10 Rev. 0.6
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 0.5
Section 1, added USB Debug Adapter and USB Cable.
Section 2, changed name from "Hardware Setup" to "Hardware Setup using an EC2 Serial Adapter".
Section 2, added 2 Notes bullets.
Section 2, removed Note from bottom of page.
Added Section 3, "Hardware Setup using a USB Debug Adapter".
Section 5.4.2, changed step 2 to include new instructions.
Section 7, J4, changed "Serial Adapter" to "Debug Adapter".
Target Board DEBUG Interface Section, added USB Debug Adapter.
DEBUG Connector Pin Descriptions Table, changed pin 4 to C2D.
Changed "jumper" to "header".
EC2 Serial Adapter section, added EC2 to the section title, table title and figure title.
EC2 Serial Adapter section, changed "JTAG" to "DEBUG".
Added "USB Debug Adapter" section.
Revision 0.5 to Revision 0.6
Removed EC2 Serial Adapter from Kit Contents.
Removed Section 2. Hardware Setup using an EC2 Serial Adapter. See RS232 Serial Adapter (EC2) User's
Guide.
Removed Section 8. EC2 Serial Adapter. See RS232 Serial Adapter (EC2) User's Guide.
Removed Section 9. USB Debug Adapter. See USB Debug Adapter User's Guide.

Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories.A"Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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