Microsemi SmartFusion2 MSS Installation and operating instructions

Application Note AC389
March 2016 1
© 2016 Microsemi Corporation
SmartFusion2 SoC FPGA - Cache Controller
Configuration - Libero SoC v11.7
Table of Contents
Purpose
This application note explains the cache controller features and how to configure the cache controller for
various cacheable memories in the SmartFusion®2 system-on-chip (SoC) FPGA devices.
References
The following are the references:
• AC390: SmartFusion2 SoC FPGA – Remapping eNVM, eSRAM, and DDR/SDR SDRAM
Memories Application Note
• SmartFusion2 MSS ARM Cortex-M3 Configuration Guide
• UG0451: SmartFusion2 and IGLOO2 Programming User Guide
• UG0450: SmartFusion2 SoC and IGLOO2 FPGA System Controller User Guide
• UG0331: SmartFusion2 Microcontroller Subsystem User Guide
• Configuring Serial Terminal Emulation Programs
Introduction
The SmartFusion2 devices integrate an 8 kb instruction cache. The following memories are cacheable:
• Embedded non-volatile memory (eNVM)
• Low power double data rate (LPDDR)
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
SmartFusion2 Cache Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Cacheable Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
SmartFusion2 Cache Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Board Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Steps to Run the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Appendix: Design and Programming Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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To aid in system reliability, the instruction cache is constructed of single event upset (SEU) tolerant
latches. This application note describes the configuration of cache controller for various cacheable
memories.
Design Requirements
Table 1 shows the design requirements.
Note: *For this application note, SoftConsole v3.4 SP1 is used. For using SoftConsole v4.0, see the
TU0546: SoftConsole v4.0 and Libero SoC v11.7 Tutorial.
Table 1 • Design Requirements
Design Requirements Description
Hardware Requirements
SmartFusion2 Security Evaluation Kit
• 12 V adapter
• FlashPro4 programmer
• USB A to Mini-B USB cable
Note: Refer the UG0594: SmartFusion2 Security
Evaluation Kit User Guide for more information
Rev D or later
Host PC or Laptop • Windows XP SP2 Operating System - 32-bit or 64-bit
• Windows 7 Operating System - 32-bit or 64-bit
Software Requirements
Libero®System-on-Chip (SoC) v11.7
SoftConsole v3.4 SP1*
Host PC Drivers USB to UART drivers

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SmartFusion2 Cache Controller Overview
Figure 1 shows the system-level view of the cache controller in the SmartFusion2 device.
Figure 1 • System-Level View of Cache Controller in the SmartFusion2 Device
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Figure 2 shows the block diagram of the SmartFusion2 cache controller. Refer to the
UG0331: SmartFusion2 Microcontroller Subsystem User Guide for more information on cache controller.
Cacheable Memory Regions
The following sections explain memory mapping of eNVM and LPDDR address space to cacheable
memory regions. The code space of the ARM®Cortex®-M3 processor ranges from 0x00000000 to
0x1FFFFFFF (0.5 GB). The address space of eNVM or LPDDR can be mapped to code space of the
Cortex-M3 processor to make the memory region cacheable. Design examples are provided in
"Appendix: Design and Programming Files" on page 16.
Remapping eNVM as Cacheable Region
The address range of eNVM_0 is from 0×60000000 to 0×6003FFFF and the address range of eNVM_1
is from 0×60040000 to 0×6007FFFF. By default, the full eNVM memory from 0×60000000 to
0×6007FFFF is mapped as a cacheable region. The eNVM base address 0×60000000 is remapped to
Corte×-M3 processor address space 0×00000000. You can remap any offset of eNVM address to the
Corte×-M3 processor address space 0×00000000 by using the ENVM_CR, ENVM_REMAPSIZE, and
ENVM_REMAP_BASR_CR system registers.
Figure 2 • SmartFusion2 Device Cache Controller Block Diagram
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Refer to "Appendix: Design and Programming Files" on page 16 for eNVM as cacheable region design
files and follow "Running the Design" on page 11 for executing the reference design.
Remapping of External RAM as Cacheable Region
Remap the LPDDR memory address to the bottom (0×0000_0000) of the Cortex-M3 processor code
region by using the DDR_CR system register. Any portion of the mapped memory can be made
cacheable. The cacheable region can be configured to 128 MB, 256 MB or 512 MB dynamically by using
the CC_REGION_CR system register. Ensure that the stack and data/heap sections of the application
are out of the cacheable memory region. Refer to the AC390: Remapping eNVM, eSRAM, and LPDDR
Memories Application Note, for more information on remapping techniques and linker script file
generation.
Table 2 • Memory Map of eNVM to Cortex-M3 Processor Code Region
Data/Code Region Space Address Range
M3 Data Region
RESERVED 0×E000_0000 to 0×FFFF_FFFF
DDR _SPACE 3 (256 MB) 0×D000_0000 to 0×DFFF_FFFF
DDR _SPACE 2 (256 MB) 0×C000_0000 to 0×CFFF_FFFF
DDR_ SPACE 1 (256 MB) 0×B000_0000 to 0×BFFF_FFFF
DDR _SPACE 0 (256 MB) 0×A000_0000 to 0×AFFF_FFFF
eNVM SFR, Remap Area etc (1 GB) 0×6000_0000 to 0×9FFF_FFFF
Peripheral [SPI, UART, CAN, Fabric etc] (0.5 GB) 0×4000_0000 to 0×5FFF_FFFF
RESERVED 0×2001_0000 to 0×3FFF_FFFF
eSRAM-1 (32 KB) 0×2000_8000 to 0×2000_FFFF
eSRAM-0 (32 KB) 0×2000_0000 to 0×2000_7FFF
M3 Code Region
RESERVED 0×0008_0000 to 0×1FFF_FFFF
eNVM (Virtual View) [512 KB] 0×0000_0000 to 0×0007_FFFF
Table 3 • Memory Map of External RAM to Cortex-M3 Processor Code Region
Data/Code Region Space Address Range
M3 Data Region
RESERVED 0×E000_0000 to 0×FFFF_FFFF
DDR _SPACE 3 (256 MB) 0×D000_0000 to 0×DFFF_FFFF
DDR _SPACE 2 (256 MB) 0×C000_0000 to 0×CFFF_FFFF
DDR_ SPACE 1 (256 MB) 0×B000_0000 to 0×BFFF_FFFF
DDR _SPACE 0 (256 MB) 0×A000_0000 to 0×AFFF_FF×FF
eNVM SFR, Remap Area etc (1 GB) 0×6000_0000 to 0×9FFF_FFFF
Peripheral [SPI, UART, CAN, Fabric etc] (0.5 GB) 0×4000_0000 to 0×5FFF_FFFF
RESERVED 0×2001_0000 to 0×3FFF_FFFF
eSRAM-1 (32 KB) 0×2000_8000 to 0×2000_FFFF
eSRAM-0 (32 KB) 0×2000_0000 to 0×2000_7FFF
M3 Code Region
DDR _SPACE 1 (256 MB) 0×1000_0000 to 0×1FFF_FFFF
DDR _SPACE 0 (256 MB) 0×0000_0000 to 0×0FFF_FFFF

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SmartFusion2 Cache Controller Features
The following sections explain the various user configurable features of the cache controller in the
SmartFusion2 device:
•Cache Memory Enable or Disable
•Cache Flush
•Cache Locked Mode
Cache Memory Enable or Disable
Cache memory can be enabled or disabled dynamically by using the CC_CR system register.
Instructions are cached when the cache memory is enabled. In Cache Disabled mode, all transactions
are treated as non-cacheable.
Use the following steps to enable or disable the cache memory dynamically using the application code:
1. Set the cacheable region.
2. Enable cache memory.
3. Run the task.
4. Get the cache status information.
5. Disable cache memory.
Refer to Table 4 on page 11 for APIs to enable or disable cache memory and to get cache status
information.
Cache Flush
Cache memory can be flushed in the following two ways:
• Complete cache memory flush: When you flush the full cache memory, all the cached instructions
are deleted.
• Index based cache memory flush: When you flush one index in the cache memory, it invalidates
all tags of four sets at one index only.
The following steps describe how to flush the cache memory:
1. Enable cache memory.
2. Run the task (the instructions are cached).
3. Disable cache memory.
4. Flush the cache memory (the cached instructions are deleted).
Refer to Table 4 on page 11 for APIs to flush the cache memory.
Cache Locked Mode
The Cache Locked mode is a special mode that provides predictable execution, which is a requirement
for some specific applications. Before enabling the Cache Locked mode, the software ensures that the
code is copied to cache memory by simulating a sequential location cache miss through I-code. After
copying the complete 8 KB of data, the Cache Locked mode is enabled. After the Cache Locked mode is
enabled, any access from 0 to 8 KB is directly read from the cache and the cache is not invalidated or
refilled for normal operations. Memory region beyond 8 KB is treated as non-cacheable and accessed as
per the memory map.
The Cache Locked mode can only be used with either DDR or eNVM memory and the lock base address
must be in the Cortex-M3 processor code region. The code image that is copied to cache memory is also
present in eNVM or DDR memory. After executing the code from the cache, the execution control comes
to the main memory to execute the remaining code image. You can enable or disable the Cache Locked
mode dynamically.

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Figure 3 shows a simple program execution flow with Cache Locked mode.
Refer to Table 4 on page 11 for APIs to enable or disable the Cache Locked mode.
Design Description
The example designs use MMUART_1, eSRAM, DDR, and eNVM memory controllers. In the design
example, microcontroller subsystem clock conditioning circuitry (MSS CCC) is configured to run M3_CLK
at 80 MHz, which drives the clock to Cortex-M3 processor. The cache controller can be configured either
using cache controller block in System Builder configurator or through APIs (Table 4 on page 11). The
software application calculates the nth Fibonacci number with and without cache controller and compares
the execution time. It also gets the cache status information such as, cache hit, cache miss, cache hit
rate, and cache miss rate. This application also supports cache memory flushing.
Figure 3 • Simple Program Execution Flow with Cache Locked Mode
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Hardware Implementation
The hardware implementation involves configuring MDDR, MMUART_1, and clocks using System
Builder. Figure 4 shows the top-level SmartDesign of the cache controller configuration.
The MSS_CCC clock is sourced from Fabric CCC. Fabric CCC is configured to provide the
80 MHz clock using GL0. Figure 5 shows the system clocks configurations for M3_CLK, MDDR_CLK,
and APB_0_CLK/APB_1_CLK.
Figure 4 • Top-Level SmartDesign
Figure 5 • Clock Configurations

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MMUART_1 is routed through the FPGA fabric for communicating with the serial terminal program.
MDDR is configured for LPDDR at 80 MHz speed. Figure 6 shows MSS MDDR configuration settings.
Click Import Configuration to import the register configuration for LPDDR (refer to "Appendix: Design
and Programming Files" on page 16 for DDR configuration file).
Figure 6 • MSS External Memory Configurator

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Figure 7 shows the cache controller configuration through System Builder in the Libero SoC software.
Note: Enabling cache through System Builder is not required in this application note design.
Software Implementation
The software design example performs the following operations:
• Enabling or disabling the cache controller
• Selecting cacheable region in case of DDR memory
• Cache memory flushing
• Initialization of timer to measure execution time
• Calculating cache hit rate, cache miss rate, and task execution time
• Displaying results on serial terminal program (for example, HyperTerminal) using MMUART_1
The example software design uses UART based serial communication to communicate with serial
terminal program on the host PC. This example takes finding the nth Fibonacci number as the task and
calculates the result with and without cache controller. The Fibonacci number is randomly selected. It
displays the cache hit rate, cache miss rate, and execution time on serial terminal program.
Figure 7 • Cache Controller Configuration Through System Builder in Libero