MICROTRONIX J1 User manual

4045 Meadowbrook Drive, Unit 126
London, ON Canada N6L 1E31
www.mi rotronix. om
Mi rotronix
Camera Link Transmitter
HSMC Daughter Card
U SER M ANUAL
R
EVISION 1.0

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This User Manual provides basic information about using the
Microtronix Camera Link Tranmitter HSMC Daughter Card, PN:
6287-01-01. The following table shows the document revision history.
Date Des ription
eptember 2012 Initial release – Version 1.0
-mail
ales Information: [e-mail]
upport Information: [e-mail]
Website
General Website: http://www.microtronix.com
Downloads: http://www.microtronix.com/downloads/
upport FTP site: http://microtronix.leapfile.com
Phone Numbers
General: [phone]-0091
Fax: [phone]
Do ument
Revision History
How to Conta t
Mi rotronix

Camera Link Transmitter HSMC Daughter Card User Manual
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Table of Contents
Document Revision History.............................................................................................................. 2
How to Contact Microtronix.............................................................................................................. 2
E-mail ........................................................................................................................................... 2
Website......................................................................................................................................... 2
Phone Numbers ........................................................................................................................... 2
Card Features .................................................................................................................................. 4
Introduction ...................................................................................................................................... 5
Kit Contents .................................................................................................................................. 5
Related Documentation................................................................................................................ 5
FPGA Host Board Compatibility ................................................................................................... 5
Hardware Description ...................................................................................................................... 6
Camera Link Connector ............................................................................................................... 6
H MC to Camera Link Connector Mapping ............................................................................. 9

Camera Link Transmitter HSMC Daughter Card User Manual
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• Dual Camera Link Transmitter connectors
• upports single Base, single Medium or single Full
• H MC Type II or III differential LVD interface
Card
Features

Camera Link Transmitter HSMC Daughter Card User Manual
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The Microtronix Camera Link Transmitter HSMC Daughter Card is
designed for building base, medium and full Camera Link transmitter
(Camera) interfaces. The card interfaces to Altera FPGA based
development boards using differential LVD signals per a Type II or III
H MC connector interface.
Two Camera Link (CL) connectors are provided which enables the card
to support one Base, one Medium or one Full Camera Link
configuration.
Kit Contents
The Microtronix Camera Link Transmitter HSMC Daughter Card is
supplied with the following components:
• Microtronix Camera Link Transmitter H MC Daughter Card
• Mounting Hardware
• CD containing user documentation and board schematics
Related Documentation
The user may also want to refer to other Microtronix information
including:
• User Manuals for:
o Camera Link IP Core Design Kit
o Camera Link IP Core
• Altera High peed Mezzanine Card (H MC) pecification
FPGA Host Board Compatibility
The card interfaces to Altera FPGA based development boards using
differential LVD signals which requires the use of a Type II or III
H MC connector interface. Microtronix has tested Camera Link
Tranmitter board on the boards listed below.
• Microtronix boards:
o ViClaro III Video Host board
o ViClaro IV Video Host board
• Altera boards:
o Cyclone III (EP3C120) FPGA Development board
o Cyclone IV (EP4CGX150) FPGA Development board
NOTE: The Camera Link board may operate on other platforms.
However, the user should verify the availability of differential
LVD signals, LVD 100Ω resistor terminations and
Introdu
tion

Camera Link Transmitter HSMC Daughter Card User Manual
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differential clock inputs capable of being routed to a PLL
within the FPGA.
The Microtronix Camera Link Tranmitter HSMC Daughter Card (PN:
6287-01-01) is shown in Figure 1 below. It provides two Camera Link
MDR-26 female connectors (3M – 14B26- ZLB-X00-OLC). The card
can be configured to signal PoCL compatibility to frame grabbers that
support PoCL(Refer to notes on the Camera Link board schematics
6287 for more information). The 26-pin CL connector pinout is shown
in Table 1 below.
Figure 1: Camera Link Transmitter HSMC Daughter Card
Camera Link Connector
The 26-pin Camera Link connectors are compliant with the Camera
Link standard. The connector assignments are shown in the tables
below. Connector J1 (the connector on left) supports a Base interface
and connector J2 (on the right) by default supports medium or full
configuration.
Hardware
Des ription

Camera Link Transmitter HSMC Daughter Card User Manual
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Table 1: Camera Link Camera J1 Base Conne tor Pinout
Board Signal Name Pin CL Signal Type Des ription
12VDC 1 12VDC Power Power PoCL Power
GND 14 Power Return Ground PoCL Power
FG0_n0 2 X0- LVD Out CL X Channel Tx
FG0_p0 15 X0+ LVD Out CL X Channel Tx
FG0_n1 3 X1- LVD Out CL X Channel Tx
FG0_p1 16 X1+ LVD Out CL X Channel Tx
FG0_n2 4 X2- LVD Out CL X Channel Tx
FG0_p2 17 X2+ LVD Out CL X Channel Tx
FG0_n3_clk 5 XClk- LVD Out CL X Channel Tx Clock
FG0_p3_clk 18 XClk+ LVD Out CL X Channel Tx Clock
FG0_n4 6 X3- LVD Out CL X Channel Tx
FG0_p4 19 X3+ LVD Out CL X Channel Tx
FG0_n5 20 erTC+ LVD In erial Data Transmitter
FG0_p5 7 erTC- LVD In erial Data Transmitter
FG0_n6 8 erTFG- LVD Out erial Data Receiver
FG0_p6 21 erTFC+ LVD Out erial Data Receiver
FG0_n7 9 CC1- LVD In User electable Input
FG0_p7 22 CC1+ LVD In User electable Input
FG0_n8 23 CC2+ LVD In User electable Input
FG0_p8 10 CC2- LVD In User electable Input
FG0_n9 11 CC3 - LVD In User electable Input
FG0_p9 24 CC3+ LVD In User electable Input
FG0_p10 12 CC4+ LVD In User electable Input
FG0_n10 25 CC4- LVD In User electable Input
GND 13 Power Return Ground PoCl Power
12VDC 26 12VDC Power Power PoCL Power

Camera Link Transmitter HSMC Daughter Card User Manual
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Table 2: Camera Link Camera J2 Medium & Full Conne tor Pinout
Cable Pin CL Signal Type Des ription
12VDC 1 12VDC Power Power PoCL Power
GND 14 Power Return Ground PoCL Power
FG1_n0 2 Y0- LVD Out CL Y Channel Tx
FG1_p0 15 Y0+ LVD Out CL Y Channel Tx
FG1_n1 3 Y1- LVD Out CL Y Channel Tx
FG1_p1 16 Y1+ LVD Out CL Y Channel Tx
FG1_n2 4 Y2- LVD Out CL Y Channel Tx
FG1_p2 17 Y2+ LVD Out CL Y Channel Tx
FG1_n3_clk 5 YClk- LVD Out CL Y Channel Tx Clock
FG1_p3_clk 18 YClk+ LVD Out CL Y Channel Tx Clock
FG1_n4 6 Y3- LVD Out CL Y Channel Tx
FG1_p4 19 Y3+ LVD Out CL Y Channel Tx
FG1_n5 7 100 Ω LVD In
FG1_p5 20 TERMINATED LVD In
FG1_n6 8 Z0- LVD Out CL Z Channel Tx
FG1_p6 21 Z0+ LVD Out CL Z Channel Tx
FG1_n7 9 Z1- LVD Out CL Z Channel Tx
FG1_p7 22 Z1+ LVD Out CL Z Channel Tx
FG1_n8 10 Z2- LVD Out CL Z Channel Tx
FG1_p8 23 Z2+ LVD Out CL Z Channel Tx
FG1_n9_clk 11 Zclk- LVD Out CL Z Channel Tx Clock
FG1_p9_clk 24 Zclk+ LVD Out CL Z Channel Tx Clock
FG1_n10 12 Z3- LVD Out CL Z Channel Tx
FG1_p10 25 Z3+ LVD Out CL Z Channel Tx
GND 13 Power Return Ground PoCl Power
12VDC 26 12VDC Power Power PoCL Power

Camera Link Transmitter HSMC Daughter Card User Manual
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HSMC to Camera Link Connector Mapping
Table 3 below shows the pinout of the H MC connector, along with the
FPGA pin connections when the Camera Link Transmitter HSMC
Daughter Card is used on header J4 of the Microtronix ViClaro III Host
Video board and J3 on the Microtronx ViClaro IV Host board.
Table 3: Camera Link Conne tor (Base) Pinout
ViClaro IV ViClaro III HSMC Camera Link Board CL Interfa e
Signal
Cy lone IV
Pin #
J3 Board
Signal
Cy lone III Pin
#
J4 Board
Signal Pin Signal Name
J2 Pin
- - - 12VDC 1 12VDC Power
- - - GND 14 Power Return
R29 H MC3_TXn0 Y7 LVD _n33 49 FG0_n0 2 X0-
T28 H MC3_TXp0 W8 LVD _p33 47 FG0_p0 15 X0+
P28 H MC3_TXn1 V7 LVD _n31 55 FG0_n1 3 X1-
P27 H MC3_TXp1 V8 LVD _p31 53 FG0_p1 16 X1+
R26 H MC3_TXn2 V5 LVD _n29 61 FG0_n2 4 X2-
R25 H MC3_TXp2 V6 LVD _p29 59 FG0_p2 17 X2+
T27 H MC3_TXn3 U5 LVD _n27 67 FG0_n3 5 XClk-
T26 H MC3_TXp3 U6 LVD _p27 65 FG0_p3 18 XClk+
T24 H MC3_TXn4 R6 LVD _n25 73 FG0_n4 6 X3-
T23 H MC3_TXp4 R7 LVD _p25 71 FG0_p4 19 X3+
N30 H MC3_RXn0 W1 LVD _n36 50 FG0_n5 20 erTC+
N29 H MC3_RXp0 W2 LVD _p36 48 FG0_p5 7 erTC-
T21 H MC3_TXn5 M7 LVD _n23 79 FG0_n6 8 erTFG-
U21 H MC3_TXp5 M8 LVD _p23 77 FG0_p6 21 erTFC+
P30 H MC3_RXn2 V3 LVD _n32 62 FG0_n7 9 CC1-
R30 H MC3_RXp2 V4 LVD _p32 60 FG0_p7 22 CC1+
R28 H MC3_RXn3 V1 LVD _n30 68 FG0_n8 23 CC2+
R27 H MC3_RXp3 V2 LVD _p30 66 FG0_p8 10 CC2-
W26 H MC3_RXn4 U1 LVD _n28 74 FG0_n9 11 CC3 -
W25 H MC3_RXp4 U2 LVD _p28 72 FG0_p9 24 CC3+
U28 H MC3_RXn5 U4 LVD _n26 80 FG0_p10 12 CC4+
U27 H MC3_RXp5 U3 LVD _p26 78 FG0_n10 25 CC4-
- - - GND 13 Power Return
- - - 12VDC 26 12VDC Power

Camera Link Transmitter HSMC Daughter Card User Manual
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Table 4: Camera Link Conne tor (Medium & Full) Pinout
ViClaro IV ViClaro III HSMC Camera Link CL Interfa e
Signal
Cy lone IV
Pin # J3 Board Signal Cy lone III
Pin # J4 Board Signal Pin Board Signal
J3 Pin
1 12VDC Power
14 Power Return
Y22 H MC3_TXn8 M3 LVD _n17 103 FG1_n0 2 Y0-
AA22 H MC3_TXp8 L1 LVD _p17 101 FG1_p0 15 Y0+
Y27 H MC3_TXn9 P1 LVD _n15 109 FG1_n1 3 Y1-
AA27 H MC3_TXp9 P2 LVD _p15 107 FG1_p1 16 Y1+
AB28 H MC3_TXn10 N3 LVD _n13 115 FG1_n2 4 Y2-
AB27 H MC3_TXp10 N4 LVD _p13 113 FG1_p2 17 Y2+
AA25 H MC3_TXn11 L6 LVD _n11 121 FG1_n3 5 YClk-
AB25 H MC3_TXp11 L7 LVD _p11 119 FG1_p3 18 YClk+
AB26 H MC3_TXn12 J5 LVD _n9 127 FG1_n4 6 Y3-
AC25 H MC3_TXp12 J6 LVD _p9 125 FG1_p4 19 Y3+
Y28 H MC3_RXn8 L3 LVD _n18 104 FG1_n5 7 100 Ω
AA28 H MC3_RXp8 L4 LVD _p18 102 FG1_p5 20 TERMINATED
AD28 H MC3_TXn13 M1 LVD _n7 133 FG1_n6 8 Z0-
AD27 H MC3_TXp13 M2 LVD _p7 131 FG1_p6 21 Z0+
AE28 H MC3_TXn14 G5 LVD _n5 139 FG1_n7 9 Z1-
AE27 H MC3_TXp14 G6 LVD _p5 137 FG1_p7 22 Z1+
AE26 H MC3_TXn15 G3 LVD _n3 145 FG1_n8 10 Z2-
AE25 H MC3_TXp15 G4 LVD _p3 143 FG1_p8 23 Z2+
AG29 H MC3_TX_CLKn1 C2 LVD _n0 157 FG1_n9 11 Zclk-
AH29 H MC3_TX_CLKp1 D3 LVD _p0 155 FG1_p9 24 Zclk+
AF28 H MC3_TXn16 D1 LVD _n1 151 FG1_n10 12 Z3-
AF27 H MC3_TXp16 D2 LVD _p1 149 FG1_p10 25 Z3+
13 Power Return
26 12VDC Power