Mitsubishi DS907x SIP User manual

TABLE OF CONTENTS
i
SECURE MICROCONTROLLER USER’S GUIDE 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 1 Introduction 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 2 Selection Guide 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 3 Secure Microcontroller Architecture 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 4 Programmer’s Guide 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 5 Memory Interconnect 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 6 Lithium/Battery Backup 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 7 Power Management 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 8 Software Control 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 9 Firmware Security 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 10 Reset Conditions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 11 Interrupts 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 12 Parallel I/O 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 13 Programmable Timers 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 14 Serial I/O 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 15 CPU Timing 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 16 Program Loading 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 17 Real–Time Clock 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 18 Troubleshooting 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 19 Instruction Set Details 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECURE MICROCONTROLLER DEVELOPMENT TOOLS
Development Support
Third Party Development Tools
DS907x SIP Stik Connectors
DS5000TK User’s Guide

USER’S GUIDE
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SECTION 1: INTRODUCTION
The Secure Microcontroller family is a line of
8051–compatible devices that utilize nonvolatile RAM
(NV RAM) rather than ROM for program storage. The
use of NV RAM allows the design of a “soft” microcon-
troller which provides a number of unique features to
embeddedsystemdesigners.Foremostamongtheseis
the enhanced security features that are employed by
the Secure Microcontroller Family to protect the user
application software against piracy and tampering.
Thesedevicesoffervaryingdegreesofsecurity,ranging
from simple access prevention to a full encryption of
program and data memory of the device. Attempts to
gain access to protected information will result in the
self–destruction of all data. The SecureMicrocontroller
familyistheheartofawiderangeofsecurity–criticalap-
plications such as electronic banking, commercial
transactions, and pay TV access control, or any situa-
tion which requires the protection of proprietary soft-
ware and algorithms.
The Secure Microcontroller family is divided between
chips and modules. The chips are monolithic micropro-
cessors that connect to a standard SRAM and lithium
battery. The modules combine the microprocessor with
the SRAM and lithium battery in a preassembled, pre-
testedmodule.Dependingonthespecificconfiguration,
modules are available in either 40–pin encapsulated
DIP or SIMM module format.
In addition to NV RAM, Dallas Semiconductor micro-
controllers offer a number of peripherals that simplify
and reduce the cost of embedded systems. Although
thespecificfeaturesof eachchipor modulevary, allde-
vices offer the following basic feature set:
•100% code–compatible with 8051
•Directly addresses 64KB program/64KB data
memory
•Nonvolatile memory control circuitry
•10–year data retention in the absence of power
•In–system reprogramming via serial port
•128 bytes fast access scratchpad RAM
•Two 16–bit general purpose timer/counters
•One UART
•Five interrupts with two external
•Dedicated memory bus, preserving four 8–bit ports
for general purpose I/O
•Power–Fail Reset
•Early Warning Power Fail Interrupt
•Watchdog Timer
SOFTWARE SECURITY
OneofthemostimportantfeaturesoftheSecureMicro-
controller family is firmware/memory security. The de-
vices were specifically designed to offer an unprece-
dented level of protection to the user application
software, preventing unauthorized copying of firmware
and denying access to critical data values. The use of
RAMratherthanthetraditionalROMorEPROMforpro-
gram storage increases the security, since tampering
with the system will result in the loss of the RAM con-
tents.Additionalfeaturessuchasreal–timehigh–speed
memory encryption, generation of dummy addresses
on the bus, and internal storage of vector RAM in-
creases the security of a Secure Microcontroller/Micro-
processor–based system.
The DS5002FP Secure Microprocessor Chip and
DS2252TSecureMicrocontrollerModuleofferthehigh-
est level of security, with permanently enabled memory
encryption,a 64–bitrandom encryption key,and a self–
destruct input for tamper protection. The DS5000FP
Soft Microprocessor Chip and DS5000(T) and
DS2250(T) Soft Microcontroller Modules offer lesser,
butstillsubstantial,protectionwithoptionaldataencryp-
tion and a 48–bit encryption key.
SEPARATE ADDRESS/DATA BUS
Soft Microprocessor chips provide a non–multiplexed
address/data bus that interfaces to memory without in-
terferingwithI/Oports.ThisByte–widebusconnectsdi-
rectly to standard CMOS SRAM in 8K x 8, 32K x 8, or
128K x 8 densities with no glue logic. Note that this is in
addition to the standard 8051 port 0 and 2 multiplexed
bus. In module form, the Byte–wide bus is already con-
nected directly to on–board SRAM, so the memory ac-
cessbecomestransparentandtheI/Oports freeforap-
plication use. The extra memory bus also allows for a
time–of–dayfunction to be included, and all Soft Micro-
controller modules are available with built in real–time
clocks. The same clock devices are individually avail-
ablewhenbuildingasystemfromchips.Batterybackup
and decoding are automatically handled by the micro-
processor.

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3
LARGE NONVOLATILE MEMORY
Soft Microprocessor chips provide nonvolatile memory
control for standard CMOS SRAM. Modules combine
themicroprocessor chipwithmemory and lithium back-
up. This includes conditionally write protected chip en-
ablesanda powersupplyoutputthatswitchesbetween
+5Vandbatterybackup.Thechipenablesaredecoded
automatically based on user selectable memory sizes
and partitioning. Partitioning defines the portion of
memory used for program and data segments. Areas
thataredesignated programare alwayswrite protected
andaretreatedasROM.Dataareasarewriteprotected
onlywhenpoweris outoftolerance. Alargenonvolatile
memory is useful for data logging and as flexible pro-
gramstorage.Memorywillberetainedforover10years
at room temperature in the absence of power by ultra
low–leakage lithium backed circuits.
IN–SYSTEM LOADING
Thein–systemprogrammingcapabilityletstheuserup-
dateprogram code at any time. This program loading is
supervised by a built–in ROM–based bootstrap loader.
The ROM loader becomes transparent once program
loading is complete. All devices allow program loading
via the serial port. Data memory can also be retrieved
using this loader function. Selected versions provide
otherparallelloadingprotocolsaswell.In–systemload-
ingallowsasystemtobeconfiguredduringfinalsystem
test. A user can load custom software, diagnostic rou-
tines, or calibration constants. If something changes or
new features arise, the system can then be repro-
grammed while in the field.
HIGH RELIABILITY OPERATION
Secure Microcontroller devices are designed for unsu-
pervised operation in remote locations. Special fea-
tures prevent a system from running out of control dur-
ingtransient events. These includeareset when power
isoutof tolerance;anearlywarningpower–failinterrupt
that allows software to save critical data; and a watch-
dog to reset the micro if it gets lost. Also, nonvolatile
memoryallowssoftwaretosavetheoperatingstatesoa
task can be resumed when power returns to normal.
The Secure Microcontroller family consists of three
chips and their associated modules. Differences stem
from I/O, memory access, and security features. The
DS5000FP is used in DS2250T and DS5000(T) mod-
ules. The DS5001FP is used in the DS2251T, and the
DS5002FPisusedintheDS2252T.Afullselectorguide
with all memory and speed permutations is provided in
the next section.
CHIP DESCRIPTION BYTE–WIDE BUS
MEMORY ACCESS SECURITY PACKAGE
DS5000FP Soft Microprocessor Chip 8, 32, 64*K bytes Optional 80–pin QFP
DS5001FP 128K Microprocessor Chip 32, 64, 128K bytes None 80–pin QFP
DS5002FP Secure Microprocessor Chip 32, 64, 128K bytes Maximum 80–pin QFP
MODULE DESCRIPTION ON–BOARD MEMORY PACKAGE
DS2250(T) DS5000FP on SIMM 8, 32, 64*K bytes 40–pin SIMM
DS5000(T) DS5000FP in DIP Module 8, 32K bytes 40–pin DIP
DS2251T DS5001FP on SIMM 32, 64, 128K bytes 72–pin SIMM
DS2252T DS5002FP on SIMM 32, 64, 128K bytes 40–pin SIMM
*32K partitionable, 32K restricted to data memory only.
NOTES:
“T” specifies optional on–board real–time clock.
128K byte versions provide fixed 64K program, 64K data segments. Other versions are partitionable.

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PRODUCT DESCRIPTION
All devices listed below have the standard 8051 family
featureset listed once hereforconvenience,butnot re-
peated for each device.
•8051–compatible instruction set
•Addresses 64K program and 64K data memory
•Four 8–bit pseudo–bidirectional I/O ports
•128 bytes scratchpad RAM
•Two 16–bit timer/counters
•One UART
•Five Interrupts with two external
DS5000FP Soft Microprocessor Chip
TheDS5000FPistheoriginalSoftMicroprocessorchip.
It adds the following features to the 8051 set :
•Non–multiplexed Byte–wide address/data bus for
memory access.
•Nonvolatile Control for 8K x 8 or 32K x 8 SRAMs
•Partitions one SRAM into program and data areas,
and write protects the program segment
•Decodes memory for up to two 32K x 8 SRAMs (#2
is data memory only)
•Power–fail Reset, and Interrupt
•Precision Watchdog Timer
•ROM based Serial Bootstrap Loader
•Optional security features
– Memory encryption in real–time
– 48–bit user selected encryption key
– Security lock destroys memory if unlocked
– Vector RAM hides 48 bytes on–chip
– Dummy operations on the memory bus
DS5000(T) Soft Microcontroller Module
The DS5000 incorporates the DS5000FP chip in a
40–pin module with an 8051 footprint and pinout.
•Familiar 40–pin DIP package
•Built–in NV RAM of 8K x 8 or 32K x 8
•I/O ports not disturbed by on–board memory access
•10–year data retention and clock operation in the
absence of power
•Partitions memory into program and data areas,
write protects the program segment
•Power–fail Reset and Interrupt
•Precision Watchdog Timer
•ROM based Serial Bootstrap Loader
•Optional memory security
•Optional built–in real time clock (battery backed)
DS2250(T) Soft Microcontroller Module
The DS2250(T) incorporates the DS5000FP chip on a
40–pinSIMM module. Ithasthe identicalfeatureset as
the DS5000(T), but is in a different form–factor. This
package change allows up to 64K bytes NV RAM
insteadof32Kbytes.Notethatasmentionedabove,the
second 32K is restricted to data memory. Like the
DS5000(T), this module guarantees better than
10–year data retention at room temperature.
DS5001FP 128K Soft Microprocessor Chip
The DS5001FP provides the base feature set of the
DS5000FP with the following extras:
•Accesses up to 128K bytes on the Byte–wide bus.
•Decodes memory for 32K x 8 or 128K x 8 SRAMs.
•Four additional decoded peripheral chip enables
•CRC hardware for checking memory validity
•Optionally emulates an 8042 style slave interface
•Bandgap reference for more accurate power moni-
tor
Note: The DS5001FP has no memory encryption
feature.

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5
DS2251T 128K Soft Microcontroller Module
The DS2251T is a SIMM based on the DS5001. It pro-
vides up to 128K bytes of on–board NV RAM and has
the Byte–wide bus available at the connector. This is
used with the decoded peripheral enables for memory
mapped peripherals such as a UART or A/D converter.
The real–time clock is a parallel access type with inter-
rupt capability. Like the older versions, the DS2251T
provides 10–year data retention, even in the largest
memory configuration.
DS5002FP Secure Microprocessor Chip
The DS5002FP is a highly secure version of the
DS5001FP. It provides the operating features of the
DS5001FP, with the following enhancements to the
DS5000 security features.
•Security is active at all times
•Improved memory encryption using a 64–bit en-
cryption key
•Automatic random generation of encryption keys
•Self–destruct input for tamper protection
•Optional top–coating prevents microprobe
(DS5002FPM)
DS2252T Secure Microcontroller Module
TheDS2252T incorporates the DS5002FP ona 40–pin
SIMM. This includes from 32K bytes to 128K bytes of
secure memory with a real time clock. The memory is
highly secure from tampering and from competitors.
Likeotherproductsinthefamily,theD2252Thasadata
retention period of over 10 years at room temperature.

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SECTION 2: SELECTION GUIDE
The following configurations are available. Speeds are
rated maximums, but all members of the Secure Micro-
controller family are fully static and can be run as slow
as desired.
CHIP DESCRIPTION MAXIMUM SPEED PART NUMBER
DS5000FP–16 Soft Microprocessor Chip 16 MHz DS5000FP–16
DS5001FP–16 128K Microprocessor Chip 16 MHz DS5001FP–16
DS5002FP–16 Secure Microprocessor Chip 16 MHz DS5002FP–16
MODULE DESCRIPTION MEMORY SPEED CLOCK PART NUMBER
DS5000 Soft Microcontroller
Module 8K bytes 16 MHz no DS5000–08–16
DS5000 Soft Microcontroller
Module 32K bytes 16 MHz no DS5000–32–16
DS5000T Soft Microcontroller
Module 8K bytes 16 MHz yes DS5000T–08–16
DS5000T Soft Microcontroller
Module 32K bytes 16 MHz yes DS5000T–32–16
DS2250 Soft Microcontroller
Module 8K bytes 16 MHz no DS2250–08–16
DS2250 Soft Microcontroller
Module 32K bytes 16 MHz no DS2250–32–16
DS2250 Soft Microcontroller
Module 64K bytes 16 MHz no DS2250–64–16
DS2250T Soft Microcontroller
Module 8K bytes 16 MHz yes DS2250T–08–16
DS2250T Soft Microcontroller
Module 32K bytes 16 MHz yes DS2250T–32–16
DS2250T Soft Microcontroller
Module 64K bytes 16 MHz yes DS2250T–64–16
DS2251T 128K Microcontroller
Module 32K bytes 16 MHz yes DS2251T–32–16
DS2251T 128K Microcontroller
Module 64K bytes 16 MHz yes DS2251T–64–16
DS2251T 128K Microcontroller
Module 128K bytes 16 MHz yes DS2251T–128–16
DS2252T Secure Microcontrol-
ler Module 32K bytes 16 MHz yes DS2252T–32–16
DS2252T Secure Microcontrol-
ler Module 64K bytes 16 MHz yes DS2252T–64–16
DS2252T Secure Microcontrol-
ler Module 128K bytes 16 MHz yes DS2252T–128–16

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SECTION 3: SECURE MICROCONTROLLER
ARCHITECTURE
Introduction
The Secure Microcontroller family is based on an 8051
compatible core with a memory interface and I/O logic
buildaroundit. Manyfunctionsare identicaltostandard
8051s and are documented here for completeness. In
general, most architecture features apply to all mem-
bersof theSecureMicrocontrollerfamily.Whenthereis
adifferencebetweenversions,thiswillbementioned.A
block diagram of the microcontroller core is shown in
Figure 3–1 below.
Bus Organization
TherearefourmajorbussesintheSecureMicroproces-
sor:theInternalDataBus,theInternalAddressBus,the
Byte–wideMemory Bus,andthe ExpandedBus.Allad-
dressesand data whichare transferred duringprogram
executionare passed on theInternalAddress and Data
Busses. User Program and Data Memory is always ac-
cessed from either the byte–wide Program/Data RAM
orfrom externalmemory locatedon theExpandedBus.
The Byte–wide Memory Bus is used for access to Pro-
gram/DataRAM inthesame fashionasan 8051Family
devicewouldaccessinternalROMorEPROMmemory.
This bus can be used in place of the Expanded Bus,
freeing Port 2 and Port 0 pins for general I/O use.
CPU Registers
AlloftheCPUregistersaremappedasSpecialFunction
Registers(SFR’s)andareidenticalinnumberandfunc-
tion to those present within the 8051. These registers
are described briefly below:
Accumulator
The Accumulator (A) is used as either a source or des-
tinationregister in allarithmetic instructions. Itmayalso
be used in most other types of instructions.
Stack Pointer
TheStackPointer(SP)isan8–bitregisterwhichisused
to mark the location of the last byte of data stored in the
stack. The stack itself may be located anywhere in the
on–chip 128–byte Scratchpad register area. The Stack
Pointer pre-increments during a stack push and post-
decrements during a stack pop.
B Register
The major function of the B register is as a source and
destination register during multiply and divide instruc-
tions. It may also be used as a scratchpad register.
Program Status Word
The Program Status Word (PSW) contains status flags
that are set according to the results of a previously
executedinstruction.Inaddition,thePSWcontainsreg-
ister bank select bits.
Data Pointer
The Data Pointer (DPTR) is used to access Data
MemorythatmaybemappedintoByte–wideDataRAM
orontoexternalmemorydevicesontheExpandedBus.
It is accessed by the user’s program as either two 8–bit
Special Function registers or as a 16–bit register with
certain instructions.
Scratchpad Registers
Scratchpadregisters are 128 registers wheredatamay
bestoreddirectly.Theyareaddressedfrom00Hto7FH
andmaybeaccessedbyaMOVinstruction.Includedin
the scratchpad area are four 8–byte banks of working
registers. These registers are not part of the data
memory map.
Serial I/O
The on–chip serial I/O port is comprised of a receive
databuffer,atransmitdatabuffer,andacontrolregister.
Boththereceivedatabufferandthetransmitdatabuffer
are accessed in a single location (SBUF) in the Special
Function Register map. The control register (SCON) is
accessed in an separate location. When the serial I/O
function is enabled, two external I/O pins (P3.0, P3.1)
are re–assigned in hardware to serve the transmit and
receive data functions.
Programmable Timers
Two 16–bit programmable timers are included that can
performvarioustimingandcountingfunctions.Atotalof
four registers (TH1, TL1, TH0, and TL0) access the up-
per and lower halves of each of the twotimer/counters.
A single control register (TCON) is used to select the
variousoperatingmodesofthetwotimers.Twoexternal
I/O pins (P3.4, P3.5) may be programmed to serve as
external counter inputs, one pin for each of the two tim-
er/counters.

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SECURE MICROCONTROLLER ARCHITECTURAL BLOCK DIAGRAM Figure 3–1
15
8
CE1
CE2 R/W
ADDRESS
ENCRYPTOR
DATA
ENCRYPTOR
TIMING
AND
CONTROL
TAMCONSECURITY
LOCK
LOGIC
PCON
TIMED
ACCESS
LOGIC
MEMORY
ALLOCATIONS
CTL. LOGIC
NONVOLATILE
CONTROL
INTERRUPT
CONTROL
IP IE
INTERNAL DATA BUS
STACK
POINTER
PSW
IDR ADDR.
REGISTER
128
SCRATCH–
PAD
REGISTERS
WATCHDOG
TIMER
OSCILLATOR
INSTRUCTION
REGISTER
TIMING
AND
CONTROL
VCC VLI
XTAL1 XTAL2
VECTOR
RAM
PORT 0
LATCH
TEMP 1 TEMP 2
ACC
ALU
B
REGISTER
DPTR
BUFFER
PROGRAM
ADDR. REG.
PC
INCREMENTOR
PC
RESIDENT
LOADER
ROM
PORT 2
LATCH
INTERNALADDRESS BUS
INTERNAL DATA BUS
DRIVERSDRIVERS
PORT 2
DRIVERS
PORT 0
DRIVERS
ENCRYPT
KEY
88
8 8
8 8
16
SERIAL
I/O
TIMER
0
TIMER
1
TH1
TL1
TCON
TLMOD
TH0
TL0
SBUF
SCON
PORT 3
DRIVERS
PORT 1
DRIVERS
PORT 1
LATCH PORT 3
LATCH
16
INTERNALADDRESS BUS
BYTE–WIDE
MEMORY
BUS
PSEN
ALE
EA
RST
EXTERNAL
PROGRAM/
DATA RAM

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9
Parallel I/O
Four SFR’s provide access for the four parallel I/Oport
latches.TheseI/OportsaredenotedasP0,P1,P2,and
P3. A total of 32 bits of parallel I/O is available through
these I/O ports. However, up to 16 bits are sacrificed
whentheExpandedBusmodeisusedtointerfacetoex-
ternalmemoryanduptosixbitsmaybesacrificedifany
external interrupt inputs, timer counter inputs, or serial
I/Ofunctionsare used. Whenusing theByte–widebus,
ports are not affected.
Program/Data RAM Interface
Secure Microcontrollers provide a non–multiplexed
Byte–wide bus that connects to external SRAM. They
also make this RAM nonvolatile, decode memory ac-
cessforit,andwrite–protectportionsdesignatedaspro-
gram memory. The Byte–wide bus consists of up to 16
address lines (depending on the version), eight data
lines, read/write control, and decoded chip enables.
WhenaccessingtheSRAMviaitsByte–widebus,there
is no activity on the ports. Thus if memory access is re-
stricted to this bus, all ports are free for use by the
application. In module form, the microprocessor is al-
ready connected to SRAM via the Byte–wide bus mak-
ing program and data memory access appear internal.
Secure Microprocessors can also access memory us-
ing the multiplexed Expanded Bus consisting of Port 0
and2,WR(P3.6)andRD(P3.7).Thisisusuallyundesir-
able since it consumes port pins that can be used for
other activity. If Expanded bus access is desired, up to
64K ROM and 64K RAM can be accessed in the same
mannerasatraditional8051.Eachversionhasdifferent
provisions for using the Expanded bus, depending on
memory map and user’s configuration. These issues
are discussed under the Programmer’s Guide.
High–Reliability Circuitry
This feature ensures proper operation of the micro and
maintainsthe contents ofthe Program/DataRAMin the
absence of VCC using a self–contained lithium energy
source. The logic provided includes the Power Fail
Warning Interrupt, Automatic Power Down and Power
On Reset. As a result, the Program/Data RAM may be
modified whenever necessary during execution of the
user’s software but will remain unchanged whenVCC is
absent. The circuitry also maintains the Internal
ScratchpadRAMandcertainSpecialFunctionregisters
during a power down condition.
Software Encryption Logic
DS5000 and DS5002 series parts provide software se-
curity circuits that include the Address Encryptor, Data
Encryptor, and the Encryption Key Word. When the de-
vice is operating in the Encryption mode and using the
Program/Data RAM, the Address Encryptor is used to
transform “logical” addresses on the Internal Address
Bus into encrypted addresses which appear on the
Byte–wide Memory Bus to the RAM. Similarly, the Data
Encryptor transforms data on the Internal Data bus into
encrypted data during write operations on the Byte–
wideMemorybus.Whendataisreadback,theDataEn-
cryptor restores it to its true value. Although each en-
cryptor uses its own algorithm for encrypting data, both
depend on the Encryption Key Word stored on–chip.
Security Lock Logic
The Security Lock logic prevents a read or write to any
Program/DataRAMlocationusingthebootstraploader.
Inaddition,itinhibitsthedevicefromfetchingcodeinthe
Expanded Bus Mode. By disabling access to key inter-
nal resources, this feature precludes unauthorized dis-
assemblyofapplicationsoftwarecontainedinProgram/
Data RAM. In contrast with an EPROM security bit,
clearing the Security Lock wipes the entire RAM area.
Vector RAM
The Vector RAM is used to contain the reset and inter-
ruptvectorcodewhentheSoftMicrocontrollerisoperat-
ing in the Encryption mode. This feature is included to
insure the security of the application software. The op-
eration of the Vector RAM as well as the reason for its
inclusion in the architecture are discussed in the
Software Security section.
Timed Access Logic
The Timed Access logic is usedto protect againstinad-
vertent changes to configuration and to the Program
RAM in the event of a loss of software control. The pro-
tected configuration parameters include the Partition
AddressbitsintheMCONregister,aswellastheEnable
Watchdog Timer bit, Stop Mode bit, and Power On Re-
set bit in the PCON register.

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Watchdog Timer
Whentheuser’ssoftwareisbeingexecuted,theWatch-
dog Timer can be used to automatically restart the pro-
cessorin theeventthat softwarecontrol is lost.It isalso
usedtogenerateanoscillatorstart–updelaytoallowthe
clock frequency to stabilize. This occurs during reset
cyclesthatfollowatimein whichtheoscillator hasbeen
stopped (Stop Mode Reset and Power On Reset).
Resident Loader ROM
The Resident Loader ROM contains firmware that con-
trols the initial loading of the nonvolatile Program/Data
RAM. The firmware provides Serial Bootstrap Load op-
eration via the on–chip serial port. The internal ROM is
not accessible by the user and performs the loading
function only when the device is strapped for operation
in the Program mode. The ROM becomes transparent
to the user once loading is complete and has no effect
on the memory map.