MPS MP5515 User manual

MP5515
Wide Input 2.7 - 18V, 5A, High-Efficiency
Bidirectional, Power Back-Up Manager
with Integrated Hot-Swap, I2C, ADC,
and Cap Health Test
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© 2018 MPS. All Rights Reserved.
DESCRIPTION
The MP5515 is an input power conditioning
PMIC targeting enterprise solid-state drives,
NVDIMM, and other applications with back-up
system requirements. The MP5515 consists of
input current limiting, input reverse current
blocking, and an MPS-patented, high-efficiency,
bidirectional, boost-buck converter with only
one inductor for energy storage and system
back-up power when there is an input power
failure. The MP5515 also provides I2C interface
and ADC. By using the I2C, users can set the
input current limit, slew rate, and perform cap
health tests. The MP5515 can also monitor
system status, such as input voltage, input
current, storage voltage, temperature, and
provide interrupt options for these features.
The internal input current-limit block prevents
inrush current during system start-up while the
reverse-current block prevents backup energy
from flowing to the failing VIN port. MPS’s
patented energy storage and release
management control circuit minimizes the
storage capacitor requirement. It pumps the
input voltage to a higher backup voltage and
releases the energy over a hold-up time to the
system bus voltage in case of an input outage.
The MP5515 requires a minimal number of
standard, external components and is available
in a 30-pin QFN (5mmx5mm) package.
FEATURES
Wide 2.7V-to-18V Operating Input Range
Up to 32V Programmable Storage Voltage
Up to 6A Programmable Input Current Limit
5A Buck Load Capability
Adjustable Slew Rate for VB Voltage Rising
Input Current Limiter with Integrated 14mΩ
MOSFET
Input Over-Voltage Protection (OVP)
Reverse-Current Protection (RCP)
Input Power Failure Indicator
Backup Capacitor Health Test
Comprehensive Voltage, Current,
Temperature Sensor ADC Conversion
Thermal Protection
Available in a QFN-30 (5mmx5mm)
Package
APPLICATIONS
Solid-State Drives (SSD)
NVDIMMs
Hard-Disk Drives
Power Back-Up Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP5515
12V
22µF
30V
PFI
PGB
RTEST
TPOR
R1
R2 EN
OVP
DET
VIN
FBB
VB CST BST
SW
VBO
STRG
FBS
PGND
AGNDILIM INT
DVDT
R6
R5
C4
C5
C6
C2
C1
VIN
STRG
R7
R3
R4
L1
VB
To DCDC
12kΩ
11kΩ
100kΩ
105kΩ
12.4k
Ω
10nF
1µF
10µH
365kΩ
10kΩ
1000µF
VCC
C3
1µF
ICH
TEMP
R8
5.1kΩ
SCL
PGS
SDA
R9
R10
11kΩ
200kΩSAS
D1
TVS
optional
for spike
0.1µF
VSTRG Release
VIN = 12V, VB= 7.5V, VB load = 5A
CH1: VB
5V/div.
CH2: VSTRG
10V/div.
CH3: VPFI
5V/div.
CH4: IL
5A/div.
5ms/div.

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ORDERING INFORMATION
Part Number
Package
Top Marking
MP5515GU*
QFN-30 (5mmx5mm)
See Below
EVKT-5515
Evaluation Kit
* For Tape & Reel, add suffix –Z (e.g. MP5515GU–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP5515: Product code of MP5515GU
LLLLLLL: Lot number
EVALUATION KIT EVKT-5515
EVKT-5515 Kit contents: (Items can be ordered separately).
#
Part Number
Item
Quantity
1
EV5515-U-00A
MP5515GU evaluation board
1
2
EVKT-USBI2C-02
Includes one USB to I2C dongle, one USB cable, and one
ribbon cable
1
3
Tdrive-5515
USB flash drive that stores the GUI installation file and
supplement documents
1
Order direct from MonolithicPower.com or our distributors.
USB to I2C Dongle
USB Cable Ribbon Cable
Input Power
Supply
EV5515-U-00A
Load
Input
Output
GUI
Figure 1: EVKT-5515 Evaluation Kit Set-Up

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PACKAGE REFERENCE
TOP VIEW
ILIM
DVDT
PFI
SAS
OVP
TPOR
FBB
ICH
TEMP
SCL
SDA
INT
1
2
3
4
5
6
7
20
19
18
VCC
21
22
FBS
23
AGND 9
PGB
8
CST
24
16
17
RTEST
DET 10
VIN
11
VIN
30
VB
VB
SWPGND
VBO
25 BST
EN
12 13 14
29 28 27
15
26
PGS
STRG
QFN-30 (5mmx5mm)
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN).....................................21V
VB, VBO ............................................-0.3V to 21V
VSTRG, VRTEST ...................................-0.3V to 36V
VSW...........-0.3V (-6V for <10ns) to VSTRG + 0.3V
VBST ......................................-0.3V to VSTRG + 6V
VCST.................................................-0.3V to 28V
All other pins.....................................-0.3V to 6V
EN current...............................................1mA(2)
PFI, PGB, PGS, INT current...................5mA(3)
RTEST current....................................500mA(3)
Continuous power dissipation (TA=+25°C) (4) (7)
................................................................. 3.57W
Junction temperature................................150°C
Lead temperature .....................................260°C
Storage temperature................ -65°C to +150°C
Recommended Operating Conditions (5)
Supply voltage (VIN).................... 2.7V (6) to 18V
Bus voltage (VB)...............................2.6V to 16V
Storage voltage (VSTRG)........VIN_MAX + 3V to 32V
Max input current........................................... 6A
Max buck-release current ..............................5A
EN current............................................0.5mA (2)
Operating junction temp. (TJ)... -40°C to +125°C
Thermal Resistance θJA θJC
QFN-30 (5mmx5mm)
EV5515-U-00A (7).................35...... 6.5.... °C/W
JESD51-7 (8).........................36........8 ..... °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) For more detail, refer to the Enable Control section on page
22.
3) When these pins are pulled up to the power source, the
current should be limited below the maximum value.
4) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
5) The device is not guaranteed to function outside of its
operating conditions.
6) Guaranteed for temperature conditions 25°C or higher. If the
temperature is lower than 25°C, one Schottky diode from VIN
to VCC is recommended to help start-up from a 2.7V input.
7) Measured on EV5515-U-00A, 2-layer 63mmx63mm PCB.
8) Measured on JESD51-7, 4-layer PCB.

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ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ= -40°C to 125°C (9), typical value is tested at TJ= 25°C, unless otherwise
noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
Power Supply
Supply current (shutdown)
IS
EN = 0V, then power on VIN,
TJ= 25°C
2.5
5
μA
Supply current (quiescent)
IQ
SAS = 2V, EN = 2V, VFBB/FBS/DET
= 1.1V
1.5
mA
SAS = 0V, EN = 2V, VFBB/FBS/DET
= 1.1V
2.5
3
mA
VCC regulator
VCC
VIN or VB = 6V, Ivcc = 1mA
4.75
5
5.25
V
VIN under-voltage lockout
threshold rising (10)
INUVR
VCC floating, TJ= 25°C
2.5
2.68
V
VIN under-voltage lockout
threshold hysteresis
INUVHYS
0.1
V
VIN to VB current limit
MOSFET on resistance
RDSON
14
mΩ
VIN to VB continuous current
limit
ILIM
RILIM = 36.5kΩ, TJ= 25°C
1.92
2
2.08
A
RILIM = 36.5kΩ, TJ= -40°C to
125°C
1.88
2
2.12
A
Off state leakage current
ILEAK
VIN = 12V, VB= 0V or VB= 12V,
VIN = 0V, TJ= 25°C
2
3
μA
VB clamping voltage
VCLAMP
VIN = 18V
15.2
16
16.8
V
VB rise time (DVDT) control
(11)
TDVDT
DVDT floating, VIN = 12V, DVDT
bits = 00, test VB rise time
1.6
ms
IDVDT
Connect capacitor to DVDT, test
DVDT charge current
3
μA
Internal reset delay-time
control
TDLY
TPOR floating, test reset delay
time
1.5
ms
ITPOR
Connect capacitor to TPOR, test
TPOR charge current
1
μA
Energy Storage and Release
Storage pre-charge current
ICH-PRE
250
350
450
mA
Boost disconnect switch RON
Rdison
30
mΩ
Switching peak current @
boost mode
ICH
ICH floating, L = 10μH
2
A
RICH= 200kΩ, L = 10μH
0.65
A
Energy management HS RON
RHon
80
mΩ
Energy management LS RON
RLon
40
mΩ
Feedback voltage
VFBB-REF,
VFBS-REF,
VDET-REF
TJ= 25°C
0.792
0.8
0.808
V
TJ= -40°C to 125°C
0.786
0.812
Feedback current
IFBB, IFBS,
IDET
VFBB = VFBS = VDET = 0.85V
10
50
nA

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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, VEN = 2V, TJ= -40°C to 125°C (9), typical value is tested at TJ= 25°C, unless otherwise
noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
VIN over-voltage threshold
VOVP
OVP pin voltage rising
0.81
V
VIN over-voltage hysteresis
VOVP-HYS
OVP pin voltage hysteresis
45
mV
Vs over-voltage threshold
VS-OVP
1.1
VFBS-
REF
VIN to VB ISOFET turn-on
voltage
VIN - VB, VB = 5V, then start
VIN
0.2
V
VIN to VB ISOFET shut-down
current
IIN-VB-OFF
PFI = low
-250
0
mA
PFI high threshold
PFIH
1.02
VDET-
REF
PFI low threshold
PFIL
0.99
VDET-
REF
PFI falling delay
PFID-L
0.5
μs
PFI rising delay
PFID-H
200
μs
PFI sink current capability
VPFI
Sink 4mA
0.3
V
PGB high threshold
PGH-VB
0.95
VFBB-
REF
PGB low threshold
PGL-VB
0.9
VFBB-
REF
PGB delay
PGD-VB
Rising and falling edge
5
μs
PGB sink-current capability
VPG-VB
Sink 4mA
0.3
V
PGS high threshold
PGH-S
PGS threshold bits = 1111
0.97
VFBS-
REF
PGS low threshold
PGL-S
PGS threshold bits = 1111
0.95
VFBS-
REF
PGS delay
PGSD-S
Rising and falling edge
25
μs
PGS sink-current capability
VPG-S
Sink 4mA
0.3
V
Buck-mode dumping valley
current limit
IDUMP-VALLEY
5
6.5
A
Release-buck switching
frequency
fs-RLS
VSTRG from 32V to 10V,
buck_Fsw bits = 100
380
480
580
kHz
VB under-voltage lockout
threshold rising (10)
INUVBR
2.2
2.35
2.5
V
VB under-voltage lockout
threshold hysteresis (10)
INUVBHYS
0.1
V
ADC
Voltage range
0
1.28
V
ADC resolution (12)
10
bits
ADC conversion time (12)
ADC conversion for one data
45
μs

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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, VEN = 2V, TJ= -40°C to 125°C (9), typical value is tested at TJ= 25°C, unless otherwise
noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
Logic Interface (SDA, SCL, INT, SAS, EN)
High-level input voltage
VIH
SDA, SCL, SAS, EN
1.2
V
Low-level input voltage
VIL
SDA, SCL, SAS, EN
0.4
V
Low-level output voltage
VOL
Sink 4mA, SDA, INT
0.3
V
Input leakage current
ILKG
Connected to 6V, SCL
10
nA
High level output leakage
Open drain, connected to 6V,
SDA
10
nA
Protection
Thermal shutdown, forced
backup (12)
TSD
150
°C
Thermal shutdown, forced
backup hysteresis (12)
THYS
25
°C
Thermal warning (12)
TWRN
120
°C
NOTES:
9) Guaranteed by over-temperature correlation, not tested in production.
10) VIN UVLO controls the IC start-up voltage threshold. VB UVLO controls energy storage and release circuitry. The internal VCC is
powered from both VIN and VB. If either VIN or VB is higher than UVLO, the IC will not shut down.
11) Refer to the “Power-On Reset Delay and VB Rising Control” section on page 19 for detailed calculations.
12) Guaranteed by characterization, not tested in production.

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I2C PORT SIGNAL CHARACTERISTICS
Parameter
Symbol
Condition
Cb = 100pF
Cb = 400pF
Units
Min
Max
Min
Max
SCLH and SCL clock
frequency
fSCHL
0
3.4
0
0.4
MHz
Set-up time for a
repeated start condition
τSU;STA
160
-
600
-
ns
Hold-time (repeated)
start condition
τHD;STA
160
-
600
-
ns
Low period of the SCL
clock
τLOW
160
-
1300
-
ns
High period of the SCL
clock
tHIGH
60
-
600
-
ns
Data set-up time
τSU:DAT
10
-
100
-
ns
Data hold time
τHD;DAT
0
70
0
-
ns
Rise time of SCLH signal
τrCL
10
40
20*0.1Cb
300
ns
Rise time of SCLH signal
after a repeated start
condition and after an
acknowledge bit
τfCL1
10
80
20*0.1Cb
300
ns
Fall time of SCLH signal
τfCL
10
40
20*0.1Cb
300
ns
Rise time of SDAH signal
τrDA
10
80
20*0.1Cb
300
ns
Fall time of SDAH signal
τfDA
10
80
20*0.1Cb
300
ns
Set-up time for stop
condition
τSU;STO
160
-
600
-
ns
Bus free time between a
stop and start condition
τBUF
160
-
1300
-
ns
Data valid time
τVD;DAT
-
16
-
90
ns
Data valid acknowledge
time
τVD;ACK
-
160
-
900
ns
Pulse width of spikes
that must be suppressed
by the input filter
tSP
0
10
0
50
ns
Capacitive load for each
bus line
Cb
SDAH and SCLH line
-
100
-
400
pF
SDAH + SDA line and
SCLH + SCL line
-
400
-
400
pF

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TYPICAL CHARACTERISTICS
VIN = 12V, VBRLS = 7.5V, L = 10µH, TA= 25°C, unless otherwise noted.
0
0.5
1
1.5
2
2.5
3
0 3 6 9 12 15 18
QUIESCENT CURRENT(mA)
INPUT VOLTAGE (V)
Quiescent Current vs. Input Voltage
EN=high,VFBB=VDET=VFBS=1V
SAS=0V
SAS=2V
0
1
2
3
4
5
0 5 10 15 20
SHUTDOWN CURRENT (uA)
INPUT VOLTAGE (V)
Shutdown Current vs. Input Voltage
EN=0V
0.6
0.7
0.8
0.9
1
1.1
1.2
-40 -20 020 40 60 80 100 120 140
EN THRESHOLD(V)
JUNCTION TEMPERATURE(OC)
EN UVLO Threshold vs. Temperature
EN-UVLO_Rising
EN_UVLO_Falling
400
420
440
460
480
500
-40 -20 020 40 60 80 100 120 140
SWITCHING FREQUENCY(kHz)
JUNCTION TEMPERATURE(OC)
Buck Switching Frequency vs. Temperature
STRG=24V
0
1
2
3
4
5
-40 -20 020 40 60 80 100 120 140
DVDT CHARGING CURRENT(uA)
JUNCTION TEMPERATURE(OC)
DVDT Charge Current vs. Temperature
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
-40 -20 020 40 60 80 100 120 140
TPOR CHARGING CURRENT(UA)
JUNCTION TEMPERATURE(OC)
TPOR Charge Current vs. Temperature

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TYPICAL CHARACTERISTICS (continued)
VIN = 12V, VBRLS = 7.5V, L = 10µH, TA= 25°C, unless otherwise noted.
4
5
6
7
8
-40 -20 020 40 60 80 100 120 140
BUCK VALLEY CURRENT LIMIT(A)
JUNCTION TEMPERATURE(OC)
Buck Valley Current Limit vs. Temperature
0
10
20
30
40
50
020 40 60 80 100
VB RISE TIME(mS)
DVDT CAPACITANCE(nF)
VBRising Time vs. DVDT Capacitance
VIN=5V
VIN=12V
0
1
2
3
4
5
6
7
8
010 20 30 40 50 60 70 80 90 100
HOT-SWAP CURRENT LIMIT(A)
ILIM RESISTANCE(kΩ)
Hot-swap Current Limit vs. ILIM Resistor
0
100
200
300
400
500
600
700
800
900
1000
0 1 2 3 4 5 6
VOLTAGE ON ILIM(mV)
INPUT CURRENT(A)
ILIM Monitor Voltage vs. Input Current
RILIM=12kΩ
0
0.5
1
1.5
2
2.5
3
3.5
4
0100 200 300 400 500 600
BOOST CURRENT PEAK(A)
ICH RESISTANCE(kΩ)
Boost switching Peak Current vs.
ICH Resistor
400
450
500
550
600
650
700
750
800
-40 -20 020 40 60 80 100 120 140
BOOST CURRENT PEAK(mA)
JUNCTION TEMPERATURE(OC)
Boost switching Peak Current vs. Temperature
RICH=200kΩ

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TYPICAL CHARACTERISTICS (continued)
VIN = 12V, VBRLS = 7.5V, L = 10µH, TA= 25°C, unless otherwise noted.
Boost Pre-Charge Current vs.
Temperature
FBS vs. Temperature
300
320
340
360
380
400
-40 -20 020 40 60 80 100 120 140
PRE-CHARGE CURRENT(mA)
JUNCTION TEMPERATURE(OC)
700
725
750
775
800
825
850
875
900
-40 -20 020 40 60 80 100 120 140
FBSVOLTAGE(mV)
JUNCTIONTEMPERATURE(°C )
FBB vs. Temperature
Hot-Swap Current Limit vs.
Temperature
700
725
750
775
800
825
850
875
900
-40 -20 020 40 60 80 100 120 140
FBB VOLTAGE(mV)
JUNCTIONTEMPERATURE(°C )
1.8
1.9
2.0
2.1
2.2
-40 -20 020 40 60 80 100 120 140
HOT-SWAP CURRENT
LIMIT(A)
JUNCTIONTEMPERATURE(°C )

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TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VSTRG = 30V, VPFI = 8V, VBRLS = 7.5V, L = 10µH, ILOAD = 5A, TA= 25°C, unless otherwise
noted.
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8
STORAGE VOLTAGE(V)
CHARGE TIME(s)
Storage Voltage vs. Charge Time
RICH=200kΩ
Vs Cap=1000uF
Vs Cap=2200uF
10
15
20
25
30
35
40
0 0.05 0.1 0.15 0.2
STORAGE VOLTAGE(V)
CHARGE TIME(s)
Storage Voltage vs. Charge Time
RICH=Float
Vs Cap=1000uF
Vs Cap=2200uF
0
50
100
150
200
250
01000 2000 3000 4000 5000
RELEASE TIME(ms)
STORAGE CAPACITANCE(uF)
Rlelease Time vs. STRG Capacitance
VB_load=1A
VB_load=3A
60
65
70
75
80
85
90
95
100
510 15 20 25 30 35
EFFICIENCY(%)
STORAGE VOLTAGE (V)
Buck Efficiency
VB=2.9V, L=4.7uH
IB=1A
IB=3A
IB=5A
60
65
70
75
80
85
90
95
100
510 15 20 25 30 35
EFFICIENCY(%)
STORAGE VOLTAGE (V)
Buck Efficiency
VB=7.5V, L=10uH
IB=1A
IB=3A
IB=5A
60
65
70
75
80
85
90
95
100
510 15 20 25 30 35
EFFICIENCY(%)
STORAGE VOLTAGE (V)
Buck Efficiency
VB=10V, L=10uH
IB=1A
IB=3A
IB=5A

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VSTRG = 30V, VPFI = 8V, VBRLS = 7.5V, L = 10µH, ILOAD = 5A, TA= 25°C, unless otherwise
noted.
Input Power-On
VBload = 5A
EN Turn-On
VB load = 5A
CH1: VB
5V/div.
CH2: VIN
10V/div.
CH3: VPFI
5V/div.
R2: VSTRG
20V/div.
CH4: IL
1A/div.
CH1: VB
5V/div.
CH2: VEN
5V/div.
CH3: VPFI
5V/div.
R2: VSTRG
20V/div.
CH4: IL
1A/div.
100ms/div.
100ms/div.
Boost Steady State
RICH = 200kΩ
Buck Steady State
VB load = 0A, 22µF ceramic cap on VB
CH2:
VSTRG_AC
200mV/div.
CH3: VSW
20V/div.
CH4: IL
500mA/div.
CH1:
VB_AC
200mV/div.
CH3: VSW
20V/div.
CH4: IL
1A/div.
100ms/div.
500ms/div.
Buck Steady State
VB load = 3A, 22µF ceramic cap on VB
Buck Steady State
VB load = 5A, 22µF ceramic cap on VB
CH1:
VB_AC
100mV/div.
CH3: VSW
20V/div.
CH4: IL
2A/div.
CH1:
VB_AC
100mV/div.
CH3: VSW
20V/div.
CH4: IL
2A/div.
2µs/div.
2µs/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VSTRG = 30V, VPFI = 8V, VBRLS = 7.5V, L = 10µH, ILOAD = 5A, TA= 25°C, unless otherwise
noted.
VSTRG Release
VB load = 1A
VSTRG Release
VB load = 3A
CH1: VB
5V/div.
CH2: VSTRG
10V/div.
CH3: VPFI
5V/div.
CH4: IL
2A/div.
CH1: VB
5V/div.
CH2: VSTRG
10V/div.
CH3: VPFI
5V/div.
CH4: IL
2A/div.
20ms/div.
5ms/div.
VSTRG Release
VB load = 5A
CH1: VB
5V/div.
CH2: VSTRG
10V/div.
CH3: VPFI
5V/div.
CH4: IL
5A/div.
5ms/div.

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PIN FUNCTIONS
QFN-30
Pin #
Name
Description
1
CST
Storage capacitor for the internal charge pump. A10nF capacitor is required
between CST and AGND to drive the input current-limit MOSFET and disconnection
MOSFET. Do not connect CST to a capacitor over 47nF.
2
VCC
Internal LDO output. VCC provides power for the internal circuits. Decouple VCC
with a minimum 1µF ceramic capacitor placed as close to VCC as possible. Do not
add an external load to VCC.
3
TPOR
Power-on reset delay. Connect a capacitor 1nF or higher between TPOR and AGND
to determine the power-on reset delay time. Leave TPOR floating for the 1.5ms
default power-on reset delay time
4
OVP
Over-voltage detection. A resistor divider from VIN to OVP can program the input
over-voltage threshold. If the OVP voltage is higher than 0.81V, the MP5515 is forced
into buck mode and recovers when the OVP voltage drops to 0.765V and VB triggers
VB_UVLO with a new TPOR time as the first power-on in default. Connect OVP to
AGND if the OVP function is not needed.
5
SAS
Configured as SAS function. When applying a high-level voltage on SAS, the input
current limit switch turns off, and backup mode begins operating. When VB and VSTRG
are discharged to UVLO, buck_release shuts down, but VCC continues working. SAS
is pulled down internally through a 4MΩresistor.
6
PFI
Power failure indicator. PFI is an open-drain output. To indicate a signal, PFI should
be pulled up to a power source through a resistor. PFI goes high if the DET voltage
exceeds 1.02 x VDET-REF. PFI goes low if the DET voltage drops below 0.99 x VDET-REF.
Once PFI is pulled low, a 200µs blanking time keeps PFI low. PFI is pulled down if
SAS, OTP, or EN is off. If PFI is pulled up to another external DC source, PFI can still
be pulled low when EN is low. If both VIN and VCC are not available, PFI is pulled low
to about 0.85V.
7
DVDT
Bus voltage start-up slew rate control. Connect a capacitor 1nF or higher from
DVDT to AGND to program different VB charge-up slew rates. The DVDT time can be
controlled by the I2C if DVDT is floating.
8
ILIM
DC input current limit. Connect a resistor between ILIM and AGND to adjust the DC
current limit from VIN to VB. Apply a voltage higher than 1.5V on ILIM to trigger OCP
and disable the ISOFET from VIN to VB.
9
AGND
IC signal ground.
10
DET
Input voltage detection sense. DET sets the buck release start voltage when VIN
drops.
11, 30
VIN
Input supply voltage. Place a 0.1µF ceramic capacitor as close to VIN as possible. A
TVS diode at the input is necessary if the VIN power line is long and the VIN voltage
spike is high in the system. Otherwise, the TVS can be ignored. Refer to the Selecting
the Input Capacitor and TVS section on page 37 for more detail.
12, 29
VB
Bus voltage. A 22μF to 47μF ceramic capacitor is required as close to VB as
possible.
13
EN
On/off control. EN enables or disables the internal circuits. When EN is low, the
MP5515 is forced to buck mode until VSTRG is discharged. The IC shuts down after VB
drops, and EN is pulled down internally through a 4MΩresistor. There is more sink
current on EN if a voltage 2V or higher is forced on EN.
14
VBO
Source of the internal disconnect MOSFET. Connect an inductor between SW and
VBO for backup boost charge and buck release operation.

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PIN FUNCTIONS (continued)
QFN-30
Pin #
Name
Description
15
PGS
Storage voltage power good indicator. By default with the PGS threshold bits =
1111, PGS goes high if the FBS voltage exceeds 0.97 x VFBS-REF. PGS goes low if the
FBS voltage drops below 0.95 x VFBS-REF. PGS can be programmed by the PGS
threshold bits. PGS is driven by an internal circuit, which does not require an external
pull-up. PGS is low even if the IC is disabled, but if both VIN and VCC power are not
available, PGS is pulled low to about 1.3V.
16
PGB
Bus voltage power-good indicator. PGB goes high if the FBB voltage exceeds 0.95
x VFBB-REF. PGB goes low if the FBB voltage drops below 0.9 x VFBB-REF.PGB is driven
by an internal circuit, which does not require an external pull-up. PGB is low even if
the IC is disabled, but if both VIN and VCC power are not available, PGB is pulled low
to about 1.3V.
17
INT
Interrupt output from the MP5515. INT is an open-drain output. Even if INT is pulled
up to external DC source, INT is pulled low when EN is low and the IC is not in buck
switching mode. If both VIN and VCC are not available, INT is pulled low only to about
0.85V.
18
SDA
I2C serial data.
19
SCL
I2C serial clock.
20
TEMP
Temperature sensor input from thermistor to ADC.
21
ICH
Boost-mode charge switching peak current programmable. Float ICH to set the
boost switching peak current at 2A.
22
FBB
Bus voltage feedback sense. FBB regulates the bus voltage in buck mode.
23
FBS
Storage voltage feedback sense. FBS sets the storage voltage in boost mode.
24
RTEST
Resistor connect for capacitor health test. In backup capacitor health test mode,
RTEST is pulled to GND internally. One resistor from STRG to RTEST can discharge
the backup capacitor. The discharge current through RTEST must be limited below
500mA.
25
BST
Bootstrap. A bootstrap capacitor is required from BST to SW to supply the high-side
switch driver.
26
STRG
Backup energy storage. Connect a backup capacitor to STRG for energy storage
and release operation.
27
SW
Switch output. SW is used for the energy storage and release circuitry. Connect an
inductor between SW and VBO.
28
PGND
Power ground.

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BLOCK DIAGRAM
HS Drive
LS Drive
Control for Current Limit & Energy Management Circuit
VIN
FBB
VB VBO SW BST
STRG
FBS
PGND
FBS
DET
5V LDO
VCC
PFI
Charge Pump
CST
RTEST
Register
Memory I2C
SDA
SCL
ADC
TEMP
Vin Iin Vs
PGS
PGB
ILIM
OVP
INT
EN
SAS
DVDT
TPOR
ICH
AGND
Figure 2: Functional Block Diagram

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OPERATION
The MP5515 is an energy backup and
management unit in a QFN-30 (5mmx5mm)
package. The MP5515 provides a very compact
and efficient energy management solution for
typical solid-state drive or hard disk drive
applications. MPS’s patented lossless energy
storage and release management circuits use a
bidirectional buck-boost converter to achieve
optimal energy transfer and provide the most
cost-effective energy storage solution.
The integrated boost converter raises the
energy backup voltage level. The backup
feedback resistor divider sets the backup
voltage. If the input shuts down suddenly, the
internal buck converter transfers the energy
from the backup capacitor to the bus and holds
the bus voltage when the system consumes the
energy from the backup capacitor.
The MP5515 also features an I2C interface.
This interface can be used to write the control
command and the monitor system status. One
integrated ADC converter converts the voltage,
current, and temperature sensor signals.
Start-Up
When the VIN power is higher than its under-
voltage lockout (UVLO) threshold, the VCC and
I2C interface is enabled. After the power-on
reset delay time, if VCC is ready and VIN is
0.2V higher than VB, the isolation MOSFET
(ISOFET) from VIN to VB is turned on, and the
bus capacitor is charged from 0V to VIN
controlled by the DVDT slew rate.
When the DVDT voltage is saturated, the
backup boost converter is unlocked and can be
enabled by the register bits. There is a timer for
~1.2ms of delay time before starting the boost
converter to ensure that the ISOFET is fully
turned on.
The backup boost converter is enabled by
default. The storage voltage is charged up with
about 350mA of trickle current during the pre-
charge period. Once the storage voltage is
close to VB, the boost switching circuit initiates,
and the storage voltage is boosted and
regulated to the target voltage (see Figure 3).
MP5515
VIN
UVLO Vcc
VB
DVDT 1.2ms delay before charge Vs
VSTRG Voltage
Charge in boost switch mode
boost is unlocked
after this point
ENCH bit(default=1)
Trickle pre-charge
TPOR
Complete
Figure 3: System Power-Up Sequence
Back-Up Voltage
After the start-up period, the internal boost
converter regulates the backup voltage to the
set value automatically. The MP5515 uses
burst mode to minimize the converter’s power
loss. When the storage voltage drops below the
set voltage, burst mode initiates and charges
the storage capacitor.
During the boost period, the boost switching
current limit and the low-side MOSFET (LS-FET)
control the boost. When the LS-FET turns on,
the inductor current increases until it reaches its
peak current level set by ICH. After reaching
the peak current level, the LS-FET turns off for
the set minimum off time. At the end of this
minimum off time, if the feedback voltage
remains below the 0.8V internal reference, the
LS-FET turns on again. Otherwise, the MP5515
waits until the voltage drops below the
reference before turning on the LS-FET. In
boost mode, the high-side MOSFET (HS-FET)
does not turn on, and the inductor current
conducts through the body diode of the HS-FET.
The boost-current limit is programmed by the
ICH resistor. The programmed boost-switching
current limit can be estimated with Equation (1):
1.0
10)(
)(
88
)( 7



HL
V
kR
AI IN
ICH
CH
(1)
Where RICH is the resistor connected to ICH,
and L is the boost inductor.
The boost switching current limit is programmed
by the ICH resistor (0.5A to 2A recommended
for normal application). By floating ICH, the
boost switching peak current is set at 2A by
default with ICH bits = 11 (for typical 12V input
and 10µH inductor application conditions).

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Refer to the ICH bits register description on
page 31 for other boost peak settings with ICH
floating.
The MP5515 applies an over-voltage protection
(OVP) function for VSTRG. If the feedback
voltage of VSTRG on FBS is over 1.1 x VFBS-REF,
the MP5515 shuts down the LS-FET of the
boost converter until VSTRG drops to the
regulating voltage. It is not necessary to add an
external power to STRG with a voltage higher
than the VSTRG regulation voltage.
Power-Down Release
After the first start-up period and the boost
starts switching, the MP5515 registers and
enables the release function. Once the input
power drops and DET drops to 0.99 x VDET-REF,
the storage boost converter stops charging and
works in buck-release mode. At the same time,
the ISOFET shuts down to prevent a negative
current from VB to VIN.
In buck mode, the MP5515 transfers energy
from the high-voltage storage capacitor to the
low-voltage bus capacitor. The regulated bus
voltage is determined by VFBB-REF and the
resistor divider from VB to FBB.
Figure 4 shows the detailed system shutdown
process. Buck mode has a max current limit
function to limit the release current. In each
buck mode switching cycle, the high-side switch
does not turn on until the inductor current drops
to a 6.5A valley current, typically.
MP5515
VIN
VB
Back up cap can supply VB
Back up_regulation
VB_UVLO
Back up
PFI
Figure 4: VIN Shutdown Sequence
Input Recovery Start-Up
If the input power fails and is restored, the
MP5515 remains in buck release mode. When
STRG is discharged and VB drops to
VB_UVLO, the MP5515 restarts from the
recovered VIN power, which is a new input
power start-up cycle with TPOR delay.
Input Current Limit
The input current limit controls the input inrush
current of the ISOFET carefully to prevent an
inrush current from VIN to VB. The internal
DVDT bits or external DVDT cap can set the
soft-start time. In addition to the soft-start
process, ILIM can limit the steady-state current
by connecting a resistor between ILIM and
AGND to set the current limit. The current limit
can be estimated with Equation (2):
08.0
)(
04.70 

kR I
ILIM
LIM
(2)
Where RILIM is the current-limit setting resistor
from ILIM to AGND.
The voltage on ILIM can also monitor and
indicate the current in the ISOFET. The
relationship between the input current and ILIM
voltage can be estimated with Equation (3):
08.0
)( 26.64*

kR
V
I
ILIM
ILIM
IN
(3)
Where VILIM is the ILIM voltage. VILIM can be
read through an ADC converter.
The voltage on ILIM is lower than 1.09V in
normal applications. If a voltage greater than
1.5V is applied on ILIM externally, the ISOFET
is shut down, and the MP5515 enters a buck-up
process.
When the VB load is close to the ILIM threshold,
during every boost refresh cycle, the input
current may easily trigger the current limit as
well as the system interrupt. To avoid
continuously triggering ILIM interrupt in this
condition, during every boost-up refresh cycle,
the input over current-interrupt is masked
automatically. The mask time depends on the
boost-up switching time.
Once the input over-current threshold is
triggered and FBB drops to VFBB-REF, the backup
buck converter starts working to maintain VB.
Once FBB is charged back to 105% of VFBB-REF,
the buck is disabled again in this condition.
During the boost refresh cycle, the buck
converter is not enabled, even if the over-
current threshold is triggered.

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Power-On Reset Delay and VB Rising
Control
TPOR controls the power-on reset function for
hot swapping. By floating TPOR, the TPOR
time is about 1.5ms by default. If an external
capacitor is connected to TPOR, an internal
1μA current charges the capacitor and
determines the TPOR time (charge TOPR cap
from 0V to 1V). The power-reset-delay time can
be estimated with Equation (4):
AVC
TTPOR
D

11
(4)
After the TPOR time, one capacitor across
DVDT programs the VB soft-start (SS) time.
During the SS period, the relationship between
VB and DVDT can be estimated with Equation
(5):
DVDT
VVB 13
(5)
Where VDVDT is the DVDT capacitor voltage
charged by a 3μA current. The VDVDT charge is
saturated to about 1.23V.
The VB soft-start time from 0V to VIN can be
estimated with Equation (6):
A313



DVDT
RCVB
T
(6)
By floating DVDT, the VB rising time can be
programmed by the internal DVDT register bits.
By default, the DVDT bit is set to 00, and the
VB slew rate is about 7.5V/ms. VB from 0V to
12V is 1.6ms by default, typically, if DVDT is
floating. Refer to the DVDT register description
on page 33 for other DVDT bit settings.
Reverse-Current Protection (RCP)
The VIN to VB MOSFET turns on when the
input voltage exceeds the VIN UVLO threshold
and VIN becomes greater than VB + 0.2V. This
MOSFET turns off when the DET voltage falls,
causing the MP5515 to enter buck-release
mode and does not turn on again until buck
mode finishes.
The ISOFET circuit applies reverse-current
protection (RCP) when energy is released from
the storage capacitors to VB. Typically, a
250mA reverse current from VB to VIN shuts
down the ISOFET.
Start-Up Sequence
After the IC is enabled, MP5515 starts to work
with the TPOR reset time and DVDT soft-start
time. During the VB rising time, an internal
charge pump charges the CST capacitor. This
provides a driver source for the hot-swap
MOSFET. Too short of a DVDT time may
trigger the input current-limit threshold. Too
large of a CST capacitor may affect the charge-
pump slew rate. A 10nF CST capacitor is
recommended. During the DVDT soft start, the
VB capacitor is charged, and the STRG
capacitor is not charged.
Once VB is charged, the DVDT voltage charges
to about 1.23V and is held at this saturated
voltage. If PFI is high and DVDT saturates, the
charge function is enabled and the storage
capacitor charges to the target voltage.
Backup Capacitance Test
The MP5515 features a back-up capacitor test
by discharging the backup capacitor through
one external resistor from STRG to RTEST.
Figure 5 shows the discharge block. The
MOSFET is about 4.5Ω, and the peak
discharge current must be limited below 500mA
by an external resistor, even it is discharged in
a short time.
STRG
RTEST
Backup Cap
GND
M1
Figure 5: Backup Capacitance Test Circuit
When the Start Cap Test register bit is set, the
MP5515 disables the boost charge switching,
and RTEST is connected to GND through the
internal MOSFET (M1) for energy discharging.
The MP5515 enables the VSTRG ADC
conversion when FBS drops to the VFBS-REF
threshold (SOC can read the STRG voltage

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through the I2C). Simultaneously, an internal
counter is enabled to measure the discharge
time. The counter continues until the cap
voltage drops below the PGS threshold voltage.
When VSTRG drops to the PGS threshold, the
ADC reads VSTRG again, and the Cap Test Done
register is set to indicate that cap test is
complete. Cap Test Done produces one
interrupt to inform the SOC that the test has
been completed. The SOC can read the backup
voltage and the counter timer registers. With
the initial voltage and end voltage reading, the
discharge time can be determined as
acceptable or not.
At the first ADC conversion, the MP5515 reads
VSTRG and stores this in the register ADC
Backup Voltage Data2. At the end of the
capacitor discharge ADC records the end
voltage in the register ’ADC Backup Voltage
Data1. The counter result is stored in the
register Cap Test Timer.
After the cap test is done, the Cap Test Start bit
is reset automatically, and the recharge function
is enabled automatically. Figure 6 shows the
work flow of performing the capacitance test.
SOC capacitance test function follows the
following operations:
1. Write register 04h bit[2] and bit[6] to code 1
(mask PGS Not Ok and ADC Done
interrupt).
2. Write register 06h to code 00h or another
value (set PGS Threshold at 80% or
another ratio of regulation).
3. If VIN is lower than 3.8V, write register 1Bh
bit[1] to code 1. This turns on the internal
VSTRG to the VCC LDO. If VIN is higher than
3.8V, ignore this step.
4. Write register 01h bit[3] to code 1 (request
Start Cap Test).
The MP5515 disables the VSTRG charge
function automatically after VSTRG is charged
higher than the FBS-set voltage. Register
01h bit[0] does not change.
The MP5515 starts discharging the STRG
cap through an external resistor after VSTRG
is fully charged.
The MP5515 starts the ADC only when VFBS
drops to the VREF-FBS threshold. ADC reads
VSTRG and stores data in ADC Backup
Voltage Data2.
The internal timer starts when VFBS drops to
the VREF-FBS threshold.
5. Wait for the interrupt from the MP5515
(afterward, if register 02h bit[7] is 1, the cap
test is complete).
When VSTRG discharges to the PGS
threshold, the discharge stops, and the
timer value is written to register Cap Test
Timer.
When PGS Threshold falling is triggered,
the MP5515 starts ADC a second time and
stores data in ADC Backup Voltage Data1.
After ADC conversion, the MP5515 sets the
Cap Test Done interrupt.
The MP5515 resets register 01h bit[3] to
code 0 automatically to clear Cap Test
Start.
The MP5515 re-enables the boost charge
function automatically.
6. Read registers 12h bit[7:0], 13h bit[1:0] and
store as VFINAL, total 10 bits (12h is the high
byte, 13h is the low byte).
Read registers 14h bit[7:0], 15h bit[1:0] and
store as VINITIAL, total 10 bits (14h is the high
byte, 15h is the low byte)
Read registers 16h bit[7:0], 17h bit[7:0] and
store as Time, total 16 bits (16h is the low
byte, 17h is the high byte).
7. Write register 02h bit[7] to code 1 to reset
the cap test interrupt event. Write both
register 04h bit[2] and bit[6] to code 1 to re-
enable PGS Not OK and ADC Done
interrupt. Write register 1Bh bit[1] to code 0
if it was set to 1 in step 3.
8. Calculate ADC results with Equation (7):
ln( )
STRG INITIAL DISCH LDO
DISCH FINAL DISCH LDO
Time
CV R I
RV R I


(7)
Where VINITIAL is VSTRG before the discharge
timer starts stored in ADC Backup Voltage
Data2 (in V), VFINAL is VSTRG after discharge
completes and stored in ADC Backup Voltage