N.A.T. NAT-FMC-SDR4 Product manual

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
N.A.T. Gesellschaft für Netzwerk- und Automatisierungs-Technologie mbH
Konrad-Zuse-Platz 9 | 53227 Bonn, Germany | Phone: [phone] - 0
[email protected] | www.nateurope.com
NAT-FMC-SDR4
FMC MEZZANINE BOARD
DESIGNED BY N.A.T. GMBH
TECHNICAL REFERENCE MANUAL V1.3
HW REVISION 1.3

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
PREFACE - 2 -
TABLE OF CONTENTS
1. PREFACE ...................................................................................................5
1.1. Disclaimer ......................................................................................................... 5
1.2. About This Document ..................................................................................... 6
2. INTRODUCTION ......................................................................................7
2.1. Wireless Applications ...................................................................................... 7
2.2. Main Features................................................................................................... 8
3. QUICK START...........................................................................................9
4. FUNCTIONAL DESCRIPTION ................................................................10
4.1. RF-Transceiver................................................................................................ 11
4.2. Clocking (NAT-FMC-SDR4-T only)...............................................................11
5. HARDWARE ...........................................................................................12
5.1. Front Panel and LEDs.....................................................................................12
5.2. Component-, Connector-, and Switch-Location ........................................13
5.2.1. J1/J2: MULTI-COAX CONNECTORS......................................................... 15
5.2.2. J3: FMC CONNECTOR (NAT-FMC-SDR4-M) ............................................. 16
5.2.3. J3: FMC CONNECTOR (NAT-FMC-SDR4-T) .............................................. 19
5.2.4. J4: GPIO CONNECTOR ..................................................................... 22
5.2.5. J5: FMC CONNECTOR (NAT-FMC-SDR4-M ONLY)....................................... 23
6. SPECIFICATIONS AND COMPLIANCES ...............................................26
6.1. Internal Reference Documentation .............................................................26
6.2. External Reference Documentation.............................................................26
6.3. Standards Compliance...................................................................................26
6.4. Compliance to RoHS Directive .....................................................................26
6.5. Compliance to WEEE Directive .....................................................................27
6.6. Compliance to CE Directive........................................................................... 27
6.7. Compliance to REACH ...................................................................................27

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
PREFACE - 3 -
6.8. Abbreviation List............................................................................................28
7. DOCUMENT’S HISTORY........................................................................29

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
PREFACE - 4 -
LIST OF TABLES
Table 1 –Technical Data ............................................................................... 8
Table 2 –Key Data RF-Transceivers................................................................. 11
Table 3 –J1/J2: Multi-Coax Connectors –Pin Assignment ....................................... 15
Table 4 –J3: FMC Connector NAT-FMC-SDR4-M ................................................. 16
Table 5 –J3: FMC Connector NAT-FMC-SDR4-T .................................................. 19
Table 6 –J4: GPIO Connector –Pin Assignment................................................... 22
Table 7 –J5: FMC Connector (NAT-FMC-SDR4-M only).......................................... 23
Table 8 –Abbreviation List........................................................................... 28
Table 9 –Document’s History ....................................................................... 29
LIST OF FIGURES
Figure 1 –Block Diagram ............................................................................ 10
Figure 2 –Front Panel NAT-AMC-ZYNQUP-SDR8 ................................................ 12
Figure 3 –NAT-FMC-SDR4-T Location Diagram –Top ........................................... 13
Figure 4 –NAT-FMC-SDR4-T Location Diagram –Bottom....................................... 13
Figure 5 –NAT-FMC-SDR4-M Location Diagram –Top .......................................... 14
Figure 6 –NAT-FMC-SDR4-M Location Diagram –Bottom...................................... 14
Figure 7 –J1/J2: Multi-Coax Connectors ........................................................... 15
Figure 8 –J4: GPIO Connector....................................................................... 22

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
PREFACE - 5 -
1. PREFACE
1.1. Disclaimer
The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.), represents
the current status of the product´s development. The documentation is updated on a regular
basis. Any changes which might ensue, including those necessitated by updated specifications,
are considered in the latest version of this documentation. N.A.T. is under no obligation to
notify any person, organization, or institution of such changes or to make these changes public
in any other way.
We must caution you, that this publication could include technical inaccuracies or typographi-
cal errors.
N.A.T. offers no warranty, either expressed or implied, for the contents of this documentation
or for the product described therein, including but not limited to the warranties of merchant-
ability or the fitness of the product for any specific purpose.
In no event will N.A.T. be liable for any loss of data or for errors in data utilization or processing
resulting from the use of this product or the documentation. In particular, N.A.T. will not be
responsible for any direct or indirect damages (including lost profits, lost savings, delays or
interruptions in the flow of business activities, including but not limited to, special, incidental,
consequential, or other similar damages) arising out of the use of or inability to use this
product or the associated documentation, even if N.A.T. or any authorized N.A.T.
representative has been advised of the possibility of such damages.
All registered names, trademarks etc. are property of their respective holders. The use of
registered names, trademarks, etc. in this publication does not imply, even in the absence of a
specific statement, that such names are exempt from the relevant protective laws and
regulations (patent laws, trade mark laws, etc.) and therefore free for general use. In no case
does N.A.T. guarantee that the information given in this documentation is free of such third-
party rights.
Neither this documentation nor any part thereof may be copied, translated, or reduced to any
electronic medium or machine form without the prior written consent from N.A.T. GmbH.
This product (and the associated documentation) is governed by the N.A.T. General Conditions
and Terms of Delivery and Payment.
Note:
The release of the Hardware Manual is related to a certain HW board revision given in
the document title. For HW revisions earlier than the one given in the document title
please contact N.A.T. for the corresponding older Hardware Manual release.

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
PREFACE - 6 -
1.2. About This Document
This document is intended to give an overview on the NAT-FMC-SDR4’s functional
capabilities.
Preface
General information about this document
Introduction
Abstract on the NAT-FMC-SDR4’s main functionality and application field
Quick Start
Important information and mandatory requirements to be considered before operating the
NAT-FMC-SDR4 for the first time
Functional Description
Detailed information on the individual devices and the NAT-FMC-SDR4’s main features
Hardware
Description of the connectors, switches, and LEDs located on the NAT-FMC-SDR4
Specifications and Compliances
Detailed list of specifications, abbreviations, and datasheets of components referred to in this
document and standards, the NAT-FMC-SDR4 complies to
Document’s History
Revision record
Note:
It is assumed, that the NAT-FMC-SDR4 is handled by qualified personnel only!

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
INTRODUCTION - 7 -
2. INTRODUCTION
The NAT-FMC-SDR4 is a mezzanine board in FMC form factor with integrated hardware
elements, which make it the ideal platform for sophisticated wireless, machine vision, and SDR
applications.
One or two of these mezzanines can be mounted on a NAT-AMC-ZYNQUP-FMC carrier
board. This combination –named NAT-AMC-ZYNQUP-SDR4 (one FMC, standard) or NAT-
AMC-ZYNQUP-SDR8 (two FMCs, option) –offers the flexibility to address a broad range of
applications.
Important: For 4RX/TX interfaces, one NAT-FMC-SDR4-T (Top) mezzanine board needs to
be installed. For 8RX/TX interfaces, one NAT-FMC-SDR4-M (Mid) and one NAT-FMC-SDR4-
T(Top) mezzanines are mandatory.
Both FMCs are built up similar, differences are explained in the relevant sections.
2.1. Wireless Applications
Due to its powerful FPGA for baseband processing (using NAT-AMC-ZYNQUP-FMC as base
board) and the flexible RF-frontend on the FMCs, the NAT-AMC-ZYNQUP-SDR4/8 is ideal for
Software Defined Radio applications.
The on-board JESD204B clocking simplifies the integration of high-speed ADC/DAC FMCs.
Inputs for reference clock, sync, trigger, and 1pps signals enable multi-board baseband and
RF-phase synchronization for massive MIMO and phased antenna arrays.

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
INTRODUCTION - 8 -
2.2. Main Features
Table 1 –Technical Data
Form Factor
NAT-FMC-SDR4-M
NAT-FMC-SDR4-T
•FMC Mezzanine Board
•Width: 69.0mm, depth: 81.1mm
•In combination with NAT-AMC-ZYNQUP-FMC: Single-wide, Full-size AMC
•Width: 73.5mm, depth: 180.6mm
Processing Resources
•On carrier board NAT-AMC-ZYNQUP-FMC
RF-Interface
•2x Analog Devices ADRV9009 RF Transceiver
Clock
•-
•Analog Devices HMC7044 with
JESD204B
•19.2MHz oscillator
•122.88MHz oscillator
FMC Slot(s)
•2 FMC slots (male/female) to
connect to carrier board / Top-FMC
•1 FMC slot (male) to connect to
carrier board or Mid-FMC
Backplane Interconnect
•Via carrier board NAT-AMC-ZYNQUP-FMC
Front Panel (including NAT-AMC-ZYNQUP-FMC carrier board)
•4x Tx, 4x Rx, 4x ORx
•GPIO RF-Control
•2x 7 GPIO 1V8 to RF Transceiver
•2x 3 GPIO 3V3 to RF Transceiver
•6x GPIO 1V8 to FPGA
•CLK OUT
•CLK IN (JESD204b)
•SYNC for JESD204b
•PPS IN
•Trigger IN/OUT to FPGA
•SD card holder
•UART-USB serial console for ARM core and MMC
•AMC standard LEDs and hot swap handle
•Application LEDs
Compliance
•AMC.0 R2.0, AMC.1, AMC.2, AMC.3, AMC.4, IMPI V1.5, HPM.1
•RoHS
•VITA 57.1
Environmental
Operating
Environment
•0 to +55 degrees Celsius (extended temperature range on request)
•Humidity: 5% to 95% (non-condensing)
•Temperature of the ADRV9009 RF Transceivers may not exceed 110°C!
Storage
Environment
•-40 to +100 degrees Celsius
•Humidity: 5% to 95% (non-condensing)

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
QUICK START - 9 -
3. QUICK START
For bring-up information, please refer to the NAT-AMC-ZYNQUP-FMC Technical Reference
Manual (see chapter 6.1 Internal Reference Documentation for details).

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
FUNCTIONAL DESCRIPTION - 10 -
4. FUNCTIONAL DESCRIPTION
The NAT-FMC-SDR4 can be divided into a number of functional blocks, which are described
in the following paragraphs.
As the NAT-FMC-SDR4 is intended to be operated with the NAT-AMC-ZYNQUP-FMC carrier
only, the following figure gives an overview on the functional blocks of the whole combination.
Figure 1 –Block Diagram
SPI+IO
SPI+IO
14
Tx
Tx
ORx
ORx
Rx
Rx
Tx
Tx
ORx
ORx
Rx
Rx
GPIO
RF-CTRL
NAT-FMC-SDR4-T
x2/x4 SerDes*
RF-
Transceiver
ADRV9009
x2/x4 SerDes*
FMC Connector
VITA 57.1
RF-
Transceiver
ADRV9009
Clock + Sync
HMC7044
JESD204b
Clocking
Clk +
Sync
Clk +
Sync
19.2
MHz
Osc
122.88
MHz
VXCO
14
6FPGA GPIO
GPIO
GPIO
SPI+IO
SPI+IO
14
Tx
Tx
ORx
ORx
Rx
Rx
Tx
Tx
ORx
ORx
Rx
Rx
GPIO
RF-CTRL
NAT-FMC-SDR4-M
x2 SerDes
RF-
Transceiver
ADRV9009
x2 SerDes
FMC Connector
VITA 57.1
RF-
Transceiver
ADRV9009
Clock + Sync
14
6FPGA GPIO
GPIO
GPIO
Clock + Sync
x10 SerDes
JTAG
IPMI
TCLKA-D MMC
I²C
Si5374
Clocking
REF_CLK IN
SYS_REF IN
GPU
SD
Card
JESD204B
CLK/SYNC
SPI
GPIO
User
CLK
USB to
JTAG and
UART
TRIG IN/OUT
AMC Ports 0/1 GbE
AMC Ports 2/3, 12-20 Custom
AMC Ports 4-11
PCIe / Ethernet / Custom
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
CLK OUT
TCLKA-D
1PPS
FPGA Clocks
FPGA
XILINX
Zynq UltraScale+
FFVF1517
ZU7EG
ZU11EG
4x A53
ARM CPU
(Zynq)
2x
R5
2x
R5
CPU
QSPI
FLASH
4
64
8GB
DDR4
64
8GB
DDR4
TRIG IN/OUT
Optional Memory
Module,
Memory Type tbd
USB
FMC Connector
to Mezzanine
JTAG
UART
NAT-AMC-ZYNQUP-SDR only
USB
StratumIII
12.8MHz RefCLK
CLK
Switch
*Note: The number of available SerDes connections per RF-Transceiver varies with the number
of installed FMCs. Equipped with two FMCs (NAT-AMC-ZYNQUP-SDR8 option), each FMC
owns four SerDes connections, two for every RF-Transceiver. If only one FMC is mounted
(NAT-AMC-ZYNQUP-SDR4 option), a total of eight SerDes connections is available on one
FMC, which means four for every RF-Transceiver.

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
FUNCTIONAL DESCRIPTION - 11 -
4.1. RF-Transceiver
Both variants of the NAT-FMC-SDR4 feature two Analog Devices ADRV9009 transceiver units.
Every transceiver offers two transmitter-, two receiver-, and two observation receiver-
interfaces.
Table 2 –Key Data RF-Transceivers
Parameter
Value
Maximum receiver bandwidth
200 MHz
Maximum tuneable transmitter synthesis
bandwidth
450 MHz
Maximum observation receiver bandwidth
450 MHz
Multichip phase synchronization for RF- and
baseband signals
Supported
Multiboard synchronization
Supported
JESD204B IQ sample data interface to FPGA
Supported
Tuning range (center frequency)
75 MHz to 6000 MHz
RX gain range
30dB in 0.5dB steps
Rx Noise Figure
2dB @ 800 MHz
3dB @ 2.4 GHz
3.8 dBm @ 5.5 GHz
Maximum output power
9 dBm @ 75 MHz < f ≤ 600 MHz
7 dBm @ 600 MHz < f ≤ 4000 MHz
6 dBm @ 4000 MHz < f ≤ 4800 MHz
4.5 dBm @ 4800 MHz < f ≤ 6000 MHz
Tx Error Vector Magnitude (EVM)
0.5% @ 75 MHz LO
0.7% @ 1900 MHz LO
0.7% @ 3800 MHz LO
1.1% @ 5900 MHz LO
3rd order output intermodulation OIP3
23 dBm @ 800 MHz
19 dBm @ 2.4 GHz
17 dBm @ 5.5 GHz
Important: The temperature of the ADRV9009 RF transceiver may not exceed 110°C!
4.2. Clocking (NAT-FMC-SDR4-T only)
The NAT-FMC-SDR4-T features an Analog Devices HMC7044 device, which offers JESD204b
interfaces.
A 19.2MHz oscillator and a 122.88MHz VXCO are connected to the clock device.

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 12 -
5. HARDWARE
5.1. Front Panel and LEDs
The front plate appearance and the labelling vary depending on the number and variant(s) of
installed FMCs.
The figure below shows the full-size version, the NAT-AMC-ZYNQUP-SDR8, which is fully
equipped with two FMCs.
Figure 2 –Front Panel NAT-AMC-ZYNQUP-SDR8
NAT-AMC-ZYNQUP-SDR8
1
HS
123
G
P
I
O2
S/T
Stat
Flt
D
C
TX1
ORX1
RX1
TX2
ORX2
RX2
DBG
B
ATX1
ORX1
RX1
TX2
ORX2
RX2
The LEDs, debug interface, and SD-Card holder are accessible via the NAT-AMC-ZYNQUP-
FMC. Please check the carrier board’s Technical Reference Manual for details (refer to 6.1
Internal Reference Documentation).

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 13 -
5.2. Component-, Connector-, and Switch-Location
Figure 3 –NAT-FMC-SDR4-T Location Diagram –Top
RF-
Trans-
ceiver
J3
J4
J2
J1 RF-
Trans-
ceiver
Power
Supply
Transformation
and De-Coupling
Figure 4 –NAT-FMC-SDR4-T Location Diagram –Bottom
Clock and
Oscillator
Power
Supply

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 14 -
Figure 5 –NAT-FMC-SDR4-M Location Diagram –Top
RF-
Trans-
ceiver
J3
J4
J2
J1 RF-
Trans-
ceiver
Power
Supply
Transformation
and De-Coupling
Figure 6 –NAT-FMC-SDR4-M Location Diagram –Bottom
Power Supply
J5
Connectors on top side: drawings imply the board is orientated with the front panel interfaces
to the left side
Connectors on bottom side: drawings imply the board is orientated with the front panel
interfaces to the right side
Please refer to the following tables to look up the connector pin assignment of the NAT-FMC-
SDR4.

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 15 -
5.2.1. J1/J2: Multi-Coax Connectors
Connectors J1 and J2 offer access to the RF-transceiver interfaces towards the front panel with
the signals routed via the pins and ground connected to the shield.
Note: An associated cable set is available as order option.
Figure 7 –J1/J2: Multi-Coax Connectors
B ACDEF
Table 3 –J1/J2: Multi-Coax Connectors –Pin Assignment
Pin #
Signal
Signal
Pin #
J1A
TX2_OUT_A
TX2_OUT_B
J2A
J1B
ORX2_IN_A
ORX2_IN_B
J2B
J1C
RX2_IN_A
RX2_IN_B
J2C
J1D
RX1_IN_A
RX1_IN_B
J2D
J1E
ORX1_IN_A
ORX1_IN_B
J2E
J1F
TX1_OUT_A
TX1_OUT_B
J2F

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 16 -
5.2.2. J3: FMC Connector (NAT-FMC-SDR4-M)
Connector J3 connects the FMC to the carrier board.
Table 4 –J3: FMC Connector NAT-FMC-SDR4-M
A
B
C
D
E
F
G
H
J
K
1
GND
GND
GND
FMC_PWR_E
N
GND
nc
GND
nc
GND
nc
2
DP1_M2C_P
GND
DP0_C2M_P
GND
nc
GND
CLK1_M2C_P
GND
CLK3_BIDIR_
P
GND
3
DP1_M2C_N
GND
DP0_C2M_N
GND
nc
GND
CLK1_M2C_N
GND
CLK3_BIDIR_
N
GND
4
GND
DP9_M2C_P
GND
GBTCLK0_M2
C_P
GND
HA00_P_CC
GND
CLK0_M2C_P
GND
CLK2_BIDIR_
P
5
GND
DP9_M2C_N
GND
GBTCLK0_M2
C_N
GND
HA00_N_CC
GND
CLK0_M2C_N
GND
CLK2_BIDIR_
N
6
SERDOUT0_A
_P
GND
DP0_M2C_P
GND
SYNCIN1_A_
P
GND
LA00_P_CC
GND
nc
GND
7
SERDOUT0_A
_N
GND
DP0_M2C_N
GND
SYNCIN1_A_
N
HA04_P
LA00_N_CC
LA02_P
nc
GP_INTERRU
PT_A
8
GND
DP8_M2C_P
GND
LA01_P_CC
GND
HA04_N
GND
LA02_N
GND
RX1_ENABLE
_A
9
GND
DP8_M2C_N
GND
LA01_N_CC
SYNCIN0_A_
P
GND
LA03_P
GND
nc
GND
10
SERDOUT1_A
_P
GND
LA06_P
GND
SYNCIN0_A_
N
HA08_P
LA03_N
LA04_P
nc
RX2_ENABLE
_A
11
SERDOUT1_A
_N
GND
LA06_N
LA05_P
GND
HA08_N
GND
LA04_N
GND
TX1_ENABLE_
A

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 17 -
A
B
C
D
E
F
G
H
J
K
12
GND
SERDOUT1_B
_P
GND
LA05_N
SYNCOUT0_
A_P
GND
LA08_P
GND
nc
GND
13
GND
SERDOUT1_B
_N
GND
GND
SYNCOUT0_
A_N
SPI_SDIO_A
LA08_N
LA07_P
nc
nc
14
DP4_M2C_P
GND
LA010_P
LA09_P
GND
SPI_SDO_A
GND
LA07_N
GND
nc
15
DP4_M2C_N
GND
LA010_N
LA09_N
SYNCOUT1_
A_P
GND
LA12_P
GND
nc
GND
16
GND
SERDOUT0_B
_P
GND
GND
SYNCOUT1_
A_N
SPI_CS_A
LA12_N
LA11_P
nc
nc
17
GND
SERDOUT0_B
_N
GND
LA13_P
GND
SPI_SCLK_A
GND
LA11_N
GND
nc
18
DP5_M2C_P
GND
LA14_P
LA13_N
SYNCOUT0_B
_P
GND
LA16_P
GND
SYNCOUT1_B
_P
GND
19
DP5_M2C_N
GND
LA14_N
GND
SYNCOUT0_B
_N
SPI_CS_B
LA16_N
LA15_P
SYNCOUT1_B
_N
GPIO_11_1V8
_A
20
GND
GBTCLK1_M2
C_P
GND
LA17_P_CC
GND
SPI_SCLK_B
GND
LA15_N
GND
GPIO_13_1V8
_A
21
GND
GBTCLK1_M2
C_N
GND
LA17_N_CC
SYNCIN0_B_P
GND
LA20_P
GND
SYNCIN1_B_P
GND
22
DP1_C2M_P
GND
LA18_P_CC
GND
SYNCIN0_B_
N
nc
LA20_N
LA19_P
SYNCIN1_B_
N
nc
23
DP1_C2M_N
GND
LA18_N_CC
LA23_P
GND
nc
GND
LA19_N
GND
nc
24
GND
DP9_C2M_P
GND
LA23_N
GPIO_14_1V8
_A
GND
LA22_P
GND
FPGA_GPIO_
2_1V8_A
GND
25
GND
DP9_C2M_N
GND
GND
GPIO_15_1V8
_A
nc
LA22_N
LA21_P
FPGA_GPIO_
3_1V8_A
nc
26
SERDIN0_A_P
GND
LA27_P
LA26_P
GND
nc
GND
LA21_N
GND
nc
27
SERDIN0_A_
N
GND
LA27_N
LA26_N
RESET_N_A
GND
LA25_P
GND
FPGA_GPIO_
4_1V8_A
GND
28
GND
DP8_C2M_P
GND
GND
TX2_ENABLE_
GPIO_10_1V8
LA25_N
LA24_P
FPGA_GPIO_
nc

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 18 -
A
B
C
D
E
F
G
H
J
K
A
_B
0_1V8_A
29
GND
DP8_C2M_N
GND
nc
GND
GPIO_12_1V8
_B
GND
LA24_N
GND
nc
30
SERDIN1_A_P
GND
FMC_SCL
nc
GPIO_8_1V8_
A
GND
LA29_P
GND
GP_INTERRU
PT_B
GND
31
SERDIN1_A_
N
GND
FMC_SDA
nc
GPIO_9_1V8_
A
GPIO_9_1V8_
B
LA29_N
LA28_P
RESET_N_B
GPIO_15_1V8
_A
32
GND
SERDIN1_B_P
GND
3P3VAUX
GND
GPIO_10_1V8
_B
GND
LA28_N
GND
GPIO_14_1V8
_A
33
GND
SERDIN1_B_
N
GND
nc
FPGA_GPIO_
1_1V8_A
GND
LA31_P
GND
RX1_ENABLE
_B
GND
34
DP4_C2M_P
GND
I2C_DEV_A0
nc
FPGA_GPIO_
5_1V8_A
SPI_SDIO_B
LA31_N
LA30_P
RX2_ENABLE
_B
GPIO_12_1V8
_B
35
DP4_C2M_N
GND
FMC_12POV
I2C_DEV_A1
GND
SPI_SDO_B
GND
LA30_N
GND
GPIO_11_1V8
_B
36
GND
SERDIN0_B_P
GND
FMC_3P3V
nc
GND
LA33_P
GND
TX1_ENABLE_
B
GND
37
GND
SERDIN0_B_
N
FMC_12POV
GND
nc
HB20_P
LA33_N
LA32_P
TX2_ENABLE_
B
GPIO_13_1V8
_B
38
DP5_C2M_P
GND
GND
FMC_3P3V
GND
HB20_N
GND
LA32_N
GND
GPIO_8_1V8_
B
39
DP5_C2M_N
GND
FMC_3P3V
GND
FMC_VADJ
GND
FMC_VADJ
GND
VIO_B_M2C
GND
40
GND
nc
GND
FMC_3P3V
GND
FMC_VADJ
GND
FMC_VADJ
GND
VIO_B_M2C

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 19 -
5.2.3. J3: FMC Connector (NAT-FMC-SDR4-T)
Connector J3 connects the FMC to the carrier board or the NAT-FMC-SDR4-M mezzanine.
Table 5 –J3: FMC Connector NAT-FMC-SDR4-T
A
B
C
D
E
F
G
H
J
K
1
GND
GND
GND
FMC_PWR_E
N
GND
nc
GND
nc
GND
nc
2
SERDOUT1_A
_P
GND
SERDIN0_A_P
GND
nc
GND
nc
GND
nc
GND
3
SERDOUT1_A
_N
GND
SERDIN0_A_
N
GND
nc
GND
nc
GND
nc
GND
4
GND
nc
GND
JESD_DEVCL
K_E_P
GND
CLK_HMC704
4_FPGA_P
GND
HMC7044_O
UT10_P
GND
CLK_HMC704
4_SYS_PLL_P
5
GND
nc
GND
JESD_DEVCL
K_E_N
GND
CLK_HMC704
4_FPGA_N
GND
HMC7044_O
UT10_N
GND
CLK_HMC704
4_SYS_PLL_N
6
SERDOUT2_A
_P
GND
SERDOUT0_A
_P
GND
nc
GND
GPIO14_1V8_
A
GND
nc
GND
7
SERDOUT2_A
_N
GND
SERDOUT0_A
_N
GND
nc
GPIO1_HMC
7044
GPIO15_1V8_
A
SYNCOUT0_
A_P
nc
nc
8
GND
nc
GND
JESD_SYSREF
_F_P
GND
GPIO3_HMC
7044
GND
SYNCOUT0_
A_N
GND
nc
9
GND
nc
GND
JESD_SYSREF
_F_N
nc
GND
GP_INTERRU
PT_A
GND
nc
GND
10
SERDOUT3_A
_P
GND
SPI_SDO_A
GND
nc
GPIO2_HMC
7044
RX1_ENABLE
_A
SYNCOUT1_
A_P
nc
nc
11
SERDOUT3_A
_N
GND
SPI_SDIO_A
GPIO8_1V8_
A
GND
nc
GND
SYNCOUT1_
A_N
GND
nc
12
GND
SERDOUT3_B
_P
GND
GPIO4_HMC
7044
nc
GND
RX2_ENABLE
_A
GND
JESD_SYSREF
_C_P
GND

NAT-FMC-SDR4
TECHNICAL REFERENCE MANUAL V1.3
HARDWARE - 20 -
A
B
C
D
E
F
G
H
J
K
13
GND
SERDOUT3_B
_N
GND
GND
nc
nc
TX1_ENABLE_
A
SYNCIN0_A_
P
JESD_SYSREF
_C_PN
JESD_DEVCL
K_D_P
14
SERDOUT0_B
_P
GND
SPI_SCLK_A
RESET_HMC7
044
GND
nc
GND
SYNCIN0_A_
N
GND
JESD_DEVCL
K_D_N
15
SERDOUT0_B
_N
GND
SPI_CS_A
SYNC_HMC7
044
nc
GND
TX2_ENABLE_
A
GND
JESD_DEVCL
K_C_P
GND
16
GND
SERDOUT2_B
_P
GND
GND
nc
nc
RESET_N_A
SYNCIN1_A_
P
JESD_DEVCL
K_C_N
JESD_SYSREF
_D_P
17
GND
SERDOUT2_B
_N
GND
GPIO_9_1V8_
A
GND
nc
GND
SYNCIN1_A_
N
GND
JESD_SYSREF
_D_N
18
SERDOUT1_B
_P
GND
SPI_CSn
GPIO_10_1V8
_A
nc
GND
GPIO_11_1V8
_A
GND
nc
GND
19
SERDOUT1_B
_N
GND
SPI_CLK
GND
nc
nc
GPIO_12_1V8
_A
LA15_P
nc
nc
20
GND
JESD_DEVCL
K_F_P
GND
JESD_SYSREF
_E_P
GND
nc
GND
LA15_N
GND
nc
21
GND
JESD_DEVCL
K_F_N
GND
JESD_SYSREF
_E_N
nc
GND
GPIO_12_1V8
_B
GND
nc
GND
22
SERDIN1_A_P
GND
GPIO_14_1V8
_A
GND
nc
nc
GPIO_11_1V8
_B
FPGA_GPIO_
2_1V8
nc
nc
23
SERDIN1_A_
N
GND
GPIO_15_1V8
_A
GPIO12_1V8_
B
GND
nc
GND
FPGA_GPIO_
3_1V8
GND
nc
24
GND
nc
GND
GPIO13_1V8_
B
nc
GND
GP_INTERRU
PT_B
GND
nc
GND
25
GND
nc
GND
GND
nc
nc
RESET_N_B
FPGA_GPIO_
4_1V8
nc
nc
26
SERDIN2_A_P
GND
SPI_SDO_B
TX1_ENABLE_
B
GND
nc
GND
FPGA_GPIO_
5_1V8
GND
nc
27
SERDIN2_A_
N
GND
SPI_SDIO_B
TX2_ENABLE_
B
nc
GND
RX1_ENABLE
_B
GND
nc
GND