N.A.T. NAT-MCH Product manual

NAT-MCH HUB-Module PCIe –Technical Reference Manual
NAT-MCH
TCA Telecom MCH Module
Technical Reference Manual V 1.2
HUB-Module PCIe HW Revision 2.3

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 2
The NAT-MCH HUB-Module PCIe has been designed by:
N.A.T. GmbH
Konrad-Zuse-Platz 9
53227 Bonn-Oberkassel
Phone: +49 / 228 / 965 864 –0
Fax: +49 / 228 / 965 864 –10
Internet: http://www.nateurope.com

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 3
Disclaimer
The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.),
represents the current status of the product’s development. The documentation is
updated on a regular basis. Any changes which might ensue, including those necessitated
by updated specifications, are considered in the latest version of this documentation.
N.A.T. is under no obligation to notify any person, organization, or institution of such
changes or to make these changes public in any other way.
We must caution you, that this publication could include technical inaccuracies or
typographical errors.
N.A.T. offers no warranty, either expressed or implied, for the contents of this
documentation or for the product described therein, including but not limited to the
warranties of merchantability or the fitness of the product for any specific purpose.
In no event will N.A.T. be liable for any loss of data or for errors in data utilization or
processing resulting from the use of this product or the documentation. In particular,
N.A.T. will not be responsible for any direct or indirect damages (including lost profits,
lost savings, delays or interruptions in the flow of business activities, including but not
limited to, special, incidental, consequential, or other similar damages) arising out of the
use of or inability to use this product or the associated documentation, even if N.A.T. or
any authorized N.A.T. representative has been advised of the possibility of such
damages.
The use of registered names, trademarks, etc. in this publication does not imply, even in
the absence of a specific statement, that such names are exempt from the relevant
protective laws and regulations (patent laws, trade mark laws, etc.) and therefore free
for general use. In no case does N.A.T. guarantee that the information given in this
documentation is free of such third-party rights.
Neither this documentation nor any part thereof may be copied, translated, or reduced to
any electronic medium or machine form without the prior written consent from N.A.T.
GmbH.
This product (and the associated documentation) is governed by the N.A.T. General
Conditions and Terms of Delivery and Payment.
Note:
The release of the Hardware Manual is related to a certain HW board revision
given in the document title. For HW revisions earlier than the one given in the
document title please contact N.A.T. for the corresponding older Hardware
Manual release.

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 4
Table of Contents
DISCLAIMER ....................................................................................................... 3
TABLE OF CONTENTS .......................................................................................... 4
LIST OF TABLES .................................................................................................. 5
LIST OF FIGURES................................................................................................ 5
CONVENTIONS.................................................................................................... 6
1INTRODUCTION ........................................................................................... 7
2OVERVIEW ................................................................................................... 8
2.1 MAJOR FEATURES......................................................................................... 8
2.2 BLOCK DIAGRAM ......................................................................................... 9
2.3 LOCATION DIAGRAM ....................................................................................10
3BOARD FEATURES ...................................................................................... 11
3.1 PCI EXPRESS SWITCH PLX PEX8748 ...............................................................11
3.2 MICROCONTROLLER .....................................................................................13
3.3 FPGA .....................................................................................................13
3.4 MULTIPLEXING UNITS ...................................................................................13
3.5 PCIE INTERFACES .......................................................................................13
3.6 INTERFACE TO NAT-MCH BASE-MODULE ..........................................................13
3.7 INTERFACE TO NAT-MCH CLK-MODULE ............................................................13
4HARDWARE ................................................................................................ 14
4.1 LEDS......................................................................................................14
4.2 CONNECTORS ............................................................................................15
4.2.1 CON1: AMC Connector to 3rd tongue ...................................................16
4.2.2 CON2: AMC Connector to 4th tongue ...................................................18
4.2.3 CON3: Connector to NAT-MCH CLK/BASE-Module .................................20
4.2.4 JP1: JTAG programming interface .......................................................20
4.2.5 J1: Connector to optional Root-Complex..............................................21
5PROGRAMMING NOTES .............................................................................. 22
5.1 SPI INTERFACE ..........................................................................................22
5.1.1 SPI-Interface –Default mode.............................................................22
5.1.2 SPI-Interface –Update mode .............................................................22
5.2 I²C INTERFACE ..........................................................................................22
5.3 REGISTER.................................................................................................22
5.3.1 Board Identifier Register ...................................................................22
5.3.2 PCB Revision Register .......................................................................23
5.3.3 Atmel Version ..................................................................................23
6BOARD SPECIFICATION ............................................................................. 24
7INSTALLATION .......................................................................................... 25
7.1 SAFETY NOTE ............................................................................................25

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 5
7.2 INSTALLATION PREREQUISITES AND REQUIREMENTS ...............................................25
7.2.1 Requirements ..................................................................................25
7.2.2 Power supply ...................................................................................25
7.2.3 Automatic Power Up..........................................................................25
7.3 STATEMENT ON ENVIRONMENTAL PROTECTION ......................................................26
7.3.1 Compliance to RoHS Directive ............................................................26
7.3.2 Compliance to WEEE Directive............................................................26
7.3.3 Compliance to CE Directive ................................................................27
7.3.4 Product Safety .................................................................................27
7.3.5 Compliance to REACH .......................................................................27
8KNOWN BUGS / RESTRICTIONS................................................................. 28
APPENDIX A: REFERENCE DOCUMENTATION .................................................... 29
APPENDIX B: DOCUMENT’S HISTORY ............................................................... 30
List of Tables
Table 1: List of used Abbreviations .......................................................................... 6
Table 2: PCIe Switch Lane to MCH Fabric Port Mapping .............................................11
Table 3: Switch Lanes to AMC port mapping for X4-Link on a standard MicroTCA-
Backplane .....................................................................................................12
Table 4: LED State –Link Status ............................................................................14
Table 5: CON1: AMC Connector to 3rd tongue –Pin Assignment..................................16
Table 6: CON2: AMC Connector to 4th tongue –Pin Assignment..................................18
Table 7: CON3: Connector to NAT-MCH CLK/BASE-Module –Pin Assignment ...............20
Table 8: J1: Connector to optional Root-Complex –Pin Assignment ............................21
Table 9: Board Identifier Register ...........................................................................22
Table 10: PCB Revision Register .............................................................................23
Table 11: Atmel Revision Register ..........................................................................23
Table 12: NAT-MCH HUB-Module PCIe Features........................................................24
List of Figures
Figure 1: Arrangement of different NAT-MCH Modules............................................. 7
Figure 2: Figure 2: NAT-MCH HUB-Module PCIe –Block Diagram.............................. 9
Figure 3: NAT-MCH HUB-Module PCIe –Location Diagram (top) ..............................10
Figure 4: NAT-MCH HUB-Module PCIe –Location Diagram (bottom).........................10
Figure 5: NAT-MCH HUB-Module PCIe –Connectors (top) .......................................15
Figure 6: NAT-MCH HUB-Module PCIe –Connectors (bottom) .................................15

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 6
Conventions
If not otherwise specified, addresses and memory maps are written in hexadecimal
notation, identified by 0x.
The following table gives a list of the abbreviations used in this document:
Table 1: List of used Abbreviations
Abbreviation
Description
AMC
Advanced Mezzanine Card
b
bit, binary
B
byte
ColdFire
MCF5470
CPU
Central Processing Unit
CU
Cooling Unit
DMA
Direct Memory Access
E1
2.048 Mbit G.703 Interface
FLASH
Programmable ROM
FRU
Field Replaceable Unit
J1
1,544 Mbit G.703 Interface (Japan)
K
kilo (factor 400 in hex, factor 1024 in decimal)
LIU
Line Interface Unit
M
mega (factor 10,0000 in hex, factor 1,048,576 in decimal)
MCH
µTCA Carrier Hub
MHz
1,000,000 Herz
µTCA
Micro Telecommunications Computing Architecture
PCIe
PCI Express
PCI
Peripheral Component Interconnect
PM
Power Manager
RAM
Random Access Memory
ROM
Read Only Memory
SDRAM
Synchronous Dynamic RAM
SSC
Spread Spectrum Clock
T1
1,544 Mbit G.703 Interface (USA)

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 7
1Introduction
The NAT-MCH consists of a BASE-Module, which can be expanded with additional
PCBs. The BASE-Module satisfies the basic requirements of the MicroTCA Specification
for a MicroTCA Carrier Hub. The main capabilities of the BASE-Module are:
management of up to 12 AMCs, two cooling units (CUs) and one or more
power modules (PMs)
Gigabit Ethernet Hub Function for Fabric A (up to 12 AMCs) and for the
Update Fabric A to a second (redundant) NAT-MCH
To meet also the optional requirements of the MicroTCA specification, a CLK-Module and
different HUB-Modules are available. With the CLK-Module the following functions can
be enabled:
generation and distribution of synchronized clock signals for up to 12 AMCs
Through the extension of the NAT-MCH with a HUB-Module, hub functions for fabric D
to G can be enabled. With the different versions the customers have the opportunity to
choose a HUB-Module that fits best to their applications. The versions differ in:
max. number of supported AMCs ( up to 6 / up to 12)
supported protocols:
oPCI Express
oSerial Rapid IO
o10Gigabit Ethernet
The features of the individual modules are described in more detail in the corresponding
Technical Reference Manuals.
A general arrangement of the different modules of a NAT-MCH is shown in the following
figure
Figure 1: Arrangement of different NAT-MCH Modules
LED Module
Basic Module CLK Module
Hub Module
This Technical Reference Manual describes the NAT-MCH HUB-Module PCIe. In
addition to the CLK-Module it can be mounted on the NAT-MCH BASE-Module. With
the NAT-MCH HUB-Module PCIe the 3rd tongue and 4th tongue of the NAT-MCH
connector to the MicroTCA backplane is installed.

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 8
2Overview
2.1 Major Features
PLX PEX8748 PCI Express switch
connection to AMC 1-6 (via 3rd tongue) and to AMC 7-12 (via 4th tongue)
non-blocking switching at full line rate
Quality of Service (QoS)
2 virtual cannels and 8 traffic classes per port supported
Configuration of one of all 12 AMC ports as transparent and non-
transparent upstream port each
Atmel ATmega1284 microcontroller
Configuration of PCIe switch
Support of Hot-Swap functionality
Lattice MachXO2 FPGA
Support of Hot-Plug functionality for each AMC-Slot
Two PI3PCIE3412 multiplexing units
Connection to AMC 12 (via 4th tongue)
Switching between AMC 12 and optional Root Complex (double-width NAT-
MCH BASE-Module only)
PCIe x1 and x4 switching function
Connection of fabrics D to G of up to 6 AMCs (NAT-MCH HUB-Module
PCIe x24)
Connection of fabrics D to G of up to 12 AMCs (NAT-MCH HUB-Module
PCIe x48)
Connection to optional Root Complex (double-width NAT-MCH BASE-
Module only)
Clustering support –up too six clusters can be operated individually, each having
its own Root Complex
PCIe compliant Spread Spectrum Clocking

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 9
2.2 Block Diagram
The following figure shows a block diagram of the NAT-MCH HUB-Module PCIe.
Figure 2: Figure 1: NAT-MCH HUB-Module PCIe –Block Diagram
backplane connector
tongue 4 (Harting Plug)
IPMI
NAT-MCH
HUB-Module PCIe
Gen III –HW v2.3
to AMC 7-11
x4 PCIe
Micro-
controller
Connector from
Base-/CLK-Module
PCI Express
SWITCH
PLX PEX8748
backplane connector
tongue 3 (Harting Plug)
Management-I²C
fabric D to G
x4 PCIe
to AMC 1-6
(Optional)
Root Complex
PCIe-Clock from
CLK-Mezzanine
fabric D to G
MUX
fabric D to G
x4 PCIe
to AMC 12
Temp
Sensor
x4 PCIe
Only on Double-Width
MCH Base Module
Load
PROM
SPI
SPI
FPGA
Link Status
LED 1-12
HP-I²C

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 10
2.3 Location Diagram
The following location diagram of the NAT-MCH HUB-Module PCIe shows the position
of important components.
Figure 3: NAT-MCH HUB-Module PCIe –Location Diagram (top)
A
M
C
C
O
N
N
E
C
T
O
R
3rd
tong
PCI Express
Switch
PLX PEX8748
Power
Supply
Osc.
MUX
A
M
C
C
O
N
N
E
C
T
O
R
4th
tongue
Load
PROM
Micro-
controller
Temp
Sensor
L
E
D
1
-
12
L
i
n
k
S
t
a
t
u
s
Power
Supply
Power
Supply
MUX
FPGA
Clock
Buffer
Heatsink
Figure 4: NAT-MCH HUB-Module PCIe –Location Diagram (bottom)
A
M
C
C
O
N
N
E
C
T
O
R
4th
tong
A
M
C
C
O
N
N
E
C
T
O
R
3rd
tongue
Temp
Sensor

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 11
3Board Features
The NAT-MCH HUB-Module PCIe is divided into a number of functional blocks, which
are described in the following paragraphs.
3.1 PCI Express Switch PLX PEX8748
The NAT-MCH HUB-Module PCIe is equipped with a PLX PEX8748 PCI Express switch,
which provides non-blocking switching at full line rate. Quality of Service (QoS) is
provided by the PEX8748, supporting 2 virtual cannels and 8 traffic classes per port. One
of all ports can be configured as transparent upstream port, and one of all ports can be
configured as non-transparent upstream port.
The PCI Express Switch PEX8748 can be configured by strapping pins, by loading an
EEPROM, or by PCI Express messages from a host. A standard configuration is done by
the microprocessor and resistors by setting the strapping pins. The values of the
strapping signals that are connected to the microcontroller can be controlled by
programming a register in the microcontroller.
These standard settings can be changed by reading the EEPROM after a reset, or by
receiving PCI Express messages from a host.
The EEPROM contains basic configuration information for the PCIe switch as well as user
settings, e.g. upstream port settings. The user settings can be changed by the CPU on
the NAT-MCH BASE-Module.
The /PERST pin is also connected to the microcontroller. The value of this pin can also be
controlled by programming a register in the microcontroller.
The PLX PEX8748 supports 12 ports, per default with 4 lanes (PCIe x4). As shown in the
following tables a certain switch port is not constrained to the according AMC port or MCH
fabric.
Table 2: PCIe Switch Lane to MCH Fabric Port Mapping
Switch Lanes
MCH Fabric
0
G-4
1
F-4
2
E-4
3
D-4
4
G-3
5
F-3
6
E-3
7
D-3
8
G-2
9
F-2
10
E-2
11
D-2
12
G-1
13
F-1
14
E-1
15
D-1

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 12
Switch Lanes
MCH Fabric
16
D-5
17
E-5
18
F-5
19
G-5
20
D-6
21
E-6
22
F-6
23
G-6
24
D-11
25
E-11
26
F-11
27
G-11
28
D-12 / Root Complex (opt.)
29
E-12 / Root Complex (opt.)
30
F-12 / Root Complex (opt.)
31
G-12 / Root Complex (opt.)
32
G-10
33
F-10
34
E-10
35
D-10
36
G-9
37
F-9
38
E-9
39
D-9
40
G-8
41
F-8
42
E-8
43
D-8
44
G-7
45
F-7
46
E-7
47
D-7
Table 3: Switch Lanes to AMC port mapping for X4-Link
on a standard MicroTCA-Backplane
Switch Port (Lanes)
AMC Slot #
0 (0 –3)
4
1 (4 –7)
3
2 (8 –11)
2
3 (12 –15)
1
8 (16 –19)
5
9 (20 –23)
6
10 (24 –27)
11
11 (28 –31)
12 / Root Complex (opt.)
16 (32 –35)
10
17 (36 –39)
9
18 (40 –43)
8
19 (44 –47)
7

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 13
3.2 Microcontroller
For configuration of the PCIe switch and for providing hot-swap functionality, an 8-bit
Atmel microcontroller resides on the NAT-MCH HUB-Module PCIe. The microcontroller
can be updated by the CPU on the NAT-MCH BASE-Module via SPI interface. Normal
communication between the CPU and the microcontroller is done by IPMI messages over
the I²C interface.
The strapping options and the reset signal of the switch can be controlled by
programming registers in the microcontroller. Also the PCIe Hot-Plug signals can be
served by the microcontroller.
Furthermore, three temperature sensors are connected to a second I²C bus of the
microcontroller. The microcontroller makes these sensors accessible to the CPU on the
NAT-MCH BASE-Module via IPMI.
3.3 FPGA
The Lattice MachXO2 FPGA is used to emulate a set of I2C port expanders that the PLX
switch normally uses to extend its pins for PCIe Hotplug support on all ports. The FPGA
implements an I2C interface towards the PLX switch and behaves as if there were 12 I2C
port expenders connected.
Further it implements a second interface towards the Atmel µC, so that the Hotplug
signals finally can be exchanged with the MCH main firmware.
3.4 Multiplexing Units
There are two PCIe Gen3 compliant multiplexing chips (each can switch two lanes) used
to switch the four lanes going towards AMC12 to the double-width NAT-MCH BASE-
Module. From the BASE-Module these lanes connect to an optional PCIe-capable
module connected as RTM to the double-width BASE-Module.
3.5 PCIe Interfaces
The NAT-MCH HUB-Module PCIe implements interfaces to connect fabrics D to G of up
to 12 AMCs or an optional Root Complex, which is only available on a double-width NAT-
MCH BASE-Module, instead of the 12th AMC.
3.6 Interface to NAT-MCH BASE-Module
The Microcontroller on the NAT-MCH HUB-Module PCIe can be updated by the CPU on
the NAT-MCH BASE-Module via SPI interface. Normal communication between
Microprocessor and CPU is done by IPMI messages via I²C interface.
A configuration EEPROM for the PCIe Switch resides on the NAT-MCH HUB-Module
PCIe. This EEPROM can be programmed / updated by the CPU of the NAT-MCH BASE-
Module via SPI interface.
3.7 Interface to NAT-MCH CLK-Module
The NAT-MCH CLK-Module can provide the 100 MHz PCI Express compliant clock signal
to the NAT-MCH HUB-Module PCIe.

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 14
4Hardware
4.1 LEDs
The NAT-MCH HUB-Module PCIe features 12 green LEDs which reflect the PCIe Link
Status. They can take the following states:
Table 4: LED State –Link Status
LED(1-12) State
Link Status
OFF
No PCIe link established
SLOW BLINK (1 blink/second)
PCIe GEN1 Link (2.5 GBaud)
FAST BLINK (2 blinks/second)
PCIe GEN2 Link (5 GBaud)
SOLID ON
PCIe GEN3 (8 GBaud)

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 15
4.2 Connectors
Figure 5: NAT-MCH HUB-Module PCIe –Connectors (top)
C
O
N
1
C
O
N
2
Heatsink
JP1
Figure 6: NAT-MCH HUB-Module PCIe –Connectors (bottom)
C
O
N
2
C
O
N
1
J1
C
O
N
3
Please refer to the following tables to look up the pin assignment of the NAT-MCH HUB-
Module PCIe.

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 16
4.2.1 CON1: AMC Connector to 3rd tongue
Table 5: CON1: AMC Connector to 3rd tongue –Pin Assignment
Pin #
MCH-Signal
MCH-Signal
Pin #
1
GND
GND
170
2
RSVD
RSVD
169
3
RSVD
RSVD
168
4
GND
GND
167
5
RSVD
RSVD
166
6
RSVD
RSVD
165
7
GND
GND
164
8
NC
NC
163
9
NC
NC-
162
10
GND
GND
161
11
NC
NC
160
12
NC
NC
159
13
GND
GND
158
14
TxFD1+
RxFD1+
157
15
TxFD1-
RxFD1-
156
16
GND
GND
155
17
TxFE1+
RxFE1+
154
18
TxFE1-
RxFE1-
153
19
GND
GND
152
20
TxFF1+
RxFF1+
151
21
TxFF1-
RxFF1-
150
22
GND
GND
149
23
TxFG1+
RxFG1+
148
24
TxFG1-
RxFG1-
147
25
GND
GND
146
26
TxFD2+
RxFD2+
145
27
TxFD2-
RxFD2-
144
28
GND
GND
143
29
TxFE2+
RxFE2+
142
30
TxFE2-
RxFE2-
141
31
GND
GND
140
32
TxFF2+
RxFF2+
139
33
TxFF2-
RxFF2-
138
34
GND
GND
137
35
TxFG2+
RxFG2+
136
36
TxFG2-
RxFG2-
135
37
GND
GND
134
38
TxFD3+
RxFD3+
133
39
TxFD3-
RxFD3-
132
40
GND
GND
131
41
TxFE3+
RxFE3+
130
42
TxFE3-
RxFE3-
129
43
GND
GND
128
44
TxFF3+
RxFF3+
127
45
TxFF3-
RxFF3-
126

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 17
Pin #
MCH-Signal
MCH-Signal
Pin #
46
GND
GND
125
47
TxFG3+
RxFG3+
124
48
TxFG3+
RxFG3-
123
49
GND
GND
122
50
TxFD4+
RxFD4+
121
51
TxFD4-
RxFD4-
120
52
GND
GND
119
53
TxFE4+
RxFE4+
118
54
TxFE4-
RxFE4-
117
55
GND
GND
116
56
TxFF4+
RxFF4+
115
57
TxFF4-
RxFF4-
114
58
GND
GND
113
59
TxFG4+
RxFG4+
112
60
TxFG4-
RxFG4-
111
61
GND
GND
110
62
TxFD5+
RxFD5+
109
63
TxFD5-
RxFD5-
108
64
GND
GND
107
65
TxFE5+
RxFE5+
106
66
TxFE5-
RxFE5-
105
67
GND
GND
104
68
TxFF5+
RxFF5+
103
69
TxFF5-
RxFF5-
102
70
GND
GND
101
71
TxFG5+
RxFG5+
100
72
TxFG5-
RxFG5-
99
73
GND
GND
98
74
TxFD6+
RxFD6+
97
75
TxFD6-
RxFD6-
96
76
GND
GND
95
77
TxFE6+
RxFE6+
94
78
TxFE6-
RxFE6-
93
79
GND
GND
92
80
TxFF6+
RxFF6+
91
81
TxFF6+
RxFF6-
90
82
GND
GND
89
83
TxFG6+
RxFG6+
88
84
TxFG6-
RxFG6-
87
85
GND
GND
86

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 18
4.2.2 CON2: AMC Connector to 4th tongue
Table 6: CON2: AMC Connector to 4th tongue –Pin Assignment
Pin #
MCH-Signal
MCH-Signal
Pin #
1
GND
GND
170
2
RSVD
RSVD
169
3
RSVD
RSVD
168
4
GND
GND
167
5
RSVD
RSVD
166
6
RSVD
RSVD
165
7
GND
GND
164
8
NC
NC
163
9
NC
NC-
162
10
GND
GND
161
11
NC
NC
160
12
NC
NC
159
13
GND
GND
158
14
TxFD7+
RxFD7+
157
15
TxFD7-
RxFD7-
156
16
GND
GND
155
17
TxFE7+
RxFE7+
154
18
TxFE7-
RxFE7-
153
19
GND
GND
152
20
TxFF7+
RxFF7+
151
21
TxFF7-
RxFF7-
150
22
GND
GND
149
23
TxFG7+
RxFG7+
148
24
TxFG7-
RxFG7-
147
25
GND
GND
146
26
TxFD8+
RxFD8+
145
27
TxFD8-
RxFD8-
144
28
GND
GND
143
29
TxFE8+
RxFE8+
142
30
TxFE8-
RxFE8-
141
31
GND
GND
140
32
TxFF8+
RxFF8+
139
33
TxFF8-
RxFF8-
138
34
GND
GND
137
35
TxFG8+
RxFG8+
136
36
TxFG8-
RxFG8-
135
37
GND
GND
134
38
TxFD9+
RxFD9+
133
39
TxFD9-
RxFD9-
132
40
GND
GND
131
41
TxFE9+
RxFE9+
130
42
TxFE9-
RxFE9-
129
43
GND
GND
128
44
TxFF9+
RxFF9+
127
45
TxFF9-
RxFF9-
126

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 19
Pin #
MCH-Signal
MCH-Signal
Pin #
46
GND
GND
125
47
TxFG9+
RxFG9+
124
48
TxFG9+
RxFG9-
123
49
GND
GND
122
50
TxFD10+
RxFD10+
121
51
TxFD10-
RxFD10-
120
52
GND
GND
119
53
TxFE10+
RxFE10+
118
54
TxFE10-
RxFE10-
117
55
GND
GND
116
56
TxFF10+
RxFF10+
115
57
TxFF10-
RxFF10-
114
58
GND
GND
113
59
TxFG10+
RxFG10+
112
60
TxFG10-
RxFG10-
111
61
GND
GND
110
62
TxFD11+
RxFD5+
109
63
TxFD11-
RxFD5-
108
64
GND
GND
107
65
TxFE11+
RxFE5+
106
66
TxFE11-
RxFE5-
105
67
GND
GND
104
68
TxFF11+
RxFF11+
103
69
TxFF11-
RxFF11-
102
70
GND
GND
101
71
TxFG11+
RxFG11+
100
72
TxFG11-
RxFG11-
99
73
GND
GND
98
74
TxFD12+
RxFD12+
97
75
TxFD12-
RxFD12-
96
76
GND
GND
95
77
TxFE12+
RxFE12+
94
78
TxFE12-
RxFE12-
93
79
GND
GND
92
80
TxFF12+
RxFF12+
91
81
TxFF12+
RxFF12-
90
82
GND
GND
89
83
TxFG12+
RxFG12+
88
84
TxFG12-
RxFG12-
87
85
GND
GND
86

NAT-MCH HUB-Module PCIe –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 20
4.2.3 CON3: Connector to NAT-MCH CLK/BASE-Module
Table 7: CON3: Connector to NAT-MCH CLK/BASE-Module
–Pin Assignment
Pin #
Signal
Signal
Pin #
1
INT1
INT2
2
3
GND
GND
4
5
NC
NC
6
7
NC
NC
8
9
+12V
+12V
10
11
+12V
+12V
12
13
PCIeCLK HUB_P
NC
14
15
PCIeCLK HUB_N
SPICLK
16
17
GND
NC
18
19
MOSI
MISO
20
21
GND
/SPISEL HUBPCB
22
23
SCL
NC
24
25
SDA
/RESET HUBPCB
26
27
GND
GND
28
CON3 connects to the NAT-MCH CLK-Module; on the CLK-Module these signals
are routed via another connector to the NAT-MCH BASE-Module.
4.2.4 JP1: JTAG programming interface
The JTAG programming interface is for development use only and not intended to
be used by the customer.