N.A.T. NAT-MCH Use and care manual

NAT-MCH Clock-Module – Technical Reference Manual
NAT-MCH
Clock-Module
Technical Reference Manual V 1.4
CLK Module HW
Revision 2.1 and Revision 2.3

NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH 2
The NAT-MCH has been designed by:
N.A.T. GmbH
Kamillenweg 22
D-53757 Sankt Augustin
Phone: ++49/2241/3989-0
Fax: ++49/2241/3989-10
E-Mail: [email protected]
Internet: http://www.nateurope.com

NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH 3
Disclaimer
The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.), repre-
sents the current status of the product’s development. The documentation is updated on a
regular basis. Any changes which might ensue, including those necessitated by updated speci-
fications, are considered in the latest version of this documentation. N.A.T. is under no obli-
gation to notify any person, organization, or institution of such changes or to make these
changes public in any other way.
We must caution you, that this publication could include technical inaccuracies or typographi-
cal errors.
N.A.T. offers no warranty, either expressed or implied, for the contents of this documentation
or for the product described therein, including but not limited to the warranties of merchant-
ability or the fitness of the product for any specific purpose.
In no event will N.A.T. be liable for any loss of data or for errors in data utilization or
processing resulting from the use of this product or the documentation. In particular, N.A.T.
will not be responsible for any direct or indirect damages (including lost profits, lost savings,
delays or interruptions in the flow of business activities, including but not limited to, special,
incidental, consequential, or other similar damages) arising out of the use of or inability to use
this product or the associated documentation, even if N.A.T. or any authorized N.A.T.
representative has been advised of the possibility of such damages.
The use of registered names, trademarks, etc. in this publication does not imply, even in the
absence of a specific statement, that such names are exempt from the relevant protective laws
and regulations (patent laws, trade mark laws, etc.) and therefore free for general use. In no
case does N.A.T. guarantee that the information given in this documentation is free of such
third-party rights.
Neither this documentation nor any part thereof may be copied, translated, or reduced to any
electronic medium or machine form without the prior written consent from N.A.T. GmbH.
This product (and the associated documentation) is governed by the N.A.T. General
Conditions and Terms of Delivery and Payment.
Note:
The release of the Hardware Manual is related
to a certain HW board revision given in the
document title. For HW revisions earlier than
the one given in the document title please
contact N.A.T. for the corresponding older
Hardware Manual release.

NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH 4
Table of Contents
CONVENTIONS................................................................................................................................................... 8
1BOARD SPECIFICATION........................................................................................................................ 9
2STATEMENT ON ENVIRONMENTAL PROTECTION.................................................................... 10
2.1 COMPLIANCE TO ROHS DIRECTIVE .................................................................................................... 10
2.2 COMPLIANCE TO WEEE DIRECTIVE ................................................................................................... 10
2.3 COMPLIANCE TO CE DIRECTIVE ......................................................................................................... 11
3INSTALLATION ...................................................................................................................................... 12
3.1 SAFETY NOTE..................................................................................................................................... 12
3.2 INSTALLATION PREREQUISITES AND REQUIREMENTS ......................................................................... 12
3.2.1 Requirements................................................................................................................................. 12
3.2.2 Power supply................................................................................................................................. 12
3.2.3 Automatic Power Up..................................................................................................................... 12
4INTRODUCTION..................................................................................................................................... 13
5CLK MODULE BASICS.......................................................................................................................... 14
6BLOCK DIAGRAM OF THE NAT-MCH CLK MODULE................................................................. 15
7BOARD FEATURES ................................................................................................................................ 16
8FUNCTIONAL BLOCKS......................................................................................................................... 18
8.1 STRATUM 3PLL................................................................................................................................. 18
8.2 MICROPROCESSOR.............................................................................................................................. 19
8.3 CLK-MULTIPLEX FUNCTION .............................................................................................................. 19
8.4 M-LVDS /HCSL TRANSCEIVER ........................................................................................................ 19
9LOCATION OVERVIEW........................................................................................................................ 21
10 CONNECTORS......................................................................................................................................... 23
10.1 CONNECTOR OVERVIEW ..................................................................................................................... 23
10.2 MCH CONNECTOR CON1 .................................................................................................................. 24
10.3 CONNECTOR CON2: INTERFACE TO BASIC-PCB ................................................................................. 26
10.4 CONNECTOR CON3: INTERFACE TO HUB-PCB................................................................................... 27
10.5 CONNECTOR JP1: ALTERA FPGA PROGRAMMING PORT .................................................................... 27
11 NAT-MCH CLK MODULE PROGRAMMING NOTES ..................................................................... 28
11.1 SPI INTERFACE................................................................................................................................... 28
11.2 I²C INTERFACE.................................................................................................................................... 28
11.3 REGISTER............................................................................................................................................ 28
11.3.1 Board Identifier Register.......................................................................................................... 29
11.3.2 PCB Revision Register ............................................................................................................. 29
11.3.3 Firmware Version Register ...................................................................................................... 29
11.3.4 FPGA Revision Register........................................................................................................... 30
11.3.5 Reference 0 Selection Register................................................................................................. 31
11.3.6 Reference 1 Selection Register................................................................................................. 32

NAT-MCH Clock-PCB – Technical Reference Manual
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© N.A.T. GmbH 5
11.3.7 Source Selection 1 Register...................................................................................................... 33
11.3.8 Source Selection 2 Register...................................................................................................... 34
11.3.9 Source Selection 3 Register...................................................................................................... 35
11.3.10 Source Selection CLK1 Update Register.................................................................................. 36
11.3.11 Source Selection CLK3 Update Register.................................................................................. 37
11.3.12 Transceiver Control 1 Register ................................................................................................ 38
11.3.13 Transceiver Control 2 Register ................................................................................................ 39
11.3.14 Transceiver Control 3 Register ................................................................................................ 40
11.3.15 Transceiver Control 4 Register ................................................................................................ 41
11.3.16 Transceiver Control 5 Register ................................................................................................ 42
11.3.17 Transceiver Control 6 Register ................................................................................................ 43
11.3.18 Transceiver Control 7 Register ................................................................................................ 44
11.3.19 PLL Control 1 Register ............................................................................................................ 45
11.3.20 PLL Control 2 Register ............................................................................................................ 46
11.3.21 PLL Output Signals Register.................................................................................................... 47
11.3.22 Reserved Register..................................................................................................................... 48
11.3.23 Synchronized Clock Register.................................................................................................... 49
11.3.24 LED2 Control Register............................................................................................................. 51
11.3.25 Holdover Function Control Register........................................................................................ 52
11.3.26 External Reference Output Control Register............................................................................ 53
KNOWN BUGS / RESTRICTIONS.................................................................................................................. 55
APPENDIX A: REFERENCE DOCUMENTATION...................................................................................... 56
APPENDIX B: DOCUMENT’S HISTORY...................................................................................................... 57
List of Figures
Figure 2: Block Diagram of the NAT-MCH CLK Module .....................................................15
Figure 5: Location Diagram of the NAT-MCH CLK Module v2.1 (top-view).......................21
Figure 6: Location diagram of the NAT-MCH CLK Module v2.1 (bottom-view).................. 21
Figure 9: Connectors of the NAT-MCH CLK Module (top view) ..........................................23
Figure 10: Connectors of the NAT-MCH CLK Module (bottom view).................................. 23
Figure 11: Detailed Functional overview.................................................................................28

NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH 6
List of Tables
Table 1: List of used Abbreviations .....................................................................................8
Table 2: NAT-MCH CLK Module Features........................................................................9
Table 3: MCH Connector CON1........................................................................................24
Table 4: Connector to Basic-PCB CON2...........................................................................26
Table 5: Connector to Hub-PCB CON3.............................................................................27
Table 6: Altera FPGA Programming Port..........................................................................27
Table 7: Board Identifier Register......................................................................................29
Table 8: PCB Revision Register.........................................................................................29
Table 9: FW_VERSION Register......................................................................................29
Table 10: FPGA Revision Register......................................................................................30
Table 11: REF0_SEL Register.............................................................................................31
Table 12: REF0_SEL - Register Bits ...................................................................................31
Table 13: REF1_SEL Register.............................................................................................32
Table 14: REF1_SEL - Register Bits ...................................................................................32
Table 15: SRC_SEL1 Register.............................................................................................33
Table 16: SRC_SEL1 - Register Bits...................................................................................33
Table 17: SRC_SEL2 Register.............................................................................................34
Table 18: SRC_SEL2 - Register Bits...................................................................................34
Table 19: SRC_SEL3 Register.............................................................................................35
Table 20: SRC_SEL3 - Register Bits...................................................................................35
Table 21: SRC_SEL_CLK1_UD Register...........................................................................36
Table 22: SRC_SEL_CLK1_UD - Register Bits .................................................................36
Table 23: SRC_SEL_CLK3_UD Register...........................................................................37
Table 24: SRC_SEL_CLK3_UD - Register Bits .................................................................37
Table 25: TRANSC_CTL1 Register....................................................................................38
Table 26: TRANSC_CTL1 - Register Bits ..........................................................................38
Table 27: TRANSC_CTL2 Register....................................................................................39
Table 28: TRANSC_CTL2 - Register Bits ..........................................................................39
Table 29: TRANSC_CTL3 Register....................................................................................40
Table 30: TRANSC_CTL3 - Register Bits ..........................................................................40
Table 31: TRANSC_CTL4 Register....................................................................................41
Table 32: TRANSC_CTL4 - Register Bits ..........................................................................41
Table 33: TRANSC_CTL5 Register....................................................................................42
Table 34: TRANSC_CTL5 - Register Bits ..........................................................................42
Table 35: TRANSC_CTL6 Register....................................................................................43
Table 36: TRANSC_CTL6 - Register Bits ..........................................................................43
Table 37: TRANSC_CTL7 Register....................................................................................44
Table 38: TRANSC_CTL7 - Register Bits ..........................................................................44
Table 39: PLL_CTR1 Register.............................................................................................45
Table 40: PLL_CTR1 – Register Bits..................................................................................45
Table 41: PLL_CTR2 Register.............................................................................................46

NAT-MCH Clock-PCB – Technical Reference Manual
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© N.A.T. GmbH 7
Table 42: PLL_CTR2 - Register Bits...................................................................................46
Table 43: PLL_Outp Register ..............................................................................................47
Table 44: PLL_Outp - Register Bits.....................................................................................47
Table 45: RES_1 Register....................................................................................................48
Table 46: RES_2 Register....................................................................................................48
Table 47: RES_3 Register....................................................................................................48
Table 48: RES_4 Register....................................................................................................48
Table 49: RES_5 Register....................................................................................................48
Table 50: RES_6 Register....................................................................................................49
Table 51: SYNC_CLK Register...........................................................................................49
Table 52: SYNC_CLK - Register Bits.................................................................................50
Table 53: LED2_CTR Register............................................................................................51
Table 54: LED2_CTR - Register Bits..................................................................................51
Table 55: H_OVER_FUNKT_CTL Register.......................................................................52
Table 56: H_OVER_FUNKT_CTL - Register Bits............................................................. 52
Table 57: EXT_REF_OUTP_CTL Register ........................................................................53
Table 58: EXT_REF_OUTP_CTL Register Bits.................................................................53

NAT-MCH Clock-PCB – Technical Reference Manual
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© N.A.T. GmbH 8
Conventions
If not otherwise specified, addresses and memory maps are written in hexadecimal notation,
identified by 0x.
Table 1: gives a list of the abbreviations used in this document:
Table 1: List of used Abbreviations
Abbreviation
Description
AMC Advanced Mezzanine Card
b bit, binary
B Byte
ColdFire MCF5470
CPU Central Processing Unit
CU Cooling Unit
DMA Direct Memory Access
E1 2.048 Mbit G.703 Interface
FLASH Programmable ROM
FRU Field Replaceable Unit
J1 1,544 Mbit G.703 Interface (Japan)
K kilo (factor 400 in hex, factor 1024 in decimal)
LIU Line Interface Unit
M mega (factor 10,0000 in hex, factor 1,048,576 in
decimal)
MCH µTCA Carrier Hub
MHz 1,000,000 Herz
µTCA Micro Telecommunications Computing Architecture
PCIe PCI Express
PCI Peripheral Component Interconnect
PM Power Manager
RAM Random Access Memory
ROM Read Only Memory
SDRAM Synchronous Dynamic RAM
SSC Spread Spectrum Clock
T1 1,544 Mbit G.703 Interface (USA)

NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH 9
1 Board Specification
Table 2: NAT-MCH CLK Module Features
Power Consumption 12 V / 0.5 A max. (only CLK Module)
Environmental
Conditions
Temperature (operating):
Temperature (storage):
Humidity:
0°C to +50°C with forced cooling
-40°C to +85°C
10 % to 90 % rh noncondensing
Standards Compliance PICMG µTCA.0 Rev. 1.0
PICMG AMC.0 Rev. 2.0
PICMG AMC.3 Rev. 1.0
PICMG SFP.0 Rev. 1.0 (System Fabric Plane Format)
IPMI Specification v2.0 Rev. 1.0
Product Safety The board complies with EN60950 and UL1950
PLL Input
Frequencies
(To be sourced from
external Reference via
Face Plate Connector,
CLK1 or CLK2)
•2 kHz
•8 kHz
•1.544 MHz
•2.048 MHz
•8.192 MHz
•16.384 MHz
•19.44 MHz
PLL Output
Frequencies
(To be distributed via Face
Plate Connector, CLK1,
CLK2 orCLK3 )
•1.544 MHz (T1)
•2.048 MHz (E1)
•3.088 MHz
•16.384 MHz
•19.44 MHz (SDH)
•4.096 MHz or 32.768 MHz
•8.192 MHz or 65.536 MHz
•6.312 MHz (DS2)
•8.448 MHz (E2)
•44.736 MHz (DS3)
•34.368 MHz (E3)
•2 kHz and 8 kHz (frame pulses)

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© N.A.T. GmbH 10
2 Statement on Environmental Protection
2.1 Compliance to RoHS Directive
Directive 2002/95/EC of the European Commission on the "Restriction of the use of
certain Hazardous Substances in Electrical and Electronic Equipment" (RoHS)
predicts that all electrical and electronic equipment being put on the European market
after June 30th, 2006 must contain lead, mercury, hexavalent chromium,
polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE) and
cadmium in maximum concentration values of 0.1% respective 0.01% by weight in
homogenous materials only.
As these hazardous substances are currently used with semiconductors, plastics (i.e.
semiconductor packages, connectors) and soldering tin any hardware product is
affected by the RoHS directive if it does not belong to one of the groups of products
exempted from the RoHS directive.
Although many of hardware products of N.A.T. are exempted from the RoHS
directive it is a declared policy of N.A.T. to provide all products fully compliant to the
RoHS directive as soon as possible. For this purpose since January 31st, 2005 N.A.T.
is requesting RoHS compliant deliveries from its suppliers. Special attention and care
has been paid to the production cycle, so that wherever and whenever possible RoHS
components are used with N.A.T. hardware products already.
2.2 Compliance to WEEE Directive
Directive 2002/95/EC of the European Commission on "Waste Electrical and
Electronic Equipment" (WEEE) predicts that every manufacturer of electrical and
electronical equipment which is put on the European market has to contribute to the
reuse, recycling and other forms of recovery of such waste so as to reduce disposal.
Moreover this directive refers to the Directive 2002/95/EC of the European
Commission on the "Restriction of the use of certain Hazardous Substances in
Electrical and Electronic Equipment" (RoHS).
Having its main focus on private persons and households using such electrical and
electronic equipment the directive also affects business-to-business relationships. The
directive is quite restrictive on how such waste of private persons and households has
to be handled by the supplier/manufacturer, however, it allows a greater flexibility in
business-to-business relationships. This pays tribute to the fact with industrial use
electrical and electronical products are commonly integrated into larger and more
complex environments or systems that cannot easily be split up again when it comes to
their disposal at the end of their life cycles.