
NAT-MCH HUB-Module XAUI –Technical Reference Manual
Version 1.2 © N.A.T. GmbH 4
Table of Contents
DISCLAIMER ....................................................................................................... 3
TABLE OF CONTENTS .......................................................................................... 4
LIST OF TABLES .................................................................................................. 5
LIST OF FIGURES................................................................................................ 5
CONVENTIONS.................................................................................................... 6
1INTRODUCTION ........................................................................................... 7
2OVERVIEW ................................................................................................... 9
2.1 MAJOR FEATURES......................................................................................... 9
2.2 TECHNICAL FEATURES ................................................................................... 9
2.3 BLOCK DIAGRAM ........................................................................................10
2.4 LOCATION DIAGRAM ....................................................................................11
3FUNCTIONAL BLOCKS ................................................................................ 12
3.1 XAUI SWITCH ...........................................................................................12
3.2 FPGA .....................................................................................................12
3.3 MICROCONTROLLER .....................................................................................13
3.4 INTERFACES ..............................................................................................13
3.5 UPLINK OPTION..........................................................................................13
4HARDWARE ................................................................................................ 14
4.1 CONNECTORS ............................................................................................14
4.1.1 Connector Overview..........................................................................14
4.1.2 CON1: HUB-Module XAUI Backplane Connector ....................................15
4.1.3 CON2: HUB-Module x48 Extender Connector........................................17
4.1.4 CON3: CLK-Module Connector ............................................................19
4.1.5 CON4: Uplink-Module Connector.........................................................20
4.1.6 JP1: FPGA Programming Interface ......................................................21
5PROGRAMMING NOTES .............................................................................. 22
5.1 BOARD IDENTIFIER REGISTER .........................................................................22
5.2 PCB REVISION REGISTER ..............................................................................22
5.3 FIRMWARE VERSION ....................................................................................23
5.4 HUB MODULE XAUI TYPE ..............................................................................23
5.5 FPGA REVISION REGISTER ............................................................................23
5.6 SWITCH CONTROL REGISTER ..........................................................................24
5.7 RESERVED ................................................................................................24
5.8 SPI MULTIPLEXER CONTROL ...........................................................................25
6BOARD SPECIFICATION ............................................................................. 26
7INSTALLATION .......................................................................................... 27
7.1 SAFETY NOTE ............................................................................................27
7.2 INSTALLATION PREREQUISITES AND REQUIREMENTS ...............................................27
7.2.1 Requirements ..................................................................................27