N.A.T. NAT-MCH Product manual

NAT-MCH BASE-Module –Technical Reference Manual
NAT-MCH
TCA Telecom MCH Module
Technical Reference Manual V 2.10
BASE-Module HW Revision 3.1 to 3.5

NAT-MCH BASE-Module–Technical Reference Manual
Version 2.10 © N.A.T. GmbH 2
The NAT-MCH has been designed by:
N.A.T. GmbH
Konrad-Zuse-Platz 9
D-53227 Bonn-Oberkassel
Phone: +49 / 228 / 965 864 - 0
Fax: +49 / 228 / 965 864 - 10
Internet: http://www.nateurope.com

NAT-MCH BASE-Module–Technical Reference Manual
Version 2.10 © N.A.T. GmbH 3
Disclaimer
The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.),
represents the current status of the product’s development. The documentation is
updated on a regular basis. Any changes which might ensue, including those necessitated
by updated specifications, are considered in the latest version of this documentation.
N.A.T. is under no obligation to notify any person, organization, or institution of such
changes or to make these changes public in any other way.
We must caution you, that this publication could include technical inaccuracies or
typographical errors.
N.A.T. offers no warranty, either expressed or implied, for the contents of this
documentation or for the product described therein, including but not limited to the
warranties of merchantability or the fitness of the product for any specific purpose.
In no event will N.A.T. be liable for any loss of data or for errors in data utilization or
processing resulting from the use of this product or the documentation. In particular,
N.A.T. will not be responsible for any direct or indirect damages (including lost profits,
lost savings, delays or interruptions in the flow of business activities, including but not
limited to, special, incidental, consequential, or other similar damages) arising out of the
use of or inability to use this product or the associated documentation, even if N.A.T. or
any authorized N.A.T. representative has been advised of the possibility of such
damages.
The use of registered names, trademarks, etc. in this publication does not imply, even in
the absence of a specific statement, that such names are exempt from the relevant
protective laws and regulations (patent laws, trade mark laws, etc.) and therefore free
for general use. In no case does N.A.T. guarantee that the information given in this
documentation is free of such third-party rights.
Neither this documentation nor any part thereof may be copied, translated, or reduced to
any electronic medium or machine form without the prior written consent from N.A.T.
GmbH.
This product (and the associated documentation) is governed by the N.A.T. General
Conditions and Terms of Delivery and Payment.
Note:
The release of the Hardware Manual is related to a certain HW board revision
given in the document title. For HW revisions earlier than the one given in the
document title please contact N.A.T. for the corresponding older Hardware
Manual release.

NAT-MCH BASE-Module–Technical Reference Manual
Version 2.10 © N.A.T. GmbH 4
Table of Contents
TABLE OF CONTENTS .......................................................................................... 4
LIST OF TABLES .................................................................................................. 6
LIST OF FIGURES................................................................................................ 6
CONVENTIONS.................................................................................................... 7
1INTRODUCTION ........................................................................................... 8
2OVERVIEW ................................................................................................... 9
2.1 MAJOR FEATURES......................................................................................... 9
2.2 BLOCK DIAGRAM ........................................................................................10
2.3 LOCATION DIAGRAM ....................................................................................11
3BOARD FEATURES ...................................................................................... 12
3.1 CPU .......................................................................................................12
3.2 MEMORY ..................................................................................................12
3.2.1 DDR2SDRAM....................................................................................12
3.2.2 FLASH.............................................................................................12
3.3 BACKPLANE INTERFACES................................................................................13
3.3.1 IPMB...............................................................................................13
3.3.2 I²C .................................................................................................13
3.3.3 Ethernet ..........................................................................................13
3.4 FRONT PANEL INTERFACES .............................................................................13
3.4.1 Ethernet Uplink Ports ........................................................................13
3.4.2 USB Debug Port ...............................................................................14
3.4.3 Clock Interface .................................................................................14
3.4.3.1 Coax-IO ..................................................................................................14
3.4.3.2 RJ45-Clock-Interface ................................................................................15
3.5 INTERFACE TO EXTENSION MODULES .................................................................15
3.5.1 NAT-MCH CKL-Module / NAT-MCH CLK-PHYS-Module ............................15
3.5.2 NAT-MCH HUB-Module ......................................................................15
3.6 I2CDEVICES .............................................................................................16
3.7 ETHERNET SWITCH ......................................................................................16
4HARDWARE ................................................................................................ 17
4.1 FRONT PANEL AND LEDS...............................................................................17
4.1.1 MCH Basic-LEDs ...............................................................................17
4.1.2 RJ45-LEDs .......................................................................................17
4.1.3 Status LEDs .....................................................................................17
4.2 CONNECTORS AND SWITCHES .........................................................................18
4.2.1 CON1: MCH Connector ......................................................................19
4.2.2 CON2: Extension Module Connector ....................................................21
4.2.3 JP1: Altera FPGA Programming Port ....................................................21
4.2.4 JP2: LED-Module Connector ...............................................................21
4.2.5 JP3: Development Connector .............................................................22
4.2.6 P3: External Clock Transceiver Module Connector .................................22
4.2.7 SW1: Hot Swap Switch......................................................................22
4.2.8 SW2: General Purpose DIL Switch ......................................................22
4.2.9 S1: Micro USB Connector ..................................................................23

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4.2.10 S100: RJ45 Connector ......................................................................23
4.2.11 S101: RJ45 Connector ......................................................................23
5PROGRAMMING NOTES .............................................................................. 24
6BOARD SPECIFICATION ............................................................................. 25
7INSTALLATION .......................................................................................... 26
7.1 SAFETY NOTE ............................................................................................26
7.2 INSTALLATION PREREQUISITES AND REQUIREMENTS ...............................................27
7.2.1 Requirements ..................................................................................27
7.2.2 Power Supply ...................................................................................27
7.2.3 Automatic Power Up..........................................................................27
7.3 STATEMENT ON ENVIRONMENTAL PROTECTION ......................................................28
7.3.1 Compliance to RoHS Directive ............................................................28
7.3.2 Compliance to WEEE Directive............................................................28
7.3.3 Compliance to CE Directive ................................................................29
7.3.4 Product Safety .................................................................................29
8KNOWN BUGS / RESTRICTIONS................................................................. 30
APPENDIX A: REFERENCE DOCUMENTATION .................................................... 31
APPENDIX B: DOCUMENT’S HISTORY ............................................................... 32

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List of Tables
Table 1: List of used Abbreviations ...................................................................... 7
Table 2: NAT-MCH BASE-Module –Coax-IO signal mapping...................................15
Table 3: NAT-MCH BASE-Module –Coax-IO Electrical characteristics ......................15
Table 4: CON1: MCH Connector –Pin-Assignment ................................................19
Table 5: CON2: Extension Module Connector –Pin Assignment ..............................21
Table 6: JP1: Altera FPGA Programming Port –Pin Assignment ..............................21
Table 7: JP2: LED-Module Connector –Pin Assignment .........................................21
Table 8: JP3: Development Connector –Pin Assignment .......................................22
Table 9: P3: External Clock Transceiver Module Connector –Pin Assignment ..........22
Table 10: S1: Micro USB Connector –Pin Assignment.............................................23
Table 11: S100: RJ45 Connector –Pin-Assignment ................................................23
Table 12: S101: RJ45 Connector –Pin-Assignment –GbE-Interface ........................23
Table 13: S101: RJ45 Connector –Pin-Assignment –RJ45-Clock-Interface ..............23
Table 14: NAT-MCH BASE-Module –Features ........................................................25
List of Figures
Figure 1: NAT-MCH BASE-Module –Block Diagram incl. LED Module ........................10
Figure 2: NAT-MCH BASE-Module –Location Diagram –top-view ............................11
Figure 3: NAT-MCH BASE-Module –Front Panel.....................................................17
Figure 4: NAT-MCH BASE-Module –Connectors –Overview ....................................18

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Version 2.10 © N.A.T. GmbH 7
Conventions
If not otherwise specified, addresses and memory maps are written in hexadecimal
notation, identified by 0x.
The following table gives a list of the abbreviations used in this document:
Table 1: List of used Abbreviations
Abbreviation
Description
AMC
Advanced Mezzanine Card
b
bit, binary
B
Byte
ColdFire
MCF54452
CPU
Central Processing Unit
CU
Cooling Unit
DMA
Direct Memory Access
E1
2.048 Mbit G.703 Interface
FLASH
Programmable ROM
FRU
Field Replaceable Unit
J1
1,544 Mbit G.703 Interface (Japan)
K
kilo (factor 400 in hex, factor 1024 in decimal)
LIU
Line Interface Unit
M
mega (factor 10,0000 in hex, factor 1,048,576 in decimal)
MCH
µTCA Carrier Hub
MHz
1,000,000 Herz
µTCA
Micro Telecommunications Computing Architecture
PCIe
PCI Express
PCI
Peripheral Component Interconnect
PM
Power Manager
RAM
Random Access Memory
ROM
Read Only Memory
SDRAM
Synchronous Dynamic RAM
SSC
Spread Spectrum Clock
T1
1,544 Mbit G.703 Interface (USA)

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1Introduction
The NAT-MCH BASE-Module satisfies the basic requirements of the MicroTCA
Specification for a MicroTCA Carrier Hub. The main capabilities of the BASE-MODULE
are:
management of up to 12 AMCs, two cooling units (CUs) and up to four power
modules (PMs)
Gigabit Ethernet Hub Function for Fabric A ( up to 12 AMCs) and for the
Update Fabric A to a second (redundant) NAT-MCH
The NAT-MCH consists of a BASE-MODULE, which can be expanded with additional
extension PCBs. To meet also the optional requirements of the MicroTCA specification, a
CLK-MODULE and different HUB-MODULEs are available. With the CLK-MODULE the
following functions can be enabled:
generation and distribution of synchronized clock signals for up to 12 AMCs
By extending the NAT-MCH with a HUB-MODULE, hub functions for fabric D to G can be
enabled. With the different versions the customers have the opportunity to choose a
HUB-MODULE that fits best to their application. The versions differ in:
max. number of supported AMCs ( up to 6 / up to 12)
supported protocols:
PCI Express
Serial Rapid IO
10Gigabit Ethernet (XAUI)
The features of the individual extension PCBs are described in more detail in the
corresponding Technical Reference Manuals.

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2Overview
2.1 Major Features
ColdFire MCF54452 32-bit CPU @266MHz
up to 64 MB main Memory (SDRAM) - 32 bit wide
up to 64 MB FLASH –16 bit wide
12 x IPMB-L interface for AMCs
IPMB-L interface for a second NAT-MCH
IPMB-0 interface for CUs and PMs
I²C interface on backplane to access FRU information device
Gigabit Ethernet Hub function for fabric A
1000BaseX over Backplane
up to 12 AMCs
second MCH
two 1000BaseT channel on front panel
1000BaseX channel to MCH Hub-Module (not supported by all Hub Modules)
USB debug port on faceplate
RJ45-Clock-Interface
Interface to extension PCBs (extension PCBs are optional)
NAT-MCH CLK-Module
NAT-MCH CLK-PHYS-Module
Various NAT-MCH HUB-Modules (e.g. PCIe, SRIO, XAUI)
Access to all extension modules via I²C and SPI; 1000BaseX for XAUI only!
100Mbit Ethernet interface between CPU and Ethernet switch for:
communication with external Shelf or System Manager
software update
Various status LEDs
12 bicolour LEDs for AMC status information
2 bicolour LEDs for CU status information
2 bicolour LEDs for PM status information
For detailed description see the following chapter.

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2.2 Block Diagram
The following figure shows a block diagram of the NAT-MCH BASE-Module and optional
available extension modules. If the extension module is added, customized I/O
functionality is available.
NAT-MCH BASE-Module –Block Diagram incl. LED ModuleFigure 1:
MCF54452
Coldfire
12 x IPMB-L
IPMB-0
I²C
Cyclone
Gigabit
Ethernet
(1000Base-X)
SWITCH
Connector to CLK/
Hub-Module
backplane connector
Gigabit Ethernet
Phy
Gigabit Ethernet
Phy
1000Base-X
MII
SPI
Connector to LED-
Modul
RJ-45
RJ-45
CLK
connector
micro-
USB
USB
64MB
DDR2
1000Base-T
1000Base-T
64MB
FLASH
CPU local bus
CPU SDRAM bus
ext. CLK
ribbon cable
BASIC-PCB
NAT-MCH
LED
LED
LED
LED
AMCs
CUs
PMs
LED-MODUL
NAT-MCH
Fabric A
1000Base-X
to 12
AMCs
Update Fabric A
to second
NAT-MCH
1000Base-X
IPMB-L
to 12 AMCs
and to second
NAT-MCH
IPMB-0
to CUs and
PMs
I²C
to FRU
information
device
(on backplane)
I²C (for IPMI)
Micro-
controller
1000Base-X
1000
Base-X
to Hub-
Module
optional
optional
*External
Clock
transceiver
Module
* There are different external clock transceiver modules available. Please refer to the
NAT-MCH CLK-Module technical reference manual for a more detailed description.
As it can be seen in Figure 1:, a LED-Module belongs to the NAT-MCH BASE-Module; it
is mounted on the front panel.
Please note: the LED-Module, the second optional RJ45 and the external clock
transceiver module are not available for the LC (Low Cost) version!

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2.3 Location Diagram
The position of important components is shown in the following location overview.
Depending on the board type it may be that the board does not include all components
named in the location diagram.
NAT-MCH BASE-Module –Location Diagram –top-viewFigure 2:

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3Board Features
The NAT-MCH BASE-Module can be divided into a number of functional blocks, which
are described in the following paragraphs.
3.1 CPU
The NAT-MCH BASE-Module features a 32-bit CPU ColdFire MCF54452 (Freescale)
which is based on the V4e ColdFire core. The MCF54452 includes a memory management
unit (MMU), a dual precision floating-point unit (FPU) and an enhanced multiply-
accumulate unit (EMAC), delivering 308 (Drystone 2.1) MIPS at 266 MHz.
The processor has integrated a 32 KB I-Cache, a 32 KB D-Cache and 32 KB on-chip
system SRAM. The MCF54452 is equipped with a 32-bit DDR2 266 controller at 133 MHz
clock rate.
The MFC5470 ColdFire integrates the following interfaces:
two 10/100 Ethernet Controllers (FECs)
DSPI –SPI with DMA capability
a I²C interface
a 16-channel DMA controller
USB Interface
3.2 Memory
3.2.1 DDR2SDRAM
The onboard DDR2SDRAM memory is 16 bit wide; its size is 32 or 64 MB
(assembly option). The interface to the SDRAM is implemented in the ColdFire
MCF54452. By programming several registers, the SDRAM controller can be
adapted to different RAM architectures.
3.2.2 FLASH
FLASH memory is connected to the demultiplexed upper 16 data bits D0 –15 of
the local bus and to the latched address lines. Its size is 16, 32 or 64 MB
(assembly option).The FLASH on the NAT-MCH BASE-MODULE can be
programmed by the CPU (by appropriate software) or through the BDM port.

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3.3 Backplane Interfaces
The NAT-MCH BASE-Module is equipped with various backplane interfaces, described in
the following sections.
3.3.1 IPMB
The NAT-MCH BASE-Module implements IPMB interfaces which conform to the
MicroTCA specification.
IPMB-L interfaces are available for communication with up to 12 AMCs and a
second NAT-MCH. An IPMB-0 interface is available for communication with CUs
and PMs.
3.3.2 I²C
The NAT-MCH BASE-Module provides an I²C interface to access the dedicated
FRU information device (resided on the backplane).
3.3.3 Ethernet
The NAT-MCH BASE-Module provides 1000BaseX interfaces for fabric A of 12
AMCs and the Update channel of fabric A. These interfaces are connected to a
Broadcom BCM5396 Gigabit Ethernet Switch.
3.4 Front Panel Interfaces
The NAT-MCH BASE-Module is equipped with various interfaces at the front panel,
described in the following sections.
3.4.1 Ethernet Uplink Ports
Two ports of the BCM5396 Gigabit Ethernet Switch are wired to connector GbE1
and GbE2 via a Broadcom BCM5482 1000BaseT physical layer chip. By this
external device the user may access fabric A also from the front panel.
GbE1: The switch interfaces the network to fabric A and to the ColdFire CPU.
Therefore this port can be used to update the ColdFire Software and to permit
communication with external shelf or system managers.
GbE2: Together with GbE1 this port can be used to increase the bandwidth of the
uplink. Instead of the second GbE-Interface the NAT-MCH BASE-Module can be
equipped with a RJ45 clock interface (see chapter 3.4.3.2 for details).
Configuration settings of the BCM5482 are done by CPU ports. It has to be set up
in GBIC mode (1000BaseT to 1000BaseX translation). Like all other I/O devices,
the PHY is resettable via software by programming an FPGA register.

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3.4.2 USB Debug Port
The front panel micro USB connector available on the NAT-MCH BASE-Module is
connected to the USB interface of the ColdFire MCF54452. It provides a console
interface for configuration and monitoring. The USB interface is running in USB
Device Mode. Hardware version 3.4 or higher supports also USB Host Mode (not
for LC version!).
A special USB-to-RS232 adapter cable can be ordered from N.A.T. GmbH.
Connecting this cable to the NAT-MCH USB port (configured to Host Mode) has
the advantage that a terminal connection will not get lost after a “reboot” or
power-cycle.
3.4.3 Clock Interface
The NAT-MCH BASE-Module can be equipped with various External Reference
Clock Transceiver Modules. The available transceiver modules differ in the number
of supported clock signals, in the supported electrical standard (e.g. LVDS, TTL,
CMOS) and the supported connector.
The external clock interfaces are routed from the transceiver module to the CLK-
Module. Therefore the external clock interfaces can only be used in collaboration
with the NAT-MCH CLK-Module.
At the moment the following External Clock Transceiver Modules are available:
3.4.3.1 Coax-IO
The Coax-IO transceiver module supports two SMA connectors at the face plate.
Each connector is connected to its independent amplifier circuit. Each amplifier
circuit can be configured as receiver or transmitter.
Configured as transmitter the output signal coming from the Clock Module FPGA is
transmitted via a simple CMOS driver. This driver is connected to the SMA
connector via AC-coupling.
The amplifier circuit first comes really into operation if configured as receiver. The
receiver part is designed to be able to work with a wide range of input voltages,
as well as signal forms (e.g. sine wave, rectangle).
To be independent of any DC-offset the receiver part is also connected via AC-
coupling.
The main part of the amplifier is a comparator that transfers the input signal from
the SMA connector into a rectangle signal with a peak to peak voltage of 3.3V.
Refer to Table 3: for the electrical characteristics.

NAT-MCH BASE-Module–Technical Reference Manual
Version 2.10 © N.A.T. GmbH 15
The signal mapping for the Coax-IO module can be found below:
Table 2: NAT-MCH BASE-Module –Coax-IO signal mapping
Schematic Name
Script Name
Function Coax-IO
Extref1_p
EXT single ended 1
SMA_1 Rx
Extref1_n
EXT single ended 2
SMA_1 Tx
Extref2_p
EXT single ended 3
SMA_2 Rx
Extref2_n
EXT single ended 4
SMA_2 Tx
Table 3: NAT-MCH BASE-Module –Coax-IO Electrical characteristics
Parameter
Min.
Typ.
Max.
Unit
Input Voltage peak to peak
0.3
5
V
Output Voltage peak to peak
(with 50 Ohm sink termination)
1
V
Input Frequency
1
50M
Hz
Output Frequency
250
125M
Hz
Termination Resistance
50
Ω
3.4.3.2 RJ45-Clock-Interface
Instead of the second GbE-Port the NAT-MCH BASE-Module can be assembled
with a second RJ45 connector usable as RJ45-Clock-Interface.
CAUTION:
The second GbE-Interface is not available with this assembly option! The pin
assignment of the RJ45-Clock-Interface differs from the GbE-Interface! For
detailed information please refer to chapter 4.2.11.
The signals are directly connected to LVDS compliant I/Os of the clock module
FPGA. To prevent the unit from damage, only signals complying with the LVDS
signal standard may be applied to this interface!
Other External Reference Clock Transceiver Modules
Please contact N.A.T. GmbH if the available Clock transceiver modules or any
parameter does not satisfy the needs for your application.
3.5 Interface to Extension Modules
3.5.1 NAT-MCH CKL-Module / NAT-MCH CLK-PHYS-Module
The NAT-MCH CLK-Module / NAT-MCH CLK-PHYS-Module can be accessed by
the ColdFire MCF54452 via I²C bus.
To interface the NAT-MCH HUB-Module, a SPI interface is also available. The
SPI interface of the ColdFire is used for this purpose.
3.5.2 NAT-MCH HUB-Module
The NAT-MCH HUB-Module is connected to the NAT-MCH BASE-Module over
the same connector that connects the NAT-MCH CLK-Module / NAT-MCH CLK-

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PHYS-Module. The NAT-MCH HUB-Module can also be accessed by the
ColdFire via I²C bus.
To interface the NAT-MCH HUB-Module, a SPI interface is also available. The
SPI interface of the ColdFire is used for this purpose.
To have a high-speed interface to the NAT-MCH HUB-Module a 1000Base-X
interface is connected used. At the moment this interface is only supported by the
NAT-MCH XAUI-Module.
3.6 I2C Devices
There are three I2C Devices on the NAT-MCH BASE-Module, which are connected to the
MCF54452 via I2C bus
An EEPROM (24C08) used for storage of board-specific information (address 0x50)
Two temperature sensors (LM75), which sense the board temperature near CPU
and near FPGA (addresses 0x9C and 0x9E)
3.7 Ethernet Switch
The Broadcom BCM5396 Gigabit Ethernet Switch provides a layer 2, non-blocking, low-
latency Gigabit Ethernet switch, supporting VPN as well as a port based rate control. The
BCM5396 supports Fabric A switching according to MicroTCA.0 R1.0 and PICMG SFP.1
R1.0, serving up to 12 AMCs as well as the update channel from the second NAT-MCH in
redundant environments. Also supported are two uplink ports at the front panel of the
NAT-MCH BASE-Module in order to interconnect to other carriers, shelves or systems.
Refer to section 3.4.1 for the Uplink ports.
The configuration register of the BMC5396 can be accessed through the MCF54452’s PHY
message channel interface.
For frame management the BMC5396 is connected to the MCF54452’s TSEC0 through the
MII interface.

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4Hardware
4.1 Front Panel and LEDs
The following figure shows the front panel of the NAT-MCH BASE-Module. It is
equipped with various LEDs.
NAT-MCH BASE-Module –Front PanelFigure 3:
SMA1SMA2
Status
Fault
Hot Swap LED
Hot Swap
Handle
NAT-MCH HUB-Module Uplink- Connector (optional)
4.1.1 MCH Basic-LEDs
The Status-LED indicates the operation status of the NAT-MCH BASE-
Module. If the LED is green, the NAT-MCH BASE-Module operates as
primary MCH in the MicroTCA-system, if the LED shines orange, it is
operating as secondary MCH
The Fault-LED indicates a malfunction of the NAT-MCH BASE-Module
The Hot-Swap-LED indicates the Hot-Swap-Status of the NAT-MCH BASE-
Module
4.1.2 RJ45-LEDs
Two RJ45-LEDs are integrated in each RJ45-connector to indicate GbE-Status.
4.1.3 Status LEDs
Various Status-LEDs residing on the front panel (mounted on the LED-
Module) indicate the status of 12 AMCs, 2 CUs and 2 PMs
The LNK-LEDS indicate the Link-Status of an optionally mountable NAT-MCH
HUB-Module

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4.2 Connectors and Switches
NAT-MCH BASE-Module –Connectors –OverviewFigure 4:
Please refer to the following tables to look up the connector and switch pin assignment of
the NAT-MCH BASE-Module.

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Version 2.10 © N.A.T. GmbH 19
4.2.1 CON1: MCH Connector
Table 4: CON1: MCH Connector –Pin-Assignment
Pin #
AMC-Signal
AMC-Signal
Pin #
1
GND
PWR_ON
170
2
PWR
NC
169
3
/PS1
NC
168
4
MP
NC
167
5
GA0
NC
166
6
RESVD
NC
165
7
GND
GND
164
8
RESVD
TxFA-1+
163
9
PWR
TxFA-1-
162
10
GND
GND
161
11
TxFUA+
RxFA-1+
160
12
TxFUA-
RxFA-1-
159
13
GND
GND
158
14
RxFUA+
TxFA-2+
157
15
RxFUA-
TxFA-2-
156
16
GND
GND
155
17
GA1
RxFA-2+
154
18
PWR
RxFA-2-
153
19
GND
GND
152
20
TxFA-3+
TxFA-4+
151
21
TxFA-3-
TxFA-4-
150
22
GND
GND
149
23
RxFA-3+
RxFA-4+
148
24
RxFA-3-
RxFA-4-
147
25
GND
GND
146
26
GA2
TxFA-6+
145
27
PWR
TxFA-6-
144
28
GND
GND
143
29
TxFA-5+
RxFA-6+
142
30
TxFA-5-
RxFA-6-
141
31
GND
GND
140
32
RxFA-5+
TxFA-8+
139
33
RxFA-5-
TxFA-8-
138
34
GND
GND
137
35
TxFA-7+
RxFA-8+
136
36
TxFA-7-
RxFA-8-
135
37
GND
GND
134
38
RxFA-7+
/TMREQ
133
39
RxFA-7-
RSVD
132
40
GND
GND
131
41
/ENABLE
I2C_SCL
130
42
PWR
I2C_SDA
129
43
GND
GND
128
44
TxFA-9+
IPMB0-SCL-A
127

NAT-MCH BASE-Module–Technical Reference Manual
Version 2.10 © N.A.T. GmbH 20
Pin #
AMC-Signal
AMC-Signal
Pin #
45
TxFA-9-
IPMB0-SDA-A
126
46
GND
GND
125
47
RxFA-9+
IPMB0-SCL-B
124
48
RxFA-9-
IPMB0-SDA-B
123
49
GND
GND
122
50
TxFA-10+
IPMBL-SCL-1
121
51
TxFA-10-
IPMBL-SDA-1
120
52
GND
GND
119
53
RxFA-10+
IPMBL-SCL-2
118
54
RxFA-10-
IPMBL-SDA-2
117
55
GND
GND
116
56
SCL_L
IPMBL-SCL-3
115
57
PWR
IPMBL-SDA-3
114
58
GND
GND
113
59
TxFA-11+
IPMBL-SCL-4
112
60
TxFA-11-
IPMBL-SDA-4
111
61
GND
GND
110
62
RxFA-11+
IPMBL-SCL-5
109
63
RxFA-11-
IPMBL-SDA-5
108
64
GND
GND
107
65
TxFA-12+
IPMBL-SCL-6
106
66
TxFA-12-
IPMBL-SDA-6
105
67
GND
GND
104
68
RxFA-12+
IPMBL-SCL-7
103
69
RxFA-12-
IPMBL-SDA-7
102
70
GND
GND
101
71
SDA_L
IPMBL-SCL-8
100
72
PWR
IPMBL-SDA-8
99
73
GND
GND
98
74
XOVER0+
IPMBL-SCL-9
97
75
XOVER0-
IPMBL-SDA-9
96
76
GND
GND
95
77
XOVER1+
IPMBL-SCL-10
94
78
XOVER1-
IPMBL-SDA-10
93
79
GND
GND
92
80
XOVER2+
IPMBL-SCL-11
91
81
XOVER2-
IPMBL-SDA-11
90
82
GND
GND
89
83
/PS0
IPMBL-SCL-12
88
84
PWR
IPMBL-SDA-12
87
85
GND
GND
86