National Instruments PXIe-6569 User manual

PXIe-6569
Getting
Started Guide
2023-09-11

Contents
Getting Started Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ni.com
2
PXIe-6569 Getting Started Guide

Getting Started Guide
Note Before you begin, install and configure your chassis and controller.
This document explains how to install, configure, test, and use the PXIe-6569. You
can program the PXIe-6569 with the following soware options.
■NI-FlexRIO driver soware
■NI LabVIEW Instrument Design Libraries for FlexRIO (instrument design
libraries)
Note Adapter modules are not installable or interchangeable on the
PXIe-6569 device.
The PXIe-6569 is available in the following fixed LVDS configurations:
■ PXIe-6569 with 32 LVDS In, 32 LVDS Out
■ PXIe-6569 with 64 LVDS In
■ PXIe-6569 with 64 LVDS Out
Note In this document, all variants are referred to inclusively as the
PXIe-6569.
FlexRIO Documentation and Resources
Use the following resources to find more information about the PXIe-6569.
All documentation can be found at ni.com/manuals or in LabVIEW by clicking Help.
© National Instruments 3
PXIe-6569 Getting Started Guide

Table 1. FlexRIO Documentation and Resources
Document Contents
PXIe-6569 Getting Started Guide (this
document) ■Installation instructions
■Basic programming information
PXIe-6569 Specifications ■Operating environment requirements
■DIO specifications
■Clocking specifications
■Physical and mechanical specifications
PXIe-6569 Safety, Environmental, and
Regulatory Information ■Safety and compliance information
■Environmental information
LabVIEW FPGA Module Help ■Basic functionality of the FPGA module
■Instructions for developing and
debugging custom hardware logic
FlexRIO 21.7 Readme ■Minimum system requirements
■Supported Application Development
Environments (ADEs)
■Known issues and bug fixes
■Recent updates
FlexRIO Help ■FlexRIO driver API and programming
information
■I/O Component Level IP (CLIP)
development information
LabVIEW Examples ■Examples showing how to run FPGA VIs
on your device
■Examples showing how to run host VIs
on your device
ni.com
4
PXIe-6569 Getting Started Guide

Unpacking the Kit
Notice To prevent electrostatic discharge (ESD) from damaging the
module, ground yourself using a grounding strap or by holding a grounded
object, such as your computer chassis.
1. Touch the antistatic package to a metal part of the computer chassis.
2. Remove the module from the package and inspect it for loose components or
other signs of damage.
Notice Never touch the exposed pins of connectors.
Note Do not install a module if it appears damaged in any way.
3. Unpack any other items and documentation from the kit.
Store the module in the antistatic package when the module is not in use.
What You Need to Get Started
Kit Contents
Verify that the following items are included in the PXIe-6569 kit.
■ PXIe-6569 hardware
■Documentation
■PXIe-6569 Getting Started Guide (this document)
■PXIe-6569 Safety, Environmental, and Regulatory Information
© National Instruments 5
PXIe-6569 Getting Started Guide

Recommended Cables
NI oers two lengths of optional SEARAY™ to SEARAY cables for connecting to the
pins on the front panel. The following table shows the details for each.
Model Name Part Number
SR240M-SR240M Cable, LVDS with SE, 0.5m 787317-0R5
SR240M-SR240M Cable, LVDS with SE, 1.0m 787317-01
Installing the Software
You must be an Administrator to install NI soware on your computer.
1. Install an ADE, such as LabVIEW or LabWindows™/CVI™.
2. Download the driver soware installer from ni.com/downloads.
NI Package Manager downloads with the driver soware to handle the
installation. Refer to the NI Package Manager Manual for more information
about installing, removing, and upgrading NI soware using NI Package
Manager.
3. Follow the instructions in the installation prompts.
Note Windows users may see access and security messages during
installation. Accept the prompts to complete the installation.
4. When the installer completes, select Restart in the dialog box that prompts
you to restart, shut down, or restart later.
Installing FlexRIO Modules
This section contains general installation instructions for installing a FlexRIO
module in a PXI Express chassis. Refer to your chassis user manual for specific
instructions and warnings. To install a module, complete the following steps:
ni.com
6
PXIe-6569 Getting Started Guide

1. Connect the AC power source to the PXI Express chassis before installing the
module. The AC power cord grounds the chassis and protects it from electrical
damage while you install the module.
2. Ensure that the chassis is powered o.
3. Install a module into a chassis slot by first placing the module card PCB into
the front of the card guides (top and bottom), as shown in the following figure.
Slide the module to the rear of the chassis, making sure that the injector/
ejector handle is pushed down, as shown in the following figure.
4. When you begin to feel resistance, push up on the injector/ejector handle to
fully seat the module into the chassis frame. Secure the module front panel to
the chassis using the module front-panel mounting screws.
Figure 1. Installing PXI Express Modules
8899
77
66
55
44
33
22HHHHHHHHHHHHHHHH
11
LOWLOW POWERPOWER
PPXXIIe-1088e-1088
3
2
1
4
5
a. Injector/Ejector Handle
b. FlexRIO Module
c. Front Panel Mounting Screws (2x)
d. PXI Express Chassis
e. Injector/Ejector Rail
© National Instruments 7
PXIe-6569 Getting Started Guide

PXIe-6569 Front Panel and Connectors
The following figure shows the front panel and pin layout of the Digital Data &
Control (DDC) connector on the PXIe-6569.
Figure 2. PXIe-6569 Front Panel Layout
PXIe-6569
DIGITAL DATA & CONTROL
A4
A1
A2
A3
A5
A6
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A7
C4
C1
C2
C3
C5
C6
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C7
C40
F4
F1
F2
F3
F5
F6
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
F7
D4
D1
D2
D3
D5
D6
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D7
B4
B1
B2
B3
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B7
E4
E1
E2
E3
E5
E6
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
E7
The following figures show the pinout of the DDC connector on the PXIe-6569 for
each connector type. Clock-capable pins are denoted in bold.
ni.com
8
PXIe-6569 Getting Started Guide

Figure 3. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows F-E
Bank 46
Bank 46
Connector SignalFPGA Signal Connector Signal FPGA Signal
*
*
aSeGpio(1)
To clocking
circuitry
aDiffGpio_p(46)
aDiffGpio_n(46)
aDiffGpio_p(48)
aDiffGpio_n(48)
aDiffGpio_p(47)
aDiffGpio_n(47)
aDiffGpio_p(51)
aDiffGpio_n(51)
aDiffGpio_p(69)
aDiffGpio_n(69)
aDiffGpio_p(63)
aDiffGpio_n(63)
aDiffGpio_p(56)
aDiffGpio_n(56)
aDiffGpio_p(61)
aDiffGpio_n(61)
aDiffGpio_p(64)
aDiffGpio_n(64)
aDiffGpio_p(66)
aDiffGpio_n(66)
aDiffGpio_p(55)
aDiffGpio_n(55)
*
*
aSeGpio(3)
aDiffGpio_p(58)*
aDiffGpio_n(58)*
aDiffGpio_p(50)
aDiffGpio_n(50)
aDiffGpio_p(49)
aDiffGpio_n(49)
aDiffGpio_p(53)*
aDiffGpio_n(53)*
aDiffGpio_p(67)
aDiffGpio_n(67)
aDiffGpio_p(65)
aDiffGpio_n(65)
aDiffGpio_p(59)
aDiffGpio_n(59)
aDiffGpio_p(57)*
aDiffGpio_n(57)*
aDiffGpio_p(60)
aDiffGpio_n(60)
aDiffGpio_p(62)
aDiffGpio_n(62)
aDiffGpio_p(68)
aDiffGpio_n(68)
E4
E1
E2
E3
E5
E6
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E7
E40
F4
F1
F2
F3
F5
F6
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
F7
GND
GND
SE 1
SE_GND_TERM
DI 10+*
DI 10-*
DI 11+
DI 11-
GND
DI 12+
DI 12-
GND
DI 13+*
DI 13-*
GND
DI 14+
DI 14-
GND
DI 15+
DI 15-
GND
DI 16+
DI 16-
GND
DI 17+*
DI 17-*
GND
DI 18+
DI 18-
GND
DI 19+
DI 19-
GND
DI 20+
DI 20-
GND
RSVD
RSVD
GND
GND
GND
GND
SE 0
SE_GND_TERM
CLK IN+
CLK IN-
DI 0+
DI 0-
GND
DI 1+
DI 1-
GND
DI 2+
DI 2-
GND
DI 3+
DI 3-
GND
DI 4+
DI 4-
GND
DI 5+
DI 5-
GND
DI 6+
DI 6-
GND
DI 7+
DI 7-
GND
DI 8+
DI 8-
GND
DI 9+
DI 9-
GND
PFI 0+
PFI 0-
GND
GND
© National Instruments 9
PXIe-6569 Getting Started Guide

Figure 4. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows D-C
Connector SignalFPGA Signal
GND
GND
SE 6
SE_GND_TERM
SE 7
SE_GND_TERM
DO 21+
DO 21-
GND
DO 22+
DO 22-
GND
DO 23+
DO 23-
GND
DO 24+
DO 24-
GND
DO 25+
DO 25-
GND
DO 26+
DO 26-
GND
DO 27+
DO 27-
GND
DO 28+
DO 28-
GND
DO 29+
DO 29-
GND
DO 30+
DO 30-
GND
DO 31+
DO 31-
GND
GND
D4
D1
D2
D3
D5
D6
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D7
D40
Connector Signal FPGA Signal
aSeGpio(5)
aSeGpio(7)
aDiffGpio_p(0)
aDiffGpio_n(0)
aDiffGpio_p(1)
aDiffGpio_n(1)
aDiffGpio_p(3)
aDiffGpio_n(3)
aDiffGpio_p(5)
aDiffGpio_n(5)
aDiffGpio_p(9)
aDiffGpio_n(9)
aDiffGpio_p(7)
aDiffGpio_n(7)
aDiffGpio_p(2)
aDiffGpio_n(2)
aDiffGpio_p(10)
aDiffGpio_n(10)
aDiffGpio_p(15)*
aDiffGpio_n(15)*
aDiffGpio_p(13)
aDiffGpio_n(13)
aDiffGpio_p(6)
aDiffGpio_n(6)
GND
GND
SE 2
SE_GND_TERM
SE 3
SE_GND_TERM
DI 21+
DI 21-
GND
DI 22+
DI 22-
GND
DI 23+
DI 23-
GND
DI 24+
DI 24-
GND
DI 25+
DI 25-
GND
DI 26+
DI 26-
GND
DI 27+
DI 27-
GND
DI 28+
DI 28-
GND
DI 29+*
DI 29-*
GND
DI 30+
DI 30-
GND
DI 31+
DI 31-
GND
GND
C4
C1
C2
C3
C5
C6
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C7
Bank 45
Bank 45
aSeGpio(13)
aSeGpio(15)
aDiffGpio_p(4)
aDiffGpio_n(4)
aDiffGpio_p(8)
aDiffGpio_n(8)
aDiffGpio_p(12)
aDiffGpio_n(12)
aDiffGpio_p(11)
aDiffGpio_n(11)
aDiffGpio_p(16)
aDiffGpio_n(16)
aDiffGpio_p(14)
aDiffGpio_n(14)
aDiffGpio_p(19)
aDiffGpio_n(19)
aDiffGpio_p(17)
aDiffGpio_n(17)
aDiffGpio_p(21)
aDiffGpio_n(21)
aDiffGpio_p(20)
aDiffGpio_n(20)
aDiffGpio_p(18)
aDiffGpio_n(18)
ni.com
10
PXIe-6569 Getting Started Guide

Figure 5. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows B-A
aSeGpio(11)
aDiffGpio_p(22)
aDiffGpio_n(22)
aDiffGpio_p(26)
aDiffGpio_n(26)
aDiffGpio_p(24)
aDiffGpio_n(24)
aDiffGpio_p(25)
aDiffGpio_n(25)
aDiffGpio_p(27)
aDiffGpio_n(27)
aDiffGpio_p(31)
aDiffGpio_n(31)
aDiffGpio_p(32)
aDiffGpio_n(32)
aDiffGpio_p(40)
aDiffGpio_n(40)
aDiffGpio_p(36)
aDiffGpio_n(36)
aDiffGpio_p(45)
aDiffGpio_n(45)
aDiffGpio_p(39)
aDiffGpio_n(39)
GND
GND
SE 5
SE_GND_TERM
DO 10+
DO 10-
DO 11+
DO 11-
GND
DO 12+
DO 12-
GND
DO 13+
DO 13-
GND
DO 14+
DO 14-
GND
DO 15+
DO 15-
GND
DO 16+
DO 16-
GND
DO 17+
DO 17-
GND
DO 18+
DO 18-
GND
DO 19+
DO 19-
GND
DO 20+
DO 20-
GND
RSVD
RSVD
GND
GND
Connector SignalFPGA Signal
B4
B1
B2
B3
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B7
B40
aSeGpio(9)
From clocking
circuitry
aDiffGpio_p(28)
aDiffGpio_n(28)
aDiffGpio_p(23)
aDiffGpio_n(23)
aDiffGpio_p(29)
aDiffGpio_n(29)
aDiffGpio_p(33)
aDiffGpio_n(33)
aDiffGpio_p(41)
aDiffGpio_n(41)
aDiffGpio_p(38)
aDiffGpio_n(38)
aDiffGpio_p(34)
aDiffGpio_n(34)
aDiffGpio_p(42)
aDiffGpio_n(42)
aDiffGpio_p(30)
aDiffGpio_n(30)
aDiffGpio_p(43)
aDiffGpio_n(43)
aDiffGpio_p(52)
aDiffGpio_n(52)
GND
GND
SE 4
SE_GND_TERM
CLK OUT+
CLK OUT-
DO 0+
DO 0-
GND
DO 1+
DO 1-
GND
DO 2+
DO 2-
GND
DO 3+
DO 3-
GND
DO 4+
DO 4-
GND
DO 5+
DO 5-
GND
DO 6+
DO 6-
GND
DO 7+
DO 7-
GND
DO 8+
DO 8-
GND
DO 9+
DO 9-
GND
PFI 1+
PFI 1-
GND
GND
Connector Signal FPGA Signal
A4
A1
A2
A3
A5
A6
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A7
Bank 44
Bank 44
© National Instruments 11
PXIe-6569 Getting Started Guide

Figure 6. PXIe-6569 with 64 LVDS In, Rows F-E
Bank 46
Bank 46
Connector SignalFPGA Signal Connector Signal FPGA Signal
*
*
aSeGpio(1)
To clocking
circuitry
aDiffGpio_p(46)
aDiffGpio_n(46)
aDiffGpio_p(48)
aDiffGpio_n(48)
aDiffGpio_p(47)
aDiffGpio_n(47)
aDiffGpio_p(51)
aDiffGpio_n(51)
aDiffGpio_p(69)
aDiffGpio_n(69)
aDiffGpio_p(63)
aDiffGpio_n(63)
aDiffGpio_p(56)
aDiffGpio_n(56)
aDiffGpio_p(61)
aDiffGpio_n(61)
aDiffGpio_p(64)
aDiffGpio_n(64)
aDiffGpio_p(66)
aDiffGpio_n(66)
aDiffGpio_p(55)
aDiffGpio_n(55)
aSeGpio(3)
aDiffGpio_p(58)*
aDiffGpio_n(58)*
aDiffGpio_p(50)
aDiffGpio_n(50)
aDiffGpio_p(49)
aDiffGpio_n(49)
aDiffGpio_p(53)*
aDiffGpio_n(53)*
aDiffGpio_p(67)
aDiffGpio_n(67)
aDiffGpio_p(65)
aDiffGpio_n(65)
aDiffGpio_p(59)
aDiffGpio_n(59)
aDiffGpio_p(57)*
aDiffGpio_n(57)*
aDiffGpio_p(60)
aDiffGpio_n(60)
aDiffGpio_p(62)
aDiffGpio_n(62)
aDiffGpio_p(68)
aDiffGpio_n(68)
E4
E1
E2
E3
E5
E6
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E7
E40
F4
F1
F2
F3
F5
F6
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
F7
GND
GND
SE 1
SE_GND_TERM
DI 43+*
DI 43-*
DI 44+
DI 44-
GND
DI 45+
DI 45-
GND
DI 46+*
DI 46-*
GND
DI 47+
DI 47-
GND
DI 48+
DI 48-
GND
DI 49+
DI 49-
GND
DI 50+*
DI 50-*
GND
DI 51+
DI 51-
GND
DI 52+
DI 52-
GND
DI 53+
DI 53-
GND
RSVD
RSVD
GND
GND
CLK IN+
GND
GND
SE 0
SE_GND_TERM
CLK IN-
DI 54+
DI 54-
GND
DI 55+
DI 55-
GND
DI 56+
DI 56-
GND
DI 57+
DI 57-
GND
DI 58+
DI 58-
GND
DI 59+
DI 59-
GND
*
DI 60+
*
DI 60-
GND
DI 61+
DI 61-
GND
DI 62+
DI 62-
GND
DI 63+
DI 63-
GND
PFI 0+
PFI 0-
GND
GND
ni.com
12
PXIe-6569 Getting Started Guide

Figure 7. PXIe-6569 with 64 LVDS In, Rows D-C
Connector SignalFPGA Signal
GND
GND
SE 6
SE_GND_TERM
SE 7
SE_GND_TERM
DI 21+
DI 21-
GND
DI 22+
DI 22-
GND
DI 23+
DI 23-
GND
DI 24+
DI 24-
GND
DI 25+
DI 25-
GND
DI 26+
DI 26-
GND
DI 27+
DI 27-
GND
DI 28+
DI 28-
GND
DI 29+*
DI 29-*
GND
DI 30+
DI 30-
GND
DI 31+
DI 31-
GND
GND
© National Instruments 13
PXIe-6569 Getting Started Guide

Figure 8. PXIe-6569 with 64 LVDS In, Rows B-A
aSeGpio(11)
aDiffGpio_p(22)
aDiffGpio_n(22)
aDiffGpio_p(26)
aDiffGpio_n(26)
aDiffGpio_p(24)
aDiffGpio_n(24)
aDiffGpio_p(25)
aDiffGpio_n(25)
aDiffGpio_p(27)
aDiffGpio_n(27)
aDiffGpio_p(31)
aDiffGpio_n(31)
aDiffGpio_p(32)
aDiffGpio_n(32)
aDiffGpio_p(40)
aDiffGpio_n(40)
aDiffGpio_p(36)
aDiffGpio_n(36)
aDiffGpio_p(45)
aDiffGpio_n(45)
aDiffGpio_p(39)
aDiffGpio_n(39)
Connector SignalFPGA Signal
B4
B1
B2
B3
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
ni.com
14
PXIe-6569 Getting Started Guide

Figure 9. PXIe-6569 with 64 LVDS Out, Rows F-E
Bank 46
Bank 46
Connector SignalFPGA Signal Connector Signal FPGA Signal
aSeGpio(1)
To clocking
circuitry
aDiffGpio_p(46)
aDiffGpio_n(46)
aDiffGpio_p(48)
aDiffGpio_n(48)
aDiffGpio_p(47)
aDiffGpio_n(47)
aDiffGpio_p(51)
aDiffGpio_n(51)
aDiffGpio_p(69)
aDiffGpio_n(69)
aDiffGpio_p(63)
aDiffGpio_n(63)
aDiffGpio_p(56)
aDiffGpio_n(56)
aDiffGpio_p(61)
aDiffGpio_n(61)
aDiffGpio_p(64)
aDiffGpio_n(64)
aDiffGpio_p(66)
aDiffGpio_n(66)
aDiffGpio_p(55)
aDiffGpio_n(55)
aSeGpio(3)
aDiffGpio_p(58)
aDiffGpio_n(58)
aDiffGpio_p(50)
aDiffGpio_n(50)
aDiffGpio_p(49)
aDiffGpio_n(49)
aDiffGpio_p(53)
aDiffGpio_n(53)
aDiffGpio_p(67)
aDiffGpio_n(67)
aDiffGpio_p(65)
aDiffGpio_n(65)
aDiffGpio_p(59)
aDiffGpio_n(59)
aDiffGpio_p(57)
aDiffGpio_n(57)
aDiffGpio_p(60)
aDiffGpio_n(60)
aDiffGpio_p(62)
aDiffGpio_n(62)
aDiffGpio_p(68)
aDiffGpio_n(68)
E4
E1
E2
E3
E5
E6
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E7
E40
F4
F1
F2
F3
F5
F6
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
F7
GND
GND
SE 1
SE_GND_TERM
DO 43+
DO 43-
DO 44+
DO 44-
GND
DO 45+
DO 45-
GND
DO 46+
DO 46-
GND
DO 47+
DO 47-
GND
DO 48+
DO 48-
GND
DO 49+
DO 49-
GND
DO 50+
DO 50-
GND
DO 51+
DO 51-
GND
DO 52+
DO 52-
GND
DO 53+
DO 53-
GND
RSVD
RSVD
GND
GND
CLK IN+
GND
GND
SE 0
SE_GND_TERM
CLK IN-
DO 54+
DO 54-
GND
DO 55+
DO 55-
GND
DO 56+
DO 56-
GND
DO 57+
DO 57-
GND
DO 58+
DO 58-
GND
DO 59+
DO 59-
GND
DO 60+
DO 60-
GND
DO 61+
DO 61-
GND
DO 62+
DO 62-
GND
DO 63+
DO 63-
GND
PFI 0+
PFI 0-
GND
GND
© National Instruments 15
PXIe-6569 Getting Started Guide

Figure 10. PXIe-6569 with 64 LVDS Out, Rows D-C
Connector SignalFPGA Signal
GND
GND
SE 6
SE_GND_TERM
SE 7
SE_GND_TERM
DO 21+
DO 21-
GND
DO 22+
DO 22-
GND
DO 23+
DO 23-
GND
DO 24+
DO 24-
GND
DO 25+
DO 25-
GND
DO 26+
DO 26-
GND
DO 27+
DO 27-
GND
DO 28+
DO 28-
GND
DO 29+
DO 29-
GND
DO 30+
DO 30-
GND
DO 31+
DO 31-
GND
GND
D4
D1
D2
D3
D5
D6
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D7
D40
Connector Signal FPGA Signal
aSeGpio(5)
aSeGpio(7)
aDiffGpio_p(0)
aDiffGpio_n(0)
aDiffGpio_p(1)
aDiffGpio_n(1)
aDiffGpio_p(3)
aDiffGpio_n(3)
aDiffGpio_p(5)
aDiffGpio_n(5)
aDiffGpio_p(9)
aDiffGpio_n(9)
aDiffGpio_p(7)
aDiffGpio_n(7)
aDiffGpio_p(2)
aDiffGpio_n(2)
aDiffGpio_p(10)
aDiffGpio_n(10)
aDiffGpio_p(15)
aDiffGpio_n(15)
aDiffGpio_p(13)
aDiffGpio_n(13)
aDiffGpio_p(6)
aDiffGpio_n(6)
C4
C1
C2
C3
C5
C6
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C7
Bank 45
Bank 45
aSeGpio(13)
aSeGpio(15)
aDiffGpio_p(4)
aDiffGpio_n(4)
aDiffGpio_p(8)
aDiffGpio_n(8)
aDiffGpio_p(12)
aDiffGpio_n(12)
aDiffGpio_p(11)
aDiffGpio_n(11)
aDiffGpio_p(16)
aDiffGpio_n(16)
aDiffGpio_p(14)
aDiffGpio_n(14)
aDiffGpio_p(19)
aDiffGpio_n(19)
aDiffGpio_p(17)
aDiffGpio_n(17)
aDiffGpio_p(21)
aDiffGpio_n(21)
aDiffGpio_p(20)
aDiffGpio_n(20)
aDiffGpio_p(18)
aDiffGpio_n(18)
GND
GND
SE 2
SE_GND_TERM
SE 3
SE_GND_TERM
DO 32+
DO 32-
GND
DO 33+
DO 33-
GND
DO 34+
DO 34-
GND
DO 35+
DO 35-
GND
DO 36+
DO 36-
GND
DO 37+
DO 37-
GND
DO 38+
DO 38-
GND
DO 39+
DO 39-
GND
DO 40+
DO 40-
GND
DO 41+
DO 41-
GND
DO 42+
DO 42-
GND
GND
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16
PXIe-6569 Getting Started Guide

Figure 11. PXIe-6569 with 64 LVDS Out, Rows B-A
aSeGpio(11)
aDiffGpio_p(22)
aDiffGpio_n(22)
aDiffGpio_p(26)
aDiffGpio_n(26)
aDiffGpio_p(24)
aDiffGpio_n(24)
aDiffGpio_p(25)
aDiffGpio_n(25)
aDiffGpio_p(27)
aDiffGpio_n(27)
aDiffGpio_p(31)
aDiffGpio_n(31)
aDiffGpio_p(32)
aDiffGpio_n(32)
aDiffGpio_p(40)
aDiffGpio_n(40)
aDiffGpio_p(36)
aDiffGpio_n(36)
aDiffGpio_p(45)
aDiffGpio_n(45)
aDiffGpio_p(39)
aDiffGpio_n(39)
Connector SignalFPGA Signal
B4
B1
B2
B3
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B7
B40
GND
GND
SE 4
SE_GND_TERM
CLK OUT+
CLK OUT-
DO 0+
DO 0-
GND
DO 1+
DO 1-
GND
DO 2+
DO 2-
GND
DO 3+
DO 3-
GND
DO 4+
DO 4-
GND
DO 5+
DO 5-
GND
DO 6+
DO 6-
GND
DO 7+
DO 7-
GND
DO 8+
DO 8-
GND
DO 9+
DO 9-
GND
PFI 1+
PFI 1-
GND
GND
Connector Signal FPGA Signal
A4
A1
A2
A3
A5
A6
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A7
Bank 44
Bank 44
GND
GND
SE 5
SE_GND_TERM
DO 10+
DO 10-
DO 11+
DO 11-
GND
DO 12+
DO 12-
GND
DO 13+
DO 13-
GND
DO 14+
DO 14-
GND
DO 15+
DO 15-
GND
DO 16+
DO 16-
GND
DO 17+
DO 17-
GND
DO 18+
DO 18-
GND
DO 19+
DO 19-
GND
DO 20+
DO 20-
GND
RSVD
RSVD
GND
GND
aSeGpio(9)
From clocking
circuitry
aDiffGpio_p(28)
aDiffGpio_n(28)
aDiffGpio_p(23)
aDiffGpio_n(23)
aDiffGpio_p(29)
aDiffGpio_n(29)
aDiffGpio_p(33)
aDiffGpio_n(33)
aDiffGpio_p(41)
aDiffGpio_n(41)
aDiffGpio_p(38)
aDiffGpio_n(38)
aDiffGpio_p(34)
aDiffGpio_n(34)
aDiffGpio_p(42)
aDiffGpio_n(42)
aDiffGpio_p(30)
aDiffGpio_n(30)
aDiffGpio_p(43)
aDiffGpio_n(43)
aDiffGpio_p(52)
aDiffGpio_n(52)
Signal Descriptions
The following table describes the signal connections for the PXIe-6569.
Connector Name Signal Type Description
DO <0...63>+/- Data Positive and negative
dierential terminals for digital
output channels 0 through 63.
DI <0...63>+/- Data Positive and negative
dierential terminals for digital
input channels 0 through 63.
© National Instruments 17
PXIe-6569 Getting Started Guide

Connector Name Signal Type Description
PFI <0,1>+/- Control Positive and negative
dierential terminals for
bidirectional PFI channels 0
and 1.
SE <0...7> Data Terminals for bidirectional
single-ended channels 0
through 7.
SE_GND_TERM Termination Terminals that provide
coupling to the single-ended
channels. These signals should
be terminated for the best
single-ended signal integrity.
These are terminated on the
PXIe-6569 with 56 Ω to ground.
NI recommends that these also
be terminated on the user side
of the SEARAY cable through a
56 Ω (±10%) resistor to GND. If
the user-side termination is not
possible, leave it disconnected.
CLKIN+/-,
CLKOUT+/-
Clock Terminals for clocking inputs
and outputs.
GND Ground Ground reference for signals.
RSVD Reserved These pins are reserved and
use of them is not supported
by NI. Leave these terminals
disconnected.
Verifying the Installation in MAX
Use Measurement & Automation Explorer (MAX) to configure your NI hardware. MAX
informs other programs about which NI hardware products are in the system and
how they are configured. MAX is automatically installed with FlexRIO.
1. Launch MAX.
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PXIe-6569 Getting Started Guide

2. In the configuration tree, expand Devices and Interfaces to see the list of
installed NI hardware.
Installed modules appear under the name of their associated chassis.
3. Expand your Chassis tree item.
MAX lists all modules installed in the chassis. Your default names may vary.
Note Device Manager identifies the PXIe-6569 as the "NI FlexRIO
Module (BT - KU035)" or "NI FlexRIO Module (BT - KU060)".
Note If you do not see your module listed, press <F5> to refresh the
list of installed modules. If the module is still not listed, power o the
system, ensure the module is correctly installed, and restart.
4. Record the identifier MAX assigns to the hardware. Use this identifier when
programming the PXIe-6569.
5. Self-test the hardware by selecting the item in the configuration tree and
clicking Self-Test in the MAX toolbar.
MAX self-test performs a basic verification of hardware resources.
Accessing FlexRIO with Integrated I/O Examples
The FlexRIO driver includes several example applications for LabVIEW. These
examples serve as interactive tools, programming models, and as building blocks
in your own applications. To access all FlexRIO with Integrated I/O getting started
examples, complete the following steps.
1. In LabVIEW, click Help » Find Examples.
2. In the NI Example Finder window that opens, click Hardware Input and
Output » FlexRIO » Integrated IO » Getting Started.
3. Double click Getting Started with FlexRIO Integrated IO.vi.
The FlexRIO with Integrated IO Project Creator window opens.
4. Select the example that corresponds to the name of your FlexRIO module.
The Description window includes a short description of the getting started
© National Instruments 19
PXIe-6569 Getting Started Guide

example for your device. Rename the project, select a location for the project,
and click OK.
The Project Explorer window for your new project opens.
Online examples are also available to demonstrate FlexRIO basics, such as using
DRAM, acquiring data, and performing high throughput streaming. To access these
examples, search FlexRIO examples in the Search the community field at ni.com/
examples.
PXIe-6569 Examples
Examples specific to PXIe-6569 can be found in the FlexRIO with Integrated IO
Project Creator.
NI provides two getting started examples for each LVDS and FPGA configuration of
the PXIe-6569: a basic interface and a SERDES interface. The following file names
and descriptions demonstrate how the examples would be displayed to a user
whose module includes a 32 LVDS In, 32 LVDS Out variation and a KU035 FPGA:
■ PXIe-6569 (32 In 32 Out - KU035) - Basic Interface.vi demonstrates device
configuration and generation/acquisition of digital data using a one sample
per cycle interface.
■ PXIe-6569 (32 In 32 Out - KU035) - SerDes Interface.vi demonstrates device
configuration and generation/acquisition of digital data using an eight sample
per cycle interface.
Common FlexRIO with Integrated I/O Examples
In addition to the examples within the FlexRIO with Integrated IO Project Creator, NI
provides several examples that apply to all FlexRIO with Integrated I/O modules to
help you perform common tasks.
The following table lists FlexRIO examples you can run from NI Example Finder:
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20
PXIe-6569 Getting Started Guide