National Instruments NI 5412 User manual

NI 5412 Specifications
NI PXI/PCI-5412 14-Bit 100 MS/s Arbitrary Waveform Generator
Unless otherwise noted, the following conditions were used for each
specification:
• Interpolation set to maximum allowed factor for a given sample rate.
• Signals terminated with 50 Ω.
• Low-Gain Amplifier Path set to 2 Vpk-pk, and High-Gain Amplifier
Path set to 12 Vpk-pk.
• Sample clock set to 100 MS/s.
Typical values are representative of an average unit operating at room
temperature. Specifications are subject to change without notice. For the
most recent NI 5412 specifications, visit ni.com/manuals.
To access all the NI 5412 documentation, including the NI Signal
Generators Getting Started Guide, which contains functional descriptions
of the NI 5412 signals, navigate to Start»Programs»National
Instruments»NI-FGEN»Documentation.
Caution Hot Surface Allow the NI 5412 to cool before removing it from the chassis to reduce
risk of burns. Use caution when handling because recently used NI 5412 devices may
exceed safe handling temperatures.
Contents
CH 0 ........................................................................................................ 2
Sample Clock .......................................................................................... 7
Onboard Clock ........................................................................................ 10
Phase-Locked Loop (PLL) Reference Clock .......................................... 10
CLK IN ................................................................................................... 11
PFI 0 and PFI 1 ....................................................................................... 12
Start Trigger ............................................................................................ 13
Markers ................................................................................................... 15
Waveform and Instruction Memory Utilization...................................... 16
Calibration............................................................................................... 18
Power ...................................................................................................... 18
Software .................................................................................................. 19
Environment............................................................................................ 20
Safety, Electromagnetic Compatibility, and CE Compliance................. 22
Physical ................................................................................................... 24
Where to Go for Support......................................................................... 25

NI 5412 Specifications 2 ni.com
CH 0
(Channel 0 Analog Output, Front Panel Connector)
Table 1.
Specification Value Comments
Number of
Channels
1 —
Connector SMB (jack) —
Output Voltage Characteristics
Output Paths The software-selectable Main Output Path setting provides
full-scale voltages from 12.00 Vpk-pk to 5.64 mVpk-pk into a
50 Ω load. NI-FGEN uses either the Low-Gain Amplifier or
the High-Gain Amplifier when the Main Output Path is
selected, depending on the Gain attribute.
—
DAC
Resolution
14 bits —
Amplitude and Offset
Amplitude
Range
Path Load
Amplitude (Vpk-pk)1. Amplitude
values assume
the full scale
of the DAC is
utilized. If an
amplitude
smaller than
the minimum
value is
desired, then
waveforms less
than full scale
of the DAC can
be used.
Minimum Value Maximum Value
Low-
Gain
Amplifier
50 Ω0.00564 2.00
1 kΩ0.0107 3.81
Open 0.0113 4.00
High-
Gain
Amplifier
50 Ω0.0338 12.0
1 kΩ0.0644 22.9
Open 0.0676 24.0
Amplitude
Resolution
3 digits —
Offset Range Span of ±25% of Amplitude Range with increments
<0.0014% of Amplitude Range.
—

©National Instruments Corporation 3 NI 5412 Specifications
Maximum Output Voltage
Maximum
Output
Vo l t a g e
Path Load Maximum Output Voltage (Vpk-pk)The Maximum
Output Voltage
of the NI 5412 is
determined by
the Amplitude
Range and the
Offset Range.
Low-
Gain
Amplifier
50 Ω±1.000
1 kΩ±1.905
Open ±2.000
High-
Gain
Amplifier
50 Ω±6.000
1 kΩ±11.43
Open ±12.00
Accuracy
DC Accuracy ±0.2% of Amplitude ± 0.05% of Offset ± 500 µV
(within ±10 °C of self-calibration temperature)
±0.4% of Amplitude ± 0.05% of Offset ± 1 mV
(0 °C to 55 °C)
Calibrated for
high impedance
load.
AC Amplitude
Accuracy
±1.0% of desired Amplitude ± 1 mV 50 kHz sine
wave.
Output Characteristics
Output
Impedance
50 Ωor 75 Ωnominal, software-selectable. —
Output
Coupling
DC —
Output Enable Software-selectable. When the Output Path is disabled, the
CH 0 Output is terminated to ground with a 1 W resistor
equal to the selected output impedance.
—
Maximum
Output
Overload
The CH 0 output can be connected to a 50 Ω, ±12 V source
without sustaining any damage. No damage occurs if the
CH 0 output is shorted to ground indefinitely.
—
Waveform
Summing
The CH 0 output supports waveform summing among
similar paths—specifically, the outputs of multiple NI 5412
signal generators can be connected directly together.
—
Table 1. (Continued)
Specification Value Comments

NI 5412 Specifications 4 ni.com
Frequency and Transient Response
Bandwidth 20 MHz –3 dB
Digital
Interpolation
Filter
Software-selectable Finite Impulse Response (FIR) filter.
Available interpolation factors are 2, 4, or 8.
—
Passband
Flatness
Low-Gain and High-Gain Amplifiers Path —
±1.0 dB from DC to 6 MHz
Pulse
Response
Path All values are
typical.
Measured with a
1 m RG-223
cable.
Low-Gain Amplifier High-Gain Amplifier
Rise/Fall Time <20 ns <20 ns
Aberration <5% <5%
Table 1. (Continued)
Specification Value Comments

©National Instruments Corporation 5 NI 5412 Specifications
Figure 1. Pulse Response, Low-Gain Amplifier Path 50 ΩLoad
–2.0
–1.6
–0.4
–1.2
0.0
–0.8
0.4
0.8
1.2
1.6
2.0
0 0.2 0.4 0.6 0.8 1.0
Time (µs)
Amplitude (V)

NI 5412 Specifications 6 ni.com
Table 1. (Continued)
Specification Value Comments
Suggested Maximum Frequencies for Common Functions
Function Path —
Low-Gain Amplifier High-Gain Amplifier
Sine 20 MHz 20 MHz
Square 5 MHz 5 MHz
Ramp 1 MHz 1 MHz
Triangle 1 MHz 1 MHz
Spectral Characteristics
Spurious-Free
Dynamic
Range
(SFDR)
without
Harmonics
Path Amplitude
–1 dBFS.
Measured from
DC to 50 MHz.
SFDR without
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor. All
values are
typical.
Low-Gain Amplifier High-Gain Amplifier
1 MHz –70 dBc –70 dBc
10 MHz –65 dBc –65 dBc
20 MHz –60 dBc –60 dBc
0 ºC to 40 ºC
Total
Harmonic
Distortion
(THD)
Path Amplitude
–1 dBFS.
Includes the 2nd
through the 6th
harmonic. All
values are
typical.
Low-Gain Amplifier High-Gain Amplifier
1 MHz –59 dBc –51 dBc
10 MHz –52 dBc –40 dBc
20 MHz –45 dBc –37 dBc

©National Instruments Corporation 7 NI 5412 Specifications
Sample Clock
Spectral Characteristics (Continued)
Average Noise
Density
Path
Amplitude
Range Average Noise Density
Average Noise
Density at small
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
Vpk-pk dBm dBm/Hz
dBFS/
Hz
Low-Gain 210 45 –134 –144
High-
Gain
12 25.6 251 –119 –145
Table 2.
Specification Value Comments
Sources 1. Internal, Divide-by-N(N≥1)
2. Internal, DDS-based, High-Resolution
3. External, CLK IN (SMB front panel connector)
4. NI PXI-5412: External, PXI Star trigger
(backplane connector)
5. NI PXI-5412: External, PXI_Trig<0..7>
(backplane connector)
NI PCI-5412: External, RTSI<0..7>
Refer to the
Onboard Clock
section for more
information
about Internal
Clock Sources.
Table 1. (Continued)
Specification Value Comments
nV
Hz
-----------

NI 5412 Specifications 8 ni.com
Sample Rate Range and Resolution
Sample Clock
Source Sample Rate Range Sample Rate Resolution
—
Divide-by-N23.84 S/s to 100 MS/s Settable to (100 MS/s) / N
(1 ≤N≤4,194,304)
High-
Resolution
10 S/s to 100 MS/s 1.06 µHz
CLK IN 200 kS/s to 105 MS/s Resolution determined by
external clock source.
External Sample Clock duty
cycle tolerance 40% to 60%.
NI PXI-5412
PXI Star
Trigger
10 S/s to 105 MS/s
NI PXI-5412
PXI_Trig<0..7>
10 S/s to 20 MS/s
NI PCI-5412
RTSI<0..7>
10 S/s to 20 MS/s
Effective Sample Rate
Sample Rate
(MS/s)
Interpolation
Factor
Effective Sample
Rate
Effective Sample
Rate =
(Interpolation
Factor) * (Sample
Rate)
10 S/s to
105 MS/s
1 (Off) 10 S/s to
105 MS/s
12.5 MS/s to
105 MS/s
225 MS/s to
210 MS/s
10 MS/s to
100 MS/s
440 MS/s to
400 MS/s
10 MS/s to
50 MS/s
880 MS/s to
400 MS/s
Sample Clock Delay Range and Resolution
Sample Clock
Source Delay Adjustment Range
Delay Adjustment
Resolution
—
Divide-by-N±1 sample clock period <10 ps
High-
Resolution
±1 sample clock period Sample Clock
Period/16,384
Table 2. (Continued)
Specification Value Comments

©National Instruments Corporation 9 NI 5412 Specifications
System Phase Noise and Jitter (10 MHz Carrier)
Sample Clock
Source
System Phase Noise
Density
(dBc/Hz) Offset System Output Jitter
(Integrated from
100 Hz to 100 kHz)
1. High-
Resolution
specifications
vary with
Sample Rate.
2. All values are
typical.
100 Hz 1 kHz 10 kHz
NI PXI-5412 –100 –118 –120 <6 ps rms
NI PCI-5412 –90 –110 –120 <7 ps rms
External
Sample Clock
Input Jitter
Tolerance
Cycle-Cycle Jitter ±300 ps
Period Jitter ±1 ns
—
Sample Clock Exporting
Exported
Sample Clock
Destinations
1. PFI<0..1> (SMB front panel connectors)
2. NI PXI-5412: PXI_Trig<0..6> (backplane connector)
NI PCI-5412: RTSI<0..6>
Exported Sample
Clocks can be
divided by integer
K(1 ≤K≤
4,194,304).
Exported
Sample Clock
Destinations Maximum Frequency Duty Cycle
—
PFI<0..1> 105 MHz 25% to 65%
NI PXI-5412
PXI_Trig<0..6>
20 MHz —
NI PCI-5412
RTSI<0..6>
20 MHz —
Table 2. (Continued)
Specification Value Comments

NI 5412 Specifications 10 ni.com
Onboard Clock
(Internal VCXO)
Phase-Locked Loop (PLL) Reference Clock
Table 3.
Specification Value Comments
Clock Source Internal sample clocks can either be locked to a Reference
Clock using a phase-locked loop or be derived from the
onboard VCXO frequency reference.
—
Frequency
Accuracy
±25 ppm —
Table 4.
Specification Value Comments
Sources 1. NI PXI-5412—PXI_CLK10 (backplane connector)
NI PCI-5412—RTSI_7 (RTSI_CLK)
2. CLK IN (SMB front panel connector)
The PLL
Reference Clock
provides the
reference
frequency for the
phase-locked
loop.
Frequency
Accuracy
When using the PLL, the Frequency Accuracy of the
NI 5412 is solely dependent on the Frequency Accuracy
of the PLL Reference Clock Source.
—
Lock Time ≤200 ms. —
Frequency
Range
5 MHz to 20 MHz in increments of 1 MHz.
Default of 10 MHz.
The PLL Reference Clock Frequency has to be accurate
to ±50 ppm.
—
Duty Cycle
Range
40% to 60% —
Exported PLL
Reference
Clock
Destinations
1. PFI<0..1> (SMB front panel connectors)
2. NI PXI-5412—PXI_Trig<0..6> (backplane connector)
NI PCI-5412—RTSI<0..6>
—

©National Instruments Corporation 11 NI 5412 Specifications
CLK IN
(Sample Clock and Reference Clock Input, Front Panel Connector)
Table 5.
Specification Value Comments
Connector SMB (jack) —
Direction Input —
Destinations 1. Sample Clock
2. PLL Reference Clock
—
Frequency
Range
1 MHz to 105 MHz (Sample Clock destination and
sine waves)
200 kHz to 105 MHz (Sample Clock destination and
square waves)
5 MHz to 20 MHz (PLL Reference Clock destination)
—
Input Voltage
Range
Sine wave: 0.65 Vpk-pk to 2.8 Vpk-pk into 50 Ω
(0 dBm to +13 dBm)
Square wave: 0.2 Vpk-pk to 2.8 Vpk-pk into 50 Ω
—
Maximum
Input Overload
±10 V —
Input
Impedance
50 Ω—
Input Coupling AC —

NI 5412 Specifications 12 ni.com
PFI 0 and PFI 1
(Programmable Function Interface, Front Panel Connectors)
Table 6.
Specification Value Comments
Connectors Two SMB (jack) —
Direction Bi-directional —
Frequency
Range
DC to 105 MHz —
As an Input (Trigger)
Destinations Start Trigger —
Maximum
Input Overload
–2 V to +7 V —
VIH 2.0 V
VIL 0.8 V
Input
Impedance
1 kΩ
As an Output (Event)
Sources 1. Sample Clock divided by integer K(1 ≤K≤4,194,304)
2. Sample Clock Timebase (100 MHz) divided by
integer M(2 ≤ M≤ 4,194,304)
3. PLL Reference Clock
4. Marker
5. Exported Start Trigger (Out Start Trigger)
—
Output
Impedance
50 Ω—
Maximum
Output
Overload
–2 V to +7 V —

©National Instruments Corporation 13 NI 5412 Specifications
Start Trigger
VOH Minimum: 2.9 V (open load), 1.4 V (50 Ωload) Output driversare
+3.3 V TTL
compatible.
Measured with a
1 m cable.
VOL Maximum: 0.2 V (open load), 0.2 V (50 Ωload)
Rise/Fall Time
(20% to 80%)
≤2.0 ns Load of 10 pF.
Table 7.
Specification Value Comments
Sources 1. PFI<0..1> (SMB front panel connectors)
2. NI PXI-5412—PXI_Trig<0..7> (backplane connector)
NI PCI-5412—RTSI<0..7>
3. NI PXI-5412—PXI Star trigger (backplane connector)
4. Software (use function call)
5. Immediate (does not wait for a trigger). Default.
—
Modes 1. Single
2. Continuous
3. Stepped
4. Burst
—
Edge Detection Rising —
Minimum
Pulse Width
25 ns. Refer to ts1 at NI Signal Generators Help»Devices»
NI 5412»NI <bus>-5412»Triggering»Trigger Timing.
—
Table 6. (Continued)
Specification Value Comments

NI 5412 Specifications 14 ni.com
Delay from
Start Trigger to
CH 0 Analog
Output
Interpolation Factor Typical Delay Refer to ts2 at
NI Signal
Generators
Help»Devices»
NI 5412»
NI <bus>-5412»
Triggering»
Trigger Timing.
Digital Interpolation Filter
disabled.
43 Sample Clock
Periods + 110 ns
257 Sample Clock
Periods + 110 ns
463 Sample Clock
Periods + 110 ns
864 Sample Clock
Periods + 110 ns
Trigger Exporting
Exported
Trigger
Destinations
A signal used as a trigger can be routed out to any
destination listed in the Destinations specification
of Table 8.
—
Exported
Trigger Delay
65 ns (typical). Refer to ts3 at NI Signal Generators Help»
Devices»NI 5412»NI <bus>-5412»Triggering»Trigger
Timing.
—
Exported
Trigger Pulse
Width
>150 ns. Refer to ts4 at NI Signal Generators Help»
Devices»NI 5412»NI <bus>-5412»Triggering»Trigger
Timing.
—
Table 7. (Continued)
Specification Value Comments

©National Instruments Corporation 15 NI 5412 Specifications
Markers
Table 8.
Specification Value Comments
Destinations 1. PFI<0..1> (SMB front panel connectors)
2. NI PXI-5412—PXI_Trig<0..6> (backplane connector)
NI PCI-5412—RTSI<0..6>
—
Quantity One Marker per Segment. —
Quantum Marker position must be placed at an integer multiple of
four samples.
—
Width >150 ns. Refer to tm2 at NI Signal Generators Help»
Devices»NI 5412»NI <bus>-5412»Waveform
Generation»Marker Events.
—
Skew
Destination
With Respect to Analog
Output
Refer to tm1 at
NI Signal
Generators
Help»Devices»
NI 5412»
NI <bus>-5412»
Waveform
Generation»
Marker Events.
PFI<0..1> ±2 Sample Clock Periods
NI PXI-5412
PXI_Trig<0..6>
NI PCI-5412 RTSI<0..6>
±2 Sample Clock Periods

NI 5412 Specifications 16 ni.com
Waveform and Instruction Memory Utilization
Table 9.
Specification Value Comments
Memory Usage The NI 5412 uses the Synchronization and Memory Core
(SMC) technology in which waveforms and instructions
share onboard memory. Parameters, such as number of
segments in sequence list, maximum number of waveforms
in memory, and number of samples available for waveform
storage, are flexible and user defined.
—
Onboard
Memory Size
8 MB standard:
8,388,608 bytes
32 MB option:
33,554,432 bytes
256 MB option:
268,435,456 bytes
—
Output Modes Arbitrary Waveform mode and Arbitrary Sequence mode —
Arbitrary
Waveform
Mode
In Arbitrary Waveform mode, a single waveform is selected
from the set of waveforms stored in onboard memory and
generated.
—
Arbitrary
Sequence
Mode
In Arbitrary Sequence mode, a sequence directs the NI 5412
to generate a set of waveforms in a specific order. Elements
of the sequence are referred to as segments. Each segment is
associated with a set of instructions. The instructions
identify which waveform is selected from the set of
waveforms in memory, how many loops (iterations) of the
waveform are generated, and at which sample in the
waveform a marker output signal is sent.
—
Minimum
Waveform Size
(Samples)
Trigger Mode
Arbitrary
Waveform Mode
Arbitrary
Sequence Mode
The Minimum
Waveform Size
is sample rate
dependent in
Arbitrary
Sequence Mode.
Single 16 16
Continuous 16 96 @ >50 MS/s
32 @ ≤50 MS/s
Stepped 32 96 @ >50 MS/s
32 @ ≤50 MS/s
Burst 16 512 @ >50 MS/s
256 @ ≤50 MS/s

©National Instruments Corporation 17 NI 5412 Specifications
Loop Count 1 to 16,777,215.
Burst trigger: Unlimited
—
Quantum Waveform size must be an integer multiple of four samples. —
Memory Limits
8 MB Standard 32 MB Option 256 MB Option All trigger modes
except where
noted.
Arbitrary
Waveform
Mode,
Maximum
Waveform
Memory
4,194,176
Samples
16,777,088
Samples
134,217,600
Samples
Arbitrary
Sequence
Mode,
Maximum
Waveform
Memory
4,194,120
Samples
16,777,008
Samples
134,217,520
Samples
Condition: One
or two segments
in a sequence.
Arbitrary
Sequence
Mode,
Maximum
Waveforms
65,000
Burst trigger:
8,000
262,000
Burst trigger:
32,000
2,097,000
Burst trigger:
262,000
Condition: One
or two segments
in a sequence.
Arbitrary
Sequence
Mode,
Maximum
Segments in a
Sequence
104,000
Burst trigger:
65,000
418,000
Burst trigger:
262,000
3,354,000
Burst trigger:
2,090,000
Condition:
Waveform
memory is
<4,000 samples.
Table 9. (Continued)
Specification Value Comments

NI 5412 Specifications 18 ni.com
Calibration
Power
Table 10.
Specification Value Comments
Self-Calibration An onboard, 24-bit ADC and precision voltage reference are
used to calibrate the DC gain and offset. The self-calibration
is initiated by the user through the software and takes
approximately 75 seconds to complete.
—
External
Calibration
The External Calibration calibrates the VCXO, voltage
reference, DC gain, and offset. Appropriate constants are
stored in nonvolatile memory.
—
Calibration
Interval
Specifications valid within 2 years of External Calibration. —
Warm-up Time 15 minutes —
Table 11.
Specification Normal Operation Overload Operation Comments
Total Power 22 W 26 W Typical.
Overload
operation occurs
when CH 0 is
shorted to
ground.

©National Instruments Corporation 19 NI 5412 Specifications
Software
Table 12.
Specification Value Comments
Driver
Software
NI-FGEN 2.3 or later version. NI-FGEN is an
IVI-compliant driver that allows you to configure, control,
and calibrate the NI 5412. NI-FGEN provides application
programming interfaces for many development
environments.
—
Application
Software
NI-FGEN provides programming interfaces for the
following application development environments:
•LabVIEW
• LabWindows™/CVI™
• Measurement Studio
• Microsoft Visual C++ .NET
• Microsoft Visual C/C++
• Microsoft Visual Basic
—
Soft Front
Panel/
Interactive
Configuration
The FGEN Soft Front Panel 2.3 or later supports interactive
control of the NI 5412. The FGEN Soft Front Panel is
included on the NI-FGEN driver CD.
Measurement & Automation Explorer (MAX) also provides
interactive configuration and test tools for the NI 5412.
MAX is also included on the NI-FGEN CD.
—

NI 5412 Specifications 20 ni.com
Environment
NI PXI-5412 Environment
Note To ensure that the NI PXI-5412 cools effectively, follow the guidelines in the
Maintain Forced-Air Cooling Note to Users included in the NI 5412 kit. The NI PXI-5412
is intended for indoor use only.
Table 13.
Specifications Value Comments
Operating
Temperature
0 ºC to +55 ºC in all NI PXI chassis except the following:
0 ºC to +45 ºC when installed in an NI PXI-101xor
NI PXI-1000B chassis.
Meets IEC-60068-2-1 and IEC-60068-2-2.
—
Storage
Temperature
–25 ºC to +85 ºC. Meets IEC-60068-2-1 and
IEC-60068-2-2.
—
Operating
Relative
Humidity
10% to 90%, noncondensing. Meets IEC-60068-2-56. —
Storage
Relative
Humidity
5% to 95%, noncondensing. Meets IEC-60068-2-56. —
Operating
Shock
30 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
Spectral and jitter
specifications
could degrade.
Storage Shock 50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
—
Operating
Vibration
5 Hz to 500 Hz, 0.31 grms. Meets IEC-60068-2-64. Spectral and jitter
specifications
could degrade.
Storage
Vibration
5 Hz to 500 Hz, 2.46 grms. Meets IEC-60068-2-64. Test
profile exceeds requirements of MIL-PRF-28800F, Class B.
—
Altitude 2,000 m maximum (at 25 °C ambient temperature) —
Pollution
Degree
2 —