Nations N32G430 Series User manual

N32G430 series
32-bit ARM®Cortex®-M4 microcontroller
User manual V1.0

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Contents
Abbreviations in the text ...............................................................................................................................................28
List of abbreviations for registers .............................................................................................................................28
Available peripherals ................................................................................................................................................28
Memory and bus architecture.......................................................................................................................................29
System architecture...................................................................................................................................................29
Bus architecture .............................................................................................................................................29
Bus address mapping ..................................................................................................................................... 30
Boot management ..........................................................................................................................................34
Memory system ........................................................................................................................................................ 35
FLASH specification .....................................................................................................................................35
iCache ............................................................................................................................................................47
SRAM............................................................................................................................................................49
FLASH register description ...........................................................................................................................50
Power control (PWR) ....................................................................................................................................................58
General description................................................................................................................................................... 58
Power supply.................................................................................................................................................. 58
Power supply supervisor................................................................................................................................59
NRST.............................................................................................................................................................61
Power modes ............................................................................................................................................................61
SLEEP mode..................................................................................................................................................63
STOP0 mode.................................................................................................................................................. 64
STOP2 mode.................................................................................................................................................. 65
STANDBY mode........................................................................................................................................... 66
PWR registers...........................................................................................................................................................67
PWR register overview..................................................................................................................................67
Power control register (PWR_CTRL)............................................................................................................67
Power control status register (PWR_CTRLSTS)...........................................................................................69
Power control register 2(PWR_CTRL2)........................................................................................................71
Reset and clock control (RCC) .....................................................................................................................................73
General description................................................................................................................................................... 73
Reset Control Unit....................................................................................................................................................73
Power reset..................................................................................................................................................... 73
System reset................................................................................................................................................... 73
Backup domain reset......................................................................................................................................75
Clock control unit.....................................................................................................................................................75
Clock Tree Diagram.......................................................................................................................................76
HSE clock...................................................................................................................................................... 76
HSI clock .......................................................................................................................................................77

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PLL clock.......................................................................................................................................................78
LSE clock.......................................................................................................................................................78
LSI clock........................................................................................................................................................78
System clock (SYSCLK) selection................................................................................................................ 79
Clock security system (CLKSS) ....................................................................................................................79
LSE Clock security system (LSECSS) .......................................................................................................... 79
RTC clock..................................................................................................................................................80
Watchdog clock.......................................................................................................................................... 80
Clock output(MCO)................................................................................................................................... 80
RCC Registers ..........................................................................................................................................................81
RCC register overview................................................................................................................................... 81
Clock Control Register (RCC_CTRL)...........................................................................................................82
Clock Configuration Register (RCC_CFG)...................................................................................................84
Clock Interrupt Register (RCC_CLKINT).....................................................................................................87
APB2 Peripheral Reset Register (RCC_APB2PRST) ...................................................................................89
APB1 Peripheral Reset Register (RCC_APB1PRST) ...................................................................................91
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)....................................................................92
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN).................................................................94
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN).................................................................95
Backup Domain Control Register (RCC_BDCTRL)................................................................................. 97
Clock Control/Status Register (RCC_CTRLSTS).....................................................................................98
AHB Peripheral Reset Register (RCC_AHBPRST)................................................................................100
Clock Configuration Register 2 (RCC_CFG2)........................................................................................101
Retention Domain Control Register (RCC_RDCTRL) ...........................................................................102
PLL and HSI Configuration Register (RCC_PLLHSIPRE) ....................................................................103
AHB Peripheral Clock Enable Register 1 (RCC_AHB1CLKEN)........................................................... 103
GPIO andAFIO...........................................................................................................................................................105
Summary.................................................................................................................................................................105
Function description ...............................................................................................................................................106
I/O mode configuration................................................................................................................................106
Status after reset........................................................................................................................................... 111
Atomic bit set and reset................................................................................................................................ 111
External Interrupt /wakeup line.................................................................................................................... 112
Alternate function ........................................................................................................................................ 113
I/O configuration of peripherals................................................................................................................... 124
GPIO Locking mechanism...........................................................................................................................126
GPIO Registers.......................................................................................................................................................127
GPIOA register overview.............................................................................................................................127
GPIOB register overview............................................................................................................................. 129
GPIOC register overview.............................................................................................................................130
GPIOD register overview ............................................................................................................................132
GPIO port mode description register (GPIOx_PMODE).............................................................................133
GPIO port type definition (GPIOx_POTYPE) ............................................................................................ 134

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GPIO slew rate configuration register (GPIOx_SR)....................................................................................135
GPIO port pull-up/pull-down description register (GPIOx_PUPD) ............................................................ 135
GPIO port input data register (GPIOx_PID)................................................................................................136
GPIO port output data register (GPIOx_POD)........................................................................................ 137
GPIO port bit set/clear register (GPIOx_PBSC)...................................................................................... 137
GPIO port bit clear register (GPIOx_PBC) .............................................................................................138
GPIO port configuration lock register (GPIOx_ PLOCK) ......................................................................139
GPIO Alternate function low register (GPIOx_AFL)..............................................................................140
GPIO Alternate function high register (GPIOx_AFH) ............................................................................140
GPIO driver strength configuration register (GPIOx_ DS) ..................................................................... 141
AFIO Registers....................................................................................................................................................... 142
AFIO register overview ...............................................................................................................................142
Alternate function mapping configuration control register (AFIO_RMP_CFG).........................................144
External interrupt configuration register 1 (AFIO_EXTI_CFG1) ...............................................................144
External interrupt configuration register 2 (AFIO_EXTI_CFG2) ...............................................................151
External interrupt configuration register 3 (AFIO_EXTI_CFG3) ...............................................................158
External interrupt configuration register 4 (AFIO_EXTI_CFG4) ...............................................................165
5V tolerance configuration register (AFIO_TOL5V _CFG)........................................................................172
Analog filter configuration register 1 (AFIO_EFT_CFG1).........................................................................174
Analog filter configuration register 2 (AFIO_EFT_CFG2).........................................................................174
Digital glitch filter stage (glitch width) configuration register (AFIO_FILT_CFG)................................ 175
Digital glitch filter configuration register 1 (AFIO_DIGEFT_CFG1) .................................................... 176
Digital glitch filter configuration register 2 (AFIO_DIGEFT_CFG2) ....................................................176
Interrupts and events...................................................................................................................................................178
Nested vectored interrupt controller .......................................................................................................................178
SysTick calibration value register................................................................................................................ 178
Interrupt and exception vectors....................................................................................................................178
External interrupt/event controller (EXTI).............................................................................................................181
Introduction to EXTI.................................................................................................................................... 181
EXTI main features...................................................................................................................................... 181
Functional description..................................................................................................................................182
EXTI line mapping ...................................................................................................................................... 184
EXTI Registers.......................................................................................................................................................185
EXTI register overview................................................................................................................................185
Interrupt Mask Register(EXTI_IMASK)..................................................................................................... 185
Event Mask Register(EXTI_EMASK) ........................................................................................................ 186
Rising Edge Trigger Selection Register(EXTI_RT_CFG)...........................................................................186
Falling Edge Trigger Selection Register(EXTI_FT_CFG) ..........................................................................187
Software Interrupt Event Register(EXTI_SWIE) ........................................................................................187
Interrupt Request Pending Register(EXTI_PEND) .....................................................................................188
RTC Timestamp Selection Register(EXTI_TS_SEL).................................................................................. 188
DMA controller............................................................................................................................................................190

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Introduction ............................................................................................................................................................190
Main features..........................................................................................................................................................190
Block diagram ........................................................................................................................................................ 191
Function description ...............................................................................................................................................191
DMA operation ............................................................................................................................................ 191
Channel priority and arbitration...................................................................................................................192
DMA channels and number of transfers....................................................................................................... 192
Programmable data bit width, alignment and endians ................................................................................. 192
Peripheral/Memory address incrementation ................................................................................................ 194
Channel configuration procedure................................................................................................................. 194
Flow control................................................................................................................................................. 195
Circular mode ..............................................................................................................................................195
Error management........................................................................................................................................ 196
Interrupt ...................................................................................................................................................196
DMA request mapping.............................................................................................................................196
DMAregisters ........................................................................................................................................................199
DMA register overview................................................................................................................................ 199
DMA interrupt status register (DMA_INTSTS) .......................................................................................... 200
DMA interrupt flag clear register (DMA_INTCLR).................................................................................... 201
DMA channel x configuration register (DMA_CHCFGx)...........................................................................202
DMA channel x transfer number register (DMA_TXNUMx) .....................................................................203
DMA channel x peripheral address register (DMA_PADDRx)...................................................................204
DMA channel x memory address register (DMA_MADDRx) ....................................................................204
DMA channel x channel request select register (DMA_CHSELx)..............................................................205
CRC calculation unit ...................................................................................................................................................207
CRC introduction....................................................................................................................................................207
CRC main features..................................................................................................................................................207
CRC32 module ............................................................................................................................................207
CRC16 module ............................................................................................................................................207
CRC function description .......................................................................................................................................208
CRC32 .........................................................................................................................................................208
CRC16 .........................................................................................................................................................208
CRC registers..........................................................................................................................................................209
CRC register overview................................................................................................................................. 209
CRC32 data register (CRC_CRC32DAT).................................................................................................... 209
CRC32 independent data register (CRC_CRC32IDAT)..............................................................................209
CRC32 control register (CRC_CRC32CTRL).............................................................................................210
CRC16 control register (CRC_CRC16CTRL).............................................................................................210
CRC16 input data register (CRC_CRC16DAT) .......................................................................................... 211
CRC cyclic redundancy check code register (CRC_CRC16D) ................................................................... 211
LRC result register (CRC_LRC)..................................................................................................................212
Advanced-control timers (TIM1 and TIM8) .................................................................................................................213

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TIM1 and TIM8 introduction ....................................................................................................................................213
Main features of TIM1 and TIM8 ..............................................................................................................................213
TIM1 and TIM8 function description ........................................................................................................................ 215
Time-base unit ............................................................................................................................................... 215
Counter mode ................................................................................................................................................ 216
Repetition counter ......................................................................................................................................... 226
Clock selection .............................................................................................................................................. 228
Capture/compare channels .............................................................................................................................232
Input capture mode ........................................................................................................................................234
PWM input mode ..........................................................................................................................................235
Forced output mode ....................................................................................................................................... 236
Output compare mode .................................................................................................................................... 237
PWM mode ............................................................................................................................................... 238
One-pulse mode ........................................................................................................................................ 241
Clearing the OCxREF signal on an external event ...................................................................................... 242
Complementary outputs with dead-time insertion .......................................................................................243
Break function ...........................................................................................................................................245
Debug mode ..............................................................................................................................................247
TIMx and external trigger synchronization ................................................................................................. 247
Timer synchronization ...............................................................................................................................251
6-step PWM generation .............................................................................................................................251
Encoder interface mode .............................................................................................................................252
Interfacing with Hall sensor ....................................................................................................................... 255
TIMx register description(x=1, 8) .............................................................................................................................257
Register overview ........................................................................................................................................ 257
Control register 1 (TIMx_CTRL1) ..............................................................................................................260
Control register 2 (TIMx_CTRL2) ..............................................................................................................262
Slave mode control register (TIMx_SMCTRL)...........................................................................................265
DMA/Interrupt enable registers (TIMx_DINTEN)......................................................................................267
Status registers (TIMx_STS) .......................................................................................................................269
Event generation registers (TIMx_EVTGEN).............................................................................................271
Capture/compare mode register 1 (TIMx_CCMOD1).................................................................................272
Capture/compare mode register 2 (TIMx_CCMOD2).................................................................................275
Capture/compare enable registers (TIMx_CCEN)................................................................................... 277
Counters (TIMx_CNT)............................................................................................................................280
Prescaler (TIMx_PSC).............................................................................................................................280
Auto-reload register (TIMx_AR)............................................................................................................. 281
Repeat count registers (TIMx_REPCNT)................................................................................................281
Capture/compare register 1 (TIMx_CCDAT1)........................................................................................ 281
Capture/compare register 2 (TIMx_CCDAT2)........................................................................................ 282
Capture/compare register 3 (TIMx_CCDAT3)........................................................................................ 283
Capture/compare register 4 (TIMx_CCDAT4)........................................................................................ 284
Break and Dead-time registers (TIMx_BKDT)....................................................................................... 285

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DMA Control register (TIMx_DCTRL) ..................................................................................................286
DMA transfer buffer register (TIMx_DADDR) ...................................................................................... 287
Capture/compare mode registers 3(TIMx_CCMOD3) ............................................................................288
Capture/compare register 5 (TIMx_CCDAT5)........................................................................................ 288
Capture/compare register 6 (TIMx_CCDAT6)........................................................................................ 289
Capture/compare register 7 (TIMx_CCDAT7)........................................................................................289
Capture/compare register 8 (TIMx_CCDAT8)........................................................................................ 290
Capture/compare register 9 (TIMx_CCDAT9)........................................................................................ 290
Break Filter (TIMx_BRKFILT)...............................................................................................................291
General-purpose timers (TIM2, TIM3, TIM4 and TIM5) ..........................................................................................293
General-purpose timers introduction ........................................................................................................................ 293
Main features of General-purpose timers ................................................................................................................. 293
General-purpose timers description ......................................................................................................................... 294
Time-base unit ...........................................................................................................................................294
Counter mode ............................................................................................................................................ 295
Clock selection ..........................................................................................................................................301
Capture/compare channels .........................................................................................................................305
Input capture mode .................................................................................................................................... 308
PWM input mode ...................................................................................................................................... 309
Forced output mode ...................................................................................................................................310
Output compare mode ............................................................................................................................... 311
PWM mode ............................................................................................................................................... 312
One-pulse mode ........................................................................................................................................ 315
Clearing the OCxREF signal on an external event ...................................................................................... 316
Debug mode ..............................................................................................................................................317
TIMx and external trigger synchronization ................................................................................................. 317
Timer synchronization ...............................................................................................................................321
Encoder interface mode .............................................................................................................................325
Interfacing with Hall sensor ....................................................................................................................... 328
TIMx register description(x=2, 3, 4 and 5) ............................................................................................................... 329
Register overview.................................................................................................................................... 329
Control register 1 (TIMx_CTRL1).......................................................................................................... 330
Control register 2 (TIMx_CTRL2).......................................................................................................... 333
Slave mode control register (TIMx_SMCTRL).......................................................................................334
DMA/Interrupt enable registers (TIMx_DINTEN) .................................................................................336
Status registers (TIMx_STS) ................................................................................................................... 337
Event generation registers (TIMx_EVTGEN).........................................................................................339
Capture/compare mode register 1 (TIMx_CCMOD1).............................................................................340
Capture/compare mode register 2 (TIMx_CCMOD2).............................................................................343
Capture/compare enable registers (TIMx_CCEN)...................................................................................344
Counters (TIMx_CNT)............................................................................................................................346
Prescaler (TIMx_PSC).............................................................................................................................346
Auto-reload register (TIMx_AR)............................................................................................................. 346

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Capture/compare register 1 (TIMx_CCDAT1)........................................................................................ 347
Capture/compare register 2 (TIMx_CCDAT2)........................................................................................ 347
Capture/compare register 3 (TIMx_CCDAT3)........................................................................................348
Capture/compare register 4 (TIMx_CCDAT4)........................................................................................ 348
DMA Control register (TIMx_DCTRL) ..................................................................................................349
DMA transfer buffer register (TIMx_DADDR) ...................................................................................... 350
Channel 1 filter register (TIMx_C1FILT)................................................................................................350
Channel 2 filter register (TIMx_C2FILT)................................................................................................351
Channel 3 filter register (TIMx_C3FILT)................................................................................................352
Channel 4 filter register (TIMx_C4FILT)................................................................................................353
Channel filter Output register (TIMx_FILTO)......................................................................................... 354
Basic timers (TIM6) .....................................................................................................................................................355
Basic timers introduction ........................................................................................................................................355
Main features of Basic timers ..................................................................................................................................355
Basic timers description ..........................................................................................................................................355
Time-base unit ...........................................................................................................................................355
Counter mode ............................................................................................................................................ 356
Clock selection ..........................................................................................................................................359
Debug mode ..............................................................................................................................................359
TIMx register description(x=6) ...............................................................................................................................359
Register overview.................................................................................................................................... 360
Control Register 1 (TIMx_CTRL1).........................................................................................................360
DMA/Interrupt Enable Registers (TIMx_DINTEN) ............................................................................... 361
Status Registers (TIMx_STS)..................................................................................................................362
Event Generation registers (TIMx_EVTGEN)........................................................................................362
Counters (TIMx_CNT)............................................................................................................................363
Prescaler (TIMx_PSC).............................................................................................................................363
Automatic reload register (TIMx_AR) ....................................................................................................363
Low Power Timer (LPTIM) .........................................................................................................................................364
Introduction ..........................................................................................................................................................364
Main Features....................................................................................................................................................... 364
Block diagram ...................................................................................................................................................... 365
Function description .............................................................................................................................................365
LPTIM clocks and on-off control ............................................................................................................365
Prescalar...................................................................................................................................................366
Glitch filter ..............................................................................................................................................366
Timer enable ............................................................................................................................................ 367
Trigger multiplexer..................................................................................................................................367
Operating mode .......................................................................................................................................368
Waveform generation............................................................................................................................... 371
Register update ........................................................................................................................................372
Counter mode...........................................................................................................................................373

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Encoder mode..........................................................................................................................................373
Non-orthogonal encoder mode ................................................................................................................375
Timeout function......................................................................................................................................376
LPTIM interrupts..................................................................................................................................... 377
LPTIM registers....................................................................................................................................................378
LPTIM register overview......................................................................................................................... 378
LPTIM interrupt and status register (LPTIM_INTSTS)..........................................................................378
LPTIM interrupt clear register (LPTIM_INTCLR) .................................................................................379
LPTIM interrupt enable register (LPTIM_INTEN)................................................................................. 380
LPTIM configuration register (LPTIM_CFG)......................................................................................... 381
LPTIM control register (LPTIM_CTRL) ................................................................................................ 384
LPTIM compare register (LPTIM_COMP).............................................................................................385
LPTIM auto-reload register (LPTIM_ARR)............................................................................................385
LPTIM counter register (LPTIM_CNT)..................................................................................................385
LPTIM option register (LPTIM_OPT) ....................................................................................................386
Independent watchdog (IWDG) ...............................................................................................................................387
Introduction ..........................................................................................................................................................387
Main features........................................................................................................................................................387
Function description .............................................................................................................................................388
Register access protection........................................................................................................................388
Debug mode.............................................................................................................................................389
IWDG Freeze........................................................................................................................................... 389
User Interface .......................................................................................................................................................389
Operate Flow ........................................................................................................................................... 389
IWDG configuration flow........................................................................................................................390
IWDG registers.....................................................................................................................................................390
IWDG register overview..........................................................................................................................390
IWDG Key Register (IWDG_KEY)........................................................................................................391
IWDG Pre-Scaler Register (IWDG_PREDIV)........................................................................................391
IWDG Reload Register (IWDG_RELV) ................................................................................................. 392
IWDG Status Register (IWDG_STS)...................................................................................................... 392
Window watchdog (WWDG)....................................................................................................................................394
Introduction ..........................................................................................................................................................394
Main features........................................................................................................................................................394
Function description .............................................................................................................................................394
Timing for refresh watchdog and interrupt generation .........................................................................................395
Debug mode..........................................................................................................................................................396
User Interface .......................................................................................................................................................396
WWDG configuration flow .....................................................................................................................396
WWDG registers ..................................................................................................................................................397
WWDG register Map............................................................................................................................... 397
WWDG control register (WWDG_CTRL).............................................................................................. 397

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WWDG config register (WWDG_CFG) .................................................................................................398
WWDG status register (WWDG_STS) ................................................................................................... 398
Analog to digital conversion (ADC) .............................................................................................................................399
Introduction ..........................................................................................................................................................399
Main features ..........................................................................................................................................................399
Function Description ...............................................................................................................................................400
ADC clock ................................................................................................................................................401
ADC switch control ...................................................................................................................................402
Channel selection ......................................................................................................................................402
Internal channel ....................................................................................................................................... 403
Single conversion mode ............................................................................................................................. 404
Continuous conversion mode ....................................................................................................................404
Timing diagram .........................................................................................................................................404
Analog watchdog ......................................................................................................................................405
Scanning mode ..........................................................................................................................................406
Injection channel management ...................................................................................................................406
Discontinuous mode ..................................................................................................................................407
Calibration............................................................................................................................................................408
Data aligned ...........................................................................................................................................................408
Programmable channel sampling time .....................................................................................................................410
Externally triggered conversion ............................................................................................................................... 410
DMA requests....................................................................................................................................................... 411
Temperature sensor ................................................................................................................................................. 411
Temperature sensor using flow................................................................................................................ 412
ADC interrupt..................................................................................................................................................... 413
ADC registers......................................................................................................................................................413
ADC register overview .............................................................................................................................414
ADC status register (ADC_STS) ................................................................................................................415
ADC control register 1 (ADC_CTRL1) .................................................................................................. 416
ADC control register 2 (ADC_CTRL2) .................................................................................................. 418
ADC sampling time register 1 (ADC_SAMPT1)....................................................................................420
ADC sampling time register 2 (ADC_ SAMPT2)................................................................................... 421
ADC injected channel data offset register x (ADC_JOFFSETx) (x=1…4)............................................. 421
ADC watchdog high threshold register (ADC_WDGHIGH) .......................................................................422
ADC watchdog low threshold register (ADC_WDGLOW) .........................................................................422
ADC regular sequence register 1 (ADC_RSEQ1)...............................................................................423
ADC regular sequence register 2 (ADC_RSEQ2)...............................................................................423
ADC regular sequence register 3 (ADC_RSEQ3)...............................................................................424
ADC Injection sequence register (ADC_JSEQ) .......................................................................................424
ADC injection data register x (ADC_JDATx) (x= 1…4) .................................................................... 425
ADC regulars data register (ADC_DAT) ................................................................................................425
ADC differential mode selection register (ADC_DIFSEL).................................................................426
ADC calibration factor (ADC_CALFACT).........................................................................................426

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ADC control register 3 (ADC_CTRL3) .............................................................................................. 427
ADC sampling time register 3 (ADC_SAMPT3)................................................................................ 428
Comparator (COMP) ................................................................................................................................................430
COMP system connection block diagram............................................................................................................. 430
COMP features .....................................................................................................................................................431
COMP configuration process................................................................................................................................ 431
COMP working mode...........................................................................................................................................432
Window mode..........................................................................................................................................432
Independent comparator ..........................................................................................................................432
Comparator interconnection .................................................................................................................................432
Interrupt................................................................................................................................................................433
COMP register...................................................................................................................................................... 434
COMP register overview ......................................................................................................................... 434
COMP interrupt enable register (COMP_INTEN) .................................................................................. 435
COMP low power select register (COMP_LPCKSEL) ...........................................................................436
COMP window mode register (COMP_WINMODE)............................................................................. 436
COMP lock register (COMP_LOCK)......................................................................................................437
COMP1 control register (COMP1_CTRL).............................................................................................. 437
COMP1 filter register (COMP1_FILC)................................................................................................... 439
COMP1 filter frequency division register (COMP1_FILP).....................................................................440
COMP2 control register (COMP2_CTRL).............................................................................................. 440
COMP2 filter register (COMP2_FILC)................................................................................................... 442
COMP2 filter frequency division register (COMP2_FILP).....................................................................443
COMP2 output select register (COMP2_OSEL).....................................................................................443
COMP3 control register (COMP3_CTRL ).............................................................................................444
COMP3 filter register (COMP3_FILC)................................................................................................... 445
COMP filter frequency division register (COMP3_FILP).......................................................................446
COMP reference voltage register (COMP_VREFSCL) ..........................................................................446
COMP test register(COMP_TEST) ......................................................................................................... 447
COMP interrupt status register (COMP_INTSTS).................................................................................. 448
I2C interface ...............................................................................................................................................................449
Introduction ..........................................................................................................................................................449
Characteristics ...................................................................................................................................................... 449
Function description .............................................................................................................................................449
SDA and SCL line control .......................................................................................................................450
Software communication process ............................................................................................................450
Error conditions description.....................................................................................................................459
DMA application .....................................................................................................................................460
Packet error check.................................................................................................................................... 462
Noise filter...............................................................................................................................................462
SMBus..................................................................................................................................................... 462
Debug mode..........................................................................................................................................................465

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Interrupt request.................................................................................................................................................... 465
I2C register...........................................................................................................................................................466
I2C register overview .............................................................................................................................. 466
Control register 1 (I2C_CTRL1) .............................................................................................................466
Control register 2 (I2C_CTRL2) .............................................................................................................469
Own address register 1 (I2C_OADDR1)................................................................................................. 470
Own address register 2 (I2C_OADDR2)................................................................................................. 471
Data register (I2C_DAT) .........................................................................................................................471
Status register 1 (I2C_STS1)................................................................................................................... 471
Status register 2 (I2C_STS2)................................................................................................................... 475
Clock control register (I2C_CLKCTRL)................................................................................................. 476
Rise time register (I2C_TMRISE)...........................................................................................................477
Universal synchronous asynchronous receiver transmitter (USART) ..................................................................479
Introduction ..........................................................................................................................................................479
Main features........................................................................................................................................................479
Functional block diagram .....................................................................................................................................480
Function description .............................................................................................................................................480
USART frame format............................................................................................................................... 481
Transmitter...............................................................................................................................................482
Receiver...................................................................................................................................................485
Generation of fractional baud rate ...........................................................................................................489
Receiver’s tolerance clock deviation .......................................................................................................490
Parity control ...........................................................................................................................................491
DMA application .....................................................................................................................................492
Hardware flow control.............................................................................................................................494
Multiprocessor communication ............................................................................................................... 496
Synchronous mode...................................................................................................................................498
Single-wire half-duplex mode .................................................................................................................501
IrDA SIR ENDEC mode.......................................................................................................................... 502
LIN mode................................................................................................................................................. 504
Smartcard mode (ISO7816).....................................................................................................................506
Interrupt request.................................................................................................................................................... 508
Mode support........................................................................................................................................................ 509
USART register ....................................................................................................................................................509
USART register overview........................................................................................................................ 509
USART Status register (USART_STS).................................................................................................... 511
USART Data register (USART_DAT).....................................................................................................513
USART Baud rate register (USART_BRCF)...........................................................................................513
USART control register 1 register (USART_CTRL1)............................................................................. 514
USART control register 2 register (USART_CTRL2)............................................................................. 516
USART control register 3 register (USART_CTRL3)............................................................................. 517
USART guard time and prescaler register (USART_GTP)......................................................................519

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Serial peripheral interface/Inter-IC Sound (SPI/ I2S) ............................................................................................521
SPI/ I2S introduction.............................................................................................................................................521
SPI and I2S main features ..................................................................................................................................... 521
SPI features..............................................................................................................................................521
I2S features...............................................................................................................................................521
SPI function description .......................................................................................................................................522
General description..................................................................................................................................522
SPI work mode ........................................................................................................................................525
Status flag ................................................................................................................................................531
Disabling the SPI.....................................................................................................................................532
SPI communication using DMA..............................................................................................................533
CRC calculation.......................................................................................................................................534
Error flag..................................................................................................................................................535
SPI interrupt.............................................................................................................................................536
I2S function description ........................................................................................................................................537
Supported audio protocols .......................................................................................................................538
Clock generator........................................................................................................................................ 544
I2S Transmission and reception sequence................................................................................................ 546
Status flag ................................................................................................................................................548
Error flag..................................................................................................................................................549
I2S interrupt.............................................................................................................................................. 549
DMA function.......................................................................................................................................... 549
SPI and I2S register description ............................................................................................................................550
SPI register overview............................................................................................................................... 550
SPI control register 1 (SPI_CTRL1) (not used in I2S mode) .................................................................. 550
SPI control register 2 (SPI_CTRL2)........................................................................................................553
SPI status register (SPI_STS) ..................................................................................................................553
SPI data register (SPI_DAT)....................................................................................................................555
SPI CRC polynomial register (SPI_CRCPOLY) (not used in I2S mode)................................................. 555
SPI RX CRC register (SPI_CRCRDAT) (not used in I2S mode).............................................................555
SPI TX CRC register（SPI_CRCTDAT）..............................................................................................556
SPI_ I2S configuration register（SPI_I2SCFG）................................................................................... 556
SPI_I2S prescaler register (SPI_I2SPREDIV)......................................................................................... 558
Real-time clock (RTC)...............................................................................................................................................559
Description ...........................................................................................................................................................559
Specification............................................................................................................................................560
RTC function description...................................................................................................................................... 561
RTC block diagram..................................................................................................................................561
GPIOs of RTC.......................................................................................................................................... 562
RTC register write protection .................................................................................................................. 562
RTC clock and prescaler.......................................................................................................................... 563
RTC calendar ...........................................................................................................................................563

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Calendar initialization and configuration................................................................................................. 564
Calendar reading......................................................................................................................................564
Calibration clock output........................................................................................................................... 565
Programmable alarms..............................................................................................................................565
Alarm configuration.................................................................................................................................565
Alarm output............................................................................................................................................ 565
Periodic automatic wakeup...................................................................................................................... 566
Wakeup timer configuration .................................................................................................................... 566
Timestamp function................................................................................................................................. 566
Tamper Detection..................................................................................................................................... 567
Daylight saving time configuration .........................................................................................................568
RTC sub-second register shift.................................................................................................................. 568
RTC digital clock precision calibration ................................................................................................... 568
RTC low power mode.............................................................................................................................. 569
RTC Registers....................................................................................................................................................... 570
RTC Register overview............................................................................................................................ 570
RTC Calendar Time Register (RTC_TSH) ..............................................................................................571
RTC Calendar Date Register (RTC_DATE) ............................................................................................572
RTC Control Register (RTC_CTRL).......................................................................................................572
RTC Initial Status Register (RTC_INITSTS) ..........................................................................................575
RTC Prescaler Register (RTC_PRE) ....................................................................................................... 577
RTC Wakeup Timer Register (RTC_WKUPT)........................................................................................ 577
RTC Alarm A Register (RTC_ALARMA)...............................................................................................578
RTC Alarm B Register (RTC_ ALARMB)..............................................................................................579
RTC Write Protection register (RTC_WRP)............................................................................................ 580
RTC Sub-second Register (RTC_SUBS).................................................................................................580
RTC Shift Control Register (RTC_ SCTRL)...........................................................................................581
RTC Timestamp Time Register (RTC_TST) ...........................................................................................581
RTC Timestamp Date Register (RTC_TSD)............................................................................................582
RTC Timestamp Sub-second Register (RTC_TSSS)............................................................................... 583
RTC Calibration Register (RTC_CALIB)................................................................................................583
RTC Tamper Configuration Register（RTC_ TMPCFG）.....................................................................584
RTC Alarm A sub-second register (RTC_ ALRMASS)...........................................................................587
RTC Alarm B sub-second register (RTC_ ALRMBSS)........................................................................... 587
RTC Option Register (RTC_ OPT).......................................................................................................... 588
RTC Backup registers (RTC_ BKP(1~20)).............................................................................................. 588
Beeper.........................................................................................................................................................................590
Introduction ..........................................................................................................................................................590
Function description .............................................................................................................................................590
Main Features ..........................................................................................................................................590
Setup freqeuency for pre-scale ratio of beeper ........................................................................................590
Bypass clock............................................................................................................................................591
Output Duty cycle.................................................................................................................................... 591

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Beeper registers ....................................................................................................................................................591
Beeper register overview .........................................................................................................................591
Beeper Control Register (BEEPER_CTRL)............................................................................................591
Controller area network (CAN)................................................................................................................................593
Introduction to CAN.............................................................................................................................................593
Main features of CAN ..........................................................................................................................................593
CAN overall introduction .....................................................................................................................................593
CAN module............................................................................................................................................594
CAN working mode.................................................................................................................................594
Send mailbox...........................................................................................................................................596
Receiving filter ........................................................................................................................................596
Receive FIFO...........................................................................................................................................596
CAN Test mode .......................................................................................................................................597
CAN Debugging mode ............................................................................................................................ 600
CAN function description..................................................................................................................................... 600
Send processing .......................................................................................................................................600
Time triggered communication mode......................................................................................................601
Non-automatic retransmission mode .......................................................................................................601
Receiving management............................................................................................................................602
Identifier filtering.....................................................................................................................................604
Message storage.......................................................................................................................................607
Bit time characteristic..............................................................................................................................608
CAN interrupt....................................................................................................................................................... 611
Error management ...................................................................................................................................612
Bus-Off recovery .....................................................................................................................................612
CAN Configuration Flow..................................................................................................................................... 612
CAN Register File ................................................................................................................................................ 614
Register Description ................................................................................................................................614
CAN register address overview ............................................................................................................... 615
CAN control and status register............................................................................................................... 619
CAN mailbox register..............................................................................................................................630
CAN filter register................................................................................................................................... 635
Debug support (DBG)................................................................................................................................................ 639
Overview ..............................................................................................................................................................639
JTAG/SW function ...............................................................................................................................................640
Switch JTAG/SW interface......................................................................................................................640
Pin allocation ...........................................................................................................................................640
MCU debugging function..................................................................................................................................... 641
Low power mode support ........................................................................................................................ 641
Peripheral debugging support ..................................................................................................................641
DBG registers.......................................................................................................................................................642
DBG register overview............................................................................................................................ 642

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ID register (DBG_ID)..............................................................................................................................642
Debug control register (DBG_CTRL) .....................................................................................................643
Unique device serial number (UID)..........................................................................................................................645
Introduction ..........................................................................................................................................................645
UID register..........................................................................................................................................................645
UCID register .......................................................................................................................................................645
Version history ...........................................................................................................................................................646
Notice ..........................................................................................................................................................................647

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List of Table
Table 2-1 List of peripheral register addresses.................................................................................................. 32
Table 2-2 List of boot mode............................................................................................................................... 35
Table 2-3 Flash bus address list......................................................................................................................... 36
Table 2-4 Option byte list .................................................................................................................................. 40
Table 2-5 Read protection configuration list ..................................................................................................... 42
Table 2-6 Flash read-write-erase permission control table................................................................................ 43
Table 2-7 FLASH register overview.................................................................................................................. 50
Table 3-1 Power modes...................................................................................................................................... 61
Table 3-2 Modules running status...................................................................................................................... 62
Table 3-3 PWR register overview...................................................................................................................... 67
Table 4-1 RCC register overview ...................................................................................................................... 81
Table 5-1 I/O port configuration table............................................................................................................. 106
Table 5-2 I/O List of functional features of the pin......................................................................................... 107
Table 5-3 special pins after reset.......................................................................................................................111
Table 5-4 Debug interface signal......................................................................................................................114
Table 5-5 Debug port image .............................................................................................................................114
Table 5-6 ADC external trigger injected conversion alternate function remapping..........................................115
Table 5-7 ADC external trigger regular conversion alternate function remapping...........................................115
Table 5-8 TIM1 alternate function remapping..................................................................................................115
Table 5-9 TIM2 alternate function remapping..................................................................................................116
Table 5-10 TIM3 alternate function remapping................................................................................................116
Table 5-11 TIM4 alternate function remapping................................................................................................116
Table 5-12 TIM5 alternate function remapping................................................................................................117
Table 5-13 TIM8 alternate function remapping................................................................................................117
Table 5-14 LPTIM alternate function remapping.............................................................................................118
Table 5-15 CAN alternate function remapping.................................................................................................118
Table 5-16 USART1 alternate function remapping ..........................................................................................118
Table 5-17 USART2 alternate function remapping ..........................................................................................119
Table 5-18 UART3 alternate function remapping.............................................................................................119
Table 5-19 UART4 alternate function remapping............................................................................................ 120

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Table 5-20 I2C1 alternate function remapping................................................................................................ 120
Table 5-21 I2C2 alternate function remapping................................................................................................ 121
Table 5-22 SPI1/I2S1 alternate function remapping........................................................................................ 121
Table 5-23 SPI2/I2S2 alternate function remapping........................................................................................ 122
Table 5-24 COMP1 alternate function remapping........................................................................................... 122
Table 5-25 COMP2 alternate function remapping........................................................................................... 122
Table 5-26 COMP3 alternate function remapping........................................................................................... 123
Table 5-27 EVENTOUT alternate function remapping................................................................................... 123
Table 5-28 BEEPER alternate function remapping......................................................................................... 123
Table 5-29 JTAG/SWD alternate function remapping..................................................................................... 123
Table 5-30 TIMESTAMP alternate function remapping.................................................................................. 123
Table 5-31 RTC_REFIN alternate function remapping................................................................................... 124
Table 5-32 MCO alternate function remapping............................................................................................... 124
Table 5-33 ADC............................................................................................................................................... 124
Table 5-34 TIM1/TIM8 ................................................................................................................................... 124
Table 5-35 TIM2/3/4/5..................................................................................................................................... 124
Table 5-36 LPTIM........................................................................................................................................... 124
Table 5-37 CAN............................................................................................................................................... 124
Table 5-38 USART.......................................................................................................................................... 125
Table 5-39 UART ............................................................................................................................................ 125
Table 5-40 I2C................................................................................................................................................. 125
Table 5-41 SPI-I2S .......................................................................................................................................... 125
Table 5-42 JTAG/SWD.................................................................................................................................... 125
Table 5-43 RTC................................................................................................................................................ 126
Table 5-44 COMP............................................................................................................................................ 126
Table 5-45 EVENT_OUT................................................................................................................................ 126
Table 5-46 Other.............................................................................................................................................. 126
Table 5-47 GPIOA register overview .............................................................................................................. 127
Table 5-48 GPIOB register overview .............................................................................................................. 129
Table 5-49 GPIOC register overview .............................................................................................................. 130
Table 5-50 GPIOD register overview.............................................................................................................. 132

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Table 5-51 AFIO register overview ................................................................................................................. 142
Table 6-1 Vector table...................................................................................................................................... 178
Table 6-2 EXTI register overview................................................................................................................... 185
Table 7-1 Programmable data width and endian operation (when PINC = MINC = 1) .................................. 192
Table 7-2 Flow control table............................................................................................................................ 195
Table 7-3 DMA interrupt request..................................................................................................................... 196
Table 7-4 DMA request mapping..................................................................................................................... 196
Table 7-5 DMA register overview ................................................................................................................... 199
Table 8-1 CRC register overview .................................................................................................................... 209
Table 9-1 Counting direction versus encoder signals...................................................................................... 253
Table 9-2 Register overview............................................................................................................................ 257
Table 9-3 TIMx internal trigger connection..................................................................................................... 267
Table 9-4 Output control bits of complementary OCx and OCxN channels with break function ................... 279
Table 10-1 Counting direction versus encoder signals.................................................................................... 326
Table 10-2 Register overview.......................................................................................................................... 329
Table 10-3 TIMx internal trigger connection................................................................................................... 336
Table 10-4 Output control bits of standard OCx channel ................................................................................ 346
Table 11-1 Register overview.......................................................................................................................... 360
Table 12-1 Pre-scalar division ratios................................................................................................................ 366
Table 12-2 9 trigger inputs corresponding to LPTIM_CFG.TRGSEL[3:0] bits.............................................. 367
Table 12-3 Encoder counting scenarios........................................................................................................... 374
Table 12-4 Interruption events......................................................................................................................... 377
Table 12-5 LPTIM register overview .............................................................................................................. 378
Table 13-1 IWDG counting maximum and minimum reset time .................................................................... 390
Table 13-2 IWDG register overview................................................................................................................ 390
Table 14-1 Maximum and minimum counting time of WWDG...................................................................... 396
Table 14-2 WWDG register overview............................................................................................................. 397
Table 15-1 ADC pins ....................................................................................................................................... 400
Table 15-2Analog watchdog channel selection............................................................................................... 405
Table 15-3 Right-align data ............................................................................................................................. 409
Table 15-4 Left-aligne data.............................................................................................................................. 409

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Table 15-5ADC is used for external triggering of regular channels ............................................................... 410
Table 15-6ADC is used for external triggering of injection channels..............................................................411
Table 15-7 ADC interrupt................................................................................................................................ 413
Table 15-8 ADC register overview.................................................................................................................. 414
Table 16-1 COMP register overview............................................................................................................... 434
Table 17-1 Comparison between SMBus and I2C........................................................................................... 463
Table 17-2 I2C interrupt request....................................................................................................................... 465
Table 17-3 I2C register overview .................................................................................................................... 466
Table 18-1 Stop bit configuration.................................................................................................................... 483
Table 18-2 Data sampling for noise detection ................................................................................................. 488
Table 18-3 Error calculation when setting baud rate....................................................................................... 490
Table 18-4 when DIV_Fraction = 0. Tolerance of USART receiver................................................................ 491
Table 18-5 when DIV_Fraction != 0, Tolerance of USART receiver .............................................................. 491
Table 18-6 Frame format ................................................................................................................................. 491
Table 18-7 USART interrupt request............................................................................................................... 508
Table 18-8 USART mode setting(1) ................................................................................................................. 509
Table 18-9 USART register overview.............................................................................................................. 509
Table 19-1 SPI interrupt request...................................................................................................................... 536
Table 19-2 Use the standard 8MHz HSE clock to get accurate audio frequency............................................. 546
Table 19-3 I2S interrupt request....................................................................................................................... 549
Table 19-4 SPI register overview..................................................................................................................... 550
Table 20-1 RTC feature support....................................................................................................................... 560
Table 20-2 RTC register overview................................................................................................................... 570
Table 21-1 Max and Min frequency supported by beeper and corresponding configure................................. 590
Table 21-2 Beeper register overview............................................................................................................... 591
Table 22-1 Examples of filter numbers............................................................................................................ 606
Table 22-2 Send mailbox register list.............................................................................................................. 608
Table 22-3 Receive mailbox register list ......................................................................................................... 608
Table 22-4 CAN register overview.................................................................................................................. 615
Table 23-1 Debug port pin............................................................................................................................... 641
Table 23-2 DBG register overview.................................................................................................................. 642