Nations N32G430 Series User manual

N32G430 series
32-bit ARM®Cortex®-M4 microcontroller
User manual V1.0

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Contents
Abbreviations in the text ...............................................................................................................................................28
List of abbreviations for registers .............................................................................................................................28
Available peripherals ................................................................................................................................................28
Memory and bus architecture.......................................................................................................................................29
System architecture...................................................................................................................................................29
Bus architecture .............................................................................................................................................29
Bus address mapping ..................................................................................................................................... 30
Boot management ..........................................................................................................................................34
Memory system ........................................................................................................................................................ 35
FLASH specification .....................................................................................................................................35
iCache ............................................................................................................................................................47
SRAM............................................................................................................................................................49
FLASH register description ...........................................................................................................................50
Power control (PWR) ....................................................................................................................................................58
General description................................................................................................................................................... 58
Power supply.................................................................................................................................................. 58
Power supply supervisor................................................................................................................................59
NRST.............................................................................................................................................................61
Power modes ............................................................................................................................................................61
SLEEP mode..................................................................................................................................................63
STOP0 mode.................................................................................................................................................. 64
STOP2 mode.................................................................................................................................................. 65
STANDBY mode........................................................................................................................................... 66
PWR registers...........................................................................................................................................................67
PWR register overview..................................................................................................................................67
Power control register (PWR_CTRL)............................................................................................................67
Power control status register (PWR_CTRLSTS)...........................................................................................69
Power control register 2(PWR_CTRL2)........................................................................................................71
Reset and clock control (RCC) .....................................................................................................................................73
General description................................................................................................................................................... 73
Reset Control Unit....................................................................................................................................................73
Power reset..................................................................................................................................................... 73
System reset................................................................................................................................................... 73
Backup domain reset......................................................................................................................................75
Clock control unit.....................................................................................................................................................75
Clock Tree Diagram.......................................................................................................................................76
HSE clock...................................................................................................................................................... 76
HSI clock .......................................................................................................................................................77

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PLL clock.......................................................................................................................................................78
LSE clock.......................................................................................................................................................78
LSI clock........................................................................................................................................................78
System clock (SYSCLK) selection................................................................................................................ 79
Clock security system (CLKSS) ....................................................................................................................79
LSE Clock security system (LSECSS) .......................................................................................................... 79
RTC clock..................................................................................................................................................80
Watchdog clock.......................................................................................................................................... 80
Clock output(MCO)................................................................................................................................... 80
RCC Registers ..........................................................................................................................................................81
RCC register overview................................................................................................................................... 81
Clock Control Register (RCC_CTRL)...........................................................................................................82
Clock Configuration Register (RCC_CFG)...................................................................................................84
Clock Interrupt Register (RCC_CLKINT).....................................................................................................87
APB2 Peripheral Reset Register (RCC_APB2PRST) ...................................................................................89
APB1 Peripheral Reset Register (RCC_APB1PRST) ...................................................................................91
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)....................................................................92
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN).................................................................94
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN).................................................................95
Backup Domain Control Register (RCC_BDCTRL)................................................................................. 97
Clock Control/Status Register (RCC_CTRLSTS).....................................................................................98
AHB Peripheral Reset Register (RCC_AHBPRST)................................................................................100
Clock Configuration Register 2 (RCC_CFG2)........................................................................................101
Retention Domain Control Register (RCC_RDCTRL) ...........................................................................102
PLL and HSI Configuration Register (RCC_PLLHSIPRE) ....................................................................103
AHB Peripheral Clock Enable Register 1 (RCC_AHB1CLKEN)........................................................... 103
GPIO andAFIO...........................................................................................................................................................105
Summary.................................................................................................................................................................105
Function description ...............................................................................................................................................106
I/O mode configuration................................................................................................................................106
Status after reset........................................................................................................................................... 111
Atomic bit set and reset................................................................................................................................ 111
External Interrupt /wakeup line.................................................................................................................... 112
Alternate function ........................................................................................................................................ 113
I/O configuration of peripherals................................................................................................................... 124
GPIO Locking mechanism...........................................................................................................................126
GPIO Registers.......................................................................................................................................................127
GPIOA register overview.............................................................................................................................127
GPIOB register overview............................................................................................................................. 129
GPIOC register overview.............................................................................................................................130
GPIOD register overview ............................................................................................................................132
GPIO port mode description register (GPIOx_PMODE).............................................................................133
GPIO port type definition (GPIOx_POTYPE) ............................................................................................ 134

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GPIO slew rate configuration register (GPIOx_SR)....................................................................................135
GPIO port pull-up/pull-down description register (GPIOx_PUPD) ............................................................ 135
GPIO port input data register (GPIOx_PID)................................................................................................136
GPIO port output data register (GPIOx_POD)........................................................................................ 137
GPIO port bit set/clear register (GPIOx_PBSC)...................................................................................... 137
GPIO port bit clear register (GPIOx_PBC) .............................................................................................138
GPIO port configuration lock register (GPIOx_ PLOCK) ......................................................................139
GPIO Alternate function low register (GPIOx_AFL)..............................................................................140
GPIO Alternate function high register (GPIOx_AFH) ............................................................................140
GPIO driver strength configuration register (GPIOx_ DS) ..................................................................... 141
AFIO Registers....................................................................................................................................................... 142
AFIO register overview ...............................................................................................................................142
Alternate function mapping configuration control register (AFIO_RMP_CFG).........................................144
External interrupt configuration register 1 (AFIO_EXTI_CFG1) ...............................................................144
External interrupt configuration register 2 (AFIO_EXTI_CFG2) ...............................................................151
External interrupt configuration register 3 (AFIO_EXTI_CFG3) ...............................................................158
External interrupt configuration register 4 (AFIO_EXTI_CFG4) ...............................................................165
5V tolerance configuration register (AFIO_TOL5V _CFG)........................................................................172
Analog filter configuration register 1 (AFIO_EFT_CFG1).........................................................................174
Analog filter configuration register 2 (AFIO_EFT_CFG2).........................................................................174
Digital glitch filter stage (glitch width) configuration register (AFIO_FILT_CFG)................................ 175
Digital glitch filter configuration register 1 (AFIO_DIGEFT_CFG1) .................................................... 176
Digital glitch filter configuration register 2 (AFIO_DIGEFT_CFG2) ....................................................176
Interrupts and events...................................................................................................................................................178
Nested vectored interrupt controller .......................................................................................................................178
SysTick calibration value register................................................................................................................ 178
Interrupt and exception vectors....................................................................................................................178
External interrupt/event controller (EXTI).............................................................................................................181
Introduction to EXTI.................................................................................................................................... 181
EXTI main features...................................................................................................................................... 181
Functional description..................................................................................................................................182
EXTI line mapping ...................................................................................................................................... 184
EXTI Registers.......................................................................................................................................................185
EXTI register overview................................................................................................................................185
Interrupt Mask Register(EXTI_IMASK)..................................................................................................... 185
Event Mask Register(EXTI_EMASK) ........................................................................................................ 186
Rising Edge Trigger Selection Register(EXTI_RT_CFG)...........................................................................186
Falling Edge Trigger Selection Register(EXTI_FT_CFG) ..........................................................................187
Software Interrupt Event Register(EXTI_SWIE) ........................................................................................187
Interrupt Request Pending Register(EXTI_PEND) .....................................................................................188
RTC Timestamp Selection Register(EXTI_TS_SEL).................................................................................. 188
DMA controller............................................................................................................................................................190

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Introduction ............................................................................................................................................................190
Main features..........................................................................................................................................................190
Block diagram ........................................................................................................................................................ 191
Function description ...............................................................................................................................................191
DMA operation ............................................................................................................................................ 191
Channel priority and arbitration...................................................................................................................192
DMA channels and number of transfers....................................................................................................... 192
Programmable data bit width, alignment and endians ................................................................................. 192
Peripheral/Memory address incrementation ................................................................................................ 194
Channel configuration procedure................................................................................................................. 194
Flow control................................................................................................................................................. 195
Circular mode ..............................................................................................................................................195
Error management........................................................................................................................................ 196
Interrupt ...................................................................................................................................................196
DMA request mapping.............................................................................................................................196
DMAregisters ........................................................................................................................................................199
DMA register overview................................................................................................................................ 199
DMA interrupt status register (DMA_INTSTS) .......................................................................................... 200
DMA interrupt flag clear register (DMA_INTCLR).................................................................................... 201
DMA channel x configuration register (DMA_CHCFGx)...........................................................................202
DMA channel x transfer number register (DMA_TXNUMx) .....................................................................203
DMA channel x peripheral address register (DMA_PADDRx)...................................................................204
DMA channel x memory address register (DMA_MADDRx) ....................................................................204
DMA channel x channel request select register (DMA_CHSELx)..............................................................205
CRC calculation unit ...................................................................................................................................................207
CRC introduction....................................................................................................................................................207
CRC main features..................................................................................................................................................207
CRC32 module ............................................................................................................................................207
CRC16 module ............................................................................................................................................207
CRC function description .......................................................................................................................................208
CRC32 .........................................................................................................................................................208
CRC16 .........................................................................................................................................................208
CRC registers..........................................................................................................................................................209
CRC register overview................................................................................................................................. 209
CRC32 data register (CRC_CRC32DAT).................................................................................................... 209
CRC32 independent data register (CRC_CRC32IDAT)..............................................................................209
CRC32 control register (CRC_CRC32CTRL).............................................................................................210
CRC16 control register (CRC_CRC16CTRL).............................................................................................210
CRC16 input data register (CRC_CRC16DAT) .......................................................................................... 211
CRC cyclic redundancy check code register (CRC_CRC16D) ................................................................... 211
LRC result register (CRC_LRC)..................................................................................................................212
Advanced-control timers (TIM1 and TIM8) .................................................................................................................213

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TIM1 and TIM8 introduction ....................................................................................................................................213
Main features of TIM1 and TIM8 ..............................................................................................................................213
TIM1 and TIM8 function description ........................................................................................................................ 215
Time-base unit ............................................................................................................................................... 215
Counter mode ................................................................................................................................................ 216
Repetition counter ......................................................................................................................................... 226
Clock selection .............................................................................................................................................. 228
Capture/compare channels .............................................................................................................................232
Input capture mode ........................................................................................................................................234
PWM input mode ..........................................................................................................................................235
Forced output mode ....................................................................................................................................... 236
Output compare mode .................................................................................................................................... 237
PWM mode ............................................................................................................................................... 238
One-pulse mode ........................................................................................................................................ 241
Clearing the OCxREF signal on an external event ...................................................................................... 242
Complementary outputs with dead-time insertion .......................................................................................243
Break function ...........................................................................................................................................245
Debug mode ..............................................................................................................................................247
TIMx and external trigger synchronization ................................................................................................. 247
Timer synchronization ...............................................................................................................................251
6-step PWM generation .............................................................................................................................251
Encoder interface mode .............................................................................................................................252
Interfacing with Hall sensor ....................................................................................................................... 255
TIMx register description(x=1, 8) .............................................................................................................................257
Register overview ........................................................................................................................................ 257
Control register 1 (TIMx_CTRL1) ..............................................................................................................260
Control register 2 (TIMx_CTRL2) ..............................................................................................................262
Slave mode control register (TIMx_SMCTRL)...........................................................................................265
DMA/Interrupt enable registers (TIMx_DINTEN)......................................................................................267
Status registers (TIMx_STS) .......................................................................................................................269
Event generation registers (TIMx_EVTGEN).............................................................................................271
Capture/compare mode register 1 (TIMx_CCMOD1).................................................................................272
Capture/compare mode register 2 (TIMx_CCMOD2).................................................................................275
Capture/compare enable registers (TIMx_CCEN)................................................................................... 277
Counters (TIMx_CNT)............................................................................................................................280
Prescaler (TIMx_PSC).............................................................................................................................280
Auto-reload register (TIMx_AR)............................................................................................................. 281
Repeat count registers (TIMx_REPCNT)................................................................................................281
Capture/compare register 1 (TIMx_CCDAT1)........................................................................................ 281
Capture/compare register 2 (TIMx_CCDAT2)........................................................................................ 282
Capture/compare register 3 (TIMx_CCDAT3)........................................................................................ 283
Capture/compare register 4 (TIMx_CCDAT4)........................................................................................ 284
Break and Dead-time registers (TIMx_BKDT)....................................................................................... 285

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DMA Control register (TIMx_DCTRL) ..................................................................................................286
DMA transfer buffer register (TIMx_DADDR) ...................................................................................... 287
Capture/compare mode registers 3(TIMx_CCMOD3) ............................................................................288
Capture/compare register 5 (TIMx_CCDAT5)........................................................................................ 288
Capture/compare register 6 (TIMx_CCDAT6)........................................................................................ 289
Capture/compare register 7 (TIMx_CCDAT7)........................................................................................289
Capture/compare register 8 (TIMx_CCDAT8)........................................................................................ 290
Capture/compare register 9 (TIMx_CCDAT9)........................................................................................ 290
Break Filter (TIMx_BRKFILT)...............................................................................................................291
General-purpose timers (TIM2, TIM3, TIM4 and TIM5) ..........................................................................................293
General-purpose timers introduction ........................................................................................................................ 293
Main features of General-purpose timers ................................................................................................................. 293
General-purpose timers description ......................................................................................................................... 294
Time-base unit ...........................................................................................................................................294
Counter mode ............................................................................................................................................ 295
Clock selection ..........................................................................................................................................301
Capture/compare channels .........................................................................................................................305
Input capture mode .................................................................................................................................... 308
PWM input mode ...................................................................................................................................... 309
Forced output mode ...................................................................................................................................310
Output compare mode ............................................................................................................................... 311
PWM mode ............................................................................................................................................... 312
One-pulse mode ........................................................................................................................................ 315
Clearing the OCxREF signal on an external event ...................................................................................... 316
Debug mode ..............................................................................................................................................317
TIMx and external trigger synchronization ................................................................................................. 317
Timer synchronization ...............................................................................................................................321
Encoder interface mode .............................................................................................................................325
Interfacing with Hall sensor ....................................................................................................................... 328
TIMx register description(x=2, 3, 4 and 5) ............................................................................................................... 329
Register overview.................................................................................................................................... 329
Control register 1 (TIMx_CTRL1).......................................................................................................... 330
Control register 2 (TIMx_CTRL2).......................................................................................................... 333
Slave mode control register (TIMx_SMCTRL).......................................................................................334
DMA/Interrupt enable registers (TIMx_DINTEN) .................................................................................336
Status registers (TIMx_STS) ................................................................................................................... 337
Event generation registers (TIMx_EVTGEN).........................................................................................339
Capture/compare mode register 1 (TIMx_CCMOD1).............................................................................340
Capture/compare mode register 2 (TIMx_CCMOD2).............................................................................343
Capture/compare enable registers (TIMx_CCEN)...................................................................................344
Counters (TIMx_CNT)............................................................................................................................346
Prescaler (TIMx_PSC).............................................................................................................................346
Auto-reload register (TIMx_AR)............................................................................................................. 346

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Capture/compare register 1 (TIMx_CCDAT1)........................................................................................ 347
Capture/compare register 2 (TIMx_CCDAT2)........................................................................................ 347
Capture/compare register 3 (TIMx_CCDAT3)........................................................................................348
Capture/compare register 4 (TIMx_CCDAT4)........................................................................................ 348
DMA Control register (TIMx_DCTRL) ..................................................................................................349
DMA transfer buffer register (TIMx_DADDR) ...................................................................................... 350
Channel 1 filter register (TIMx_C1FILT)................................................................................................350
Channel 2 filter register (TIMx_C2FILT)................................................................................................351
Channel 3 filter register (TIMx_C3FILT)................................................................................................352
Channel 4 filter register (TIMx_C4FILT)................................................................................................353
Channel filter Output register (TIMx_FILTO)......................................................................................... 354
Basic timers (TIM6) .....................................................................................................................................................355
Basic timers introduction ........................................................................................................................................355
Main features of Basic timers ..................................................................................................................................355
Basic timers description ..........................................................................................................................................355
Time-base unit ...........................................................................................................................................355
Counter mode ............................................................................................................................................ 356
Clock selection ..........................................................................................................................................359
Debug mode ..............................................................................................................................................359
TIMx register description(x=6) ...............................................................................................................................359
Register overview.................................................................................................................................... 360
Control Register 1 (TIMx_CTRL1).........................................................................................................360
DMA/Interrupt Enable Registers (TIMx_DINTEN) ............................................................................... 361
Status Registers (TIMx_STS)..................................................................................................................362
Event Generation registers (TIMx_EVTGEN)........................................................................................362
Counters (TIMx_CNT)............................................................................................................................363
Prescaler (TIMx_PSC).............................................................................................................................363
Automatic reload register (TIMx_AR) ....................................................................................................363
Low Power Timer (LPTIM) .........................................................................................................................................364
Introduction ..........................................................................................................................................................364
Main Features....................................................................................................................................................... 364
Block diagram ...................................................................................................................................................... 365
Function description .............................................................................................................................................365
LPTIM clocks and on-off control ............................................................................................................365
Prescalar...................................................................................................................................................366
Glitch filter ..............................................................................................................................................366
Timer enable ............................................................................................................................................ 367
Trigger multiplexer..................................................................................................................................367
Operating mode .......................................................................................................................................368
Waveform generation............................................................................................................................... 371
Register update ........................................................................................................................................372
Counter mode...........................................................................................................................................373

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Encoder mode..........................................................................................................................................373
Non-orthogonal encoder mode ................................................................................................................375
Timeout function......................................................................................................................................376
LPTIM interrupts..................................................................................................................................... 377
LPTIM registers....................................................................................................................................................378
LPTIM register overview......................................................................................................................... 378
LPTIM interrupt and status register (LPTIM_INTSTS)..........................................................................378
LPTIM interrupt clear register (LPTIM_INTCLR) .................................................................................379
LPTIM interrupt enable register (LPTIM_INTEN)................................................................................. 380
LPTIM configuration register (LPTIM_CFG)......................................................................................... 381
LPTIM control register (LPTIM_CTRL) ................................................................................................ 384
LPTIM compare register (LPTIM_COMP).............................................................................................385
LPTIM auto-reload register (LPTIM_ARR)............................................................................................385
LPTIM counter register (LPTIM_CNT)..................................................................................................385
LPTIM option register (LPTIM_OPT) ....................................................................................................386
Independent watchdog (IWDG) ...............................................................................................................................387
Introduction ..........................................................................................................................................................387
Main features........................................................................................................................................................387
Function description .............................................................................................................................................388
Register access protection........................................................................................................................388
Debug mode.............................................................................................................................................389
IWDG Freeze........................................................................................................................................... 389
User Interface .......................................................................................................................................................389
Operate Flow ........................................................................................................................................... 389
IWDG configuration flow........................................................................................................................390
IWDG registers.....................................................................................................................................................390
IWDG register overview..........................................................................................................................390
IWDG Key Register (IWDG_KEY)........................................................................................................391
IWDG Pre-Scaler Register (IWDG_PREDIV)........................................................................................391
IWDG Reload Register (IWDG_RELV) ................................................................................................. 392
IWDG Status Register (IWDG_STS)...................................................................................................... 392
Window watchdog (WWDG)....................................................................................................................................394
Introduction ..........................................................................................................................................................394
Main features........................................................................................................................................................394
Function description .............................................................................................................................................394
Timing for refresh watchdog and interrupt generation .........................................................................................395
Debug mode..........................................................................................................................................................396
User Interface .......................................................................................................................................................396
WWDG configuration flow .....................................................................................................................396
WWDG registers ..................................................................................................................................................397
WWDG register Map............................................................................................................................... 397
WWDG control register (WWDG_CTRL).............................................................................................. 397

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WWDG config register (WWDG_CFG) .................................................................................................398
WWDG status register (WWDG_STS) ................................................................................................... 398
Analog to digital conversion (ADC) .............................................................................................................................399
Introduction ..........................................................................................................................................................399
Main features ..........................................................................................................................................................399
Function Description ...............................................................................................................................................400
ADC clock ................................................................................................................................................401
ADC switch control ...................................................................................................................................402
Channel selection ......................................................................................................................................402
Internal channel ....................................................................................................................................... 403
Single conversion mode ............................................................................................................................. 404
Continuous conversion mode ....................................................................................................................404
Timing diagram .........................................................................................................................................404
Analog watchdog ......................................................................................................................................405
Scanning mode ..........................................................................................................................................406
Injection channel management ...................................................................................................................406
Discontinuous mode ..................................................................................................................................407
Calibration............................................................................................................................................................408
Data aligned ...........................................................................................................................................................408
Programmable channel sampling time .....................................................................................................................410
Externally triggered conversion ............................................................................................................................... 410
DMA requests....................................................................................................................................................... 411
Temperature sensor ................................................................................................................................................. 411
Temperature sensor using flow................................................................................................................ 412
ADC interrupt..................................................................................................................................................... 413
ADC registers......................................................................................................................................................413
ADC register overview .............................................................................................................................414
ADC status register (ADC_STS) ................................................................................................................415
ADC control register 1 (ADC_CTRL1) .................................................................................................. 416
ADC control register 2 (ADC_CTRL2) .................................................................................................. 418
ADC sampling time register 1 (ADC_SAMPT1)....................................................................................420
ADC sampling time register 2 (ADC_ SAMPT2)................................................................................... 421
ADC injected channel data offset register x (ADC_JOFFSETx) (x=1…4)............................................. 421
ADC watchdog high threshold register (ADC_WDGHIGH) .......................................................................422
ADC watchdog low threshold register (ADC_WDGLOW) .........................................................................422
ADC regular sequence register 1 (ADC_RSEQ1)...............................................................................423
ADC regular sequence register 2 (ADC_RSEQ2)...............................................................................423
ADC regular sequence register 3 (ADC_RSEQ3)...............................................................................424
ADC Injection sequence register (ADC_JSEQ) .......................................................................................424
ADC injection data register x (ADC_JDATx) (x= 1…4) .................................................................... 425
ADC regulars data register (ADC_DAT) ................................................................................................425
ADC differential mode selection register (ADC_DIFSEL).................................................................426
ADC calibration factor (ADC_CALFACT).........................................................................................426