Infineon Technologies CYPRESS Traveo Series User manual

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S6J3350 Series
32-bit Microcontroller
Traveo™ Family
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-10634 Rev. *J Revised August 5, 2020
The Traveo™ family expands the company’s automotive applications, scalability and high performance into one line-up and at the
same time adds new features to fulfill the latest requirements of the automotive industry. Based on the powerful Arm® Cortex®- R5F
core in single operations, it offers state-of-the-art real time performance, safety and security features. The family supports the latest
in-car networks and offers high performance graphics engines optimized for a minimum memory footprint and embeds dedicated
features to increase data security in the car.
S6J3350 is a microcontroller series for body and gateway.
Features
◼System
32bit Arm Cortex-R5F CPU core at up to 240 MHz
General purpose I/O port: up to 148
12-bit A/D converter: up to 64 channels
External interrupt: up to 24 channels
Base timer: up to 64 channels
32-bit reload timer: up to 6 channels
32-bit free-run timer: 8 channels
Input capture unit: 12 channels
Output compare unit: 12 channels
Built-in CR oscillator
Real-time clock
DMA controller: 16 channels
JTAG debug interface
◼Communication
CAN-FD: up to 8 channels
Multi-function serial interface: up to 12 channels,
selectable protocol: UART, CSIO, LIN and I2C
Ethernet AVB MAC
◼Memory
HyperBus™ Memory interface
DDR High Speed SPI
External BUS interface
◼Security and Safety
Secure Hardware Extension – SHE
Safety features, such as MPU, TPU, ECC and others
CRC generator: 1 channel
Watchdog timer with window function
Low voltage detector
Clock supervisor for all source clocks
Applications
◼Body Control Module(BCM)
◼Lighting
◼Gateway

Document Number: 002-10634 Rev. *J Page 2 of 307
S6J3350 Series
Table of Contents
1. Overview........................................................................3
1.1 Overview ...................................................................3
1.2 Document Definition..................................................3
2. Function List .................................................................4
2.1 Function List..............................................................4
2.2 Optional Function......................................................6
3. Product Description......................................................9
3.1 Overview ...................................................................9
3.2 Product Description...................................................9
4. Package and Pin Assignment....................................14
4.1 Pin Assignment .......................................................14
4.2 Package Dimensions...............................................17
5. IO Circuit Type ............................................................21
5.1 I/O Circuit Type .......................................................21
5.2 Note.........................................................................25
6. Port Description..........................................................26
6.1 Port Description List ................................................26
6.2Remark................................................................... 44
7. Port Configuration...................................................... 45
7.1 Resource Input Configuration Module .................... 45
7.2 Port Output Function Configuration ...................... 135
8. Precautions and Handling Devices......................... 146
8.1 Handling Precautions............................................ 146
8.2 Handling Devices.................................................. 149
9. Electric Characteristics............................................ 151
9.1 Electrical Characteristics....................................... 151
10.Acronyms.................................................................. 243
11.Ordering Information................................................ 244
12.Errata......................................................................... 245
13.Appendix................................................................... 247
13.1 Application 1: JTAG Tool Connection................... 247
14.Major Changes.......................................................... 248
Document History.......................................................... 305
Sales, Solutions, and Legal Information...................... 307

Document Number: 002-10634 Rev. *J Page 3 of 307
S6J3350 Series
1. Overview
1.1 Overview
S6J3350 is a microcontroller series which is to be applied to automotive systems representative of body and gateway.
1.2 Document Definition
The related documents of S6J3350 are as follows:
Table 1-1: Document Definition
Document Type
Definition
Primary User
Document Code
S6J3350 Datasheet
This document.
The function and its characteristics are
specified quantitatively.
Investigator and Hardware
Engineer
002-10634
S6J3300 Hardware
Manual
S6J3300 Series 32-bit Microcontroller
Traveo™ Family Hardware Manual
The function and its operation of
S6J3300 series are described.
Software Engineer
002-10185
Traveo™ Platform
Hardware Manual
32-Bit Microcontroller Traveo™ Family
S6J33xx, S6J34xx, S6J35xx Series
Hardware Manual Platform Part
The function and its operation of CPU
core platform are described.
Software Engineer
002-07884
Application Note
The reference software, sample
application, the reference board design,
and so on are explained.
Software and Hardware Engineer
002-04455
002-04446
002-09716
002-04452
002-04096
002-12061
002-02495
Notes:
−Refer all documents for the system development.
−"Primary user" is a most likely an engineer for whom the document is the most useful.
−The description of the datasheet and the S6J3300 Hardware Manual should precede the duplicated description of TraveoTM
Platform Hardware Manual.
−TraveoTM Platform Hardware Manual is expected to be used as dictionary of platform specification.

Document Number: 002-10634 Rev. *J Page 4 of 307
S6J3350 Series
2. Function List
2.1 Function List
This table shows the functions which are implemented in S6J3350 series.
Table 2-1: Function List
Function
Description
Remarks
CPU core
Arm Cortex R5F
FPU
Available
PPU
Available
MPU
Available
TPU
Available
Endian
Little endian
Core clock frequency
240 MHz
HPM bus frequency
200 MHz
LLPM bus frequency
240 MHz
Resource clock frequency
80 MHz (Max)
Embedded CR oscillation
Slow clock:100 kHz,
Fast clock: 4 MHz
(Center frequency)
See 9.1.4.1
PLL
PLL0, 1, 2, 3
SSCG PLL
SSCG0, 1, 2, 3
Clock supervisor
Available
DMA
16 ch
Boot-ROM
16 Kbyte
JTAG
Available
Data cache
16 Kbyte
Instruction cache
16 Kbyte
Program FLASH
Option
See 2.2.1
Work FLASH
112 Kbyte
TCRAM
128 Kbyte
System SRAM
384 Kbyte
Backup RAM
32 Kbyte
Security (SHE)
Option
Low latency interrupt
Available
Power domain
5 domains
External power supply
5 V(VCC5, VCC53),
3 V(VCC3, VCC53),
1.2 V(VCC12)
Embedded LDO power supply
for 5.0V
Available
Low voltage detection of
external power supply
Available
Low voltage detection of
internal LDO output
Available
Hardware watchdog timer
Available
Software watchdog timer
Available
Package
Option
See 2.2.1
AUTOSAR
AUTOSAR 4.0.3
General Purpose I/O
Option
See 2.2.3
Up/down counter
2 ch
I/O timer
(FRT 5 ch x ICU 6 ch x OCU 6 ch) + (FRT 3 ch x ICU 6 ch x OCU 6
ch)
32bit Reload timer
6 ch
Real time clock
Available
Automatic calibration
Base timer
32 units (64 ch)
12bit-A/D converter
2 unit - 64 input ports (Max)
See 2.2.3
CRC
4 units
Programmable CRC
1 unit

Document Number: 002-10634 Rev. *J Page 5 of 307
S6J3350 Series
Function
Description
Remarks
Source clock timer
4 ch
NMI
Available
External interrupt
24 ch
Internal interrupt
512 vectors
DDR HSSPI
1 ch
A type of Quad SPI
Hyper BUS
1 ch
See the AC
specification on
9.1.4.16
Multi-function serial interface
12 ch
CAN-FD
8 ch
CAN-FD RAM (ECC
supported)
16 KB/ch
It equivalents to 128 message buffer per channel of MCAN module
Ethernet AVB
1 unit
See 2.2.1
External BUS
1 ch
Notes:
−The options are described in 2.2 Optional Function.

Document Number: 002-10634 Rev. *J Page 6 of 307
S6J3350 Series
2.2 Optional Function
2.2.1 Basic Option
This figure shows the optional function and the part number relations of the series.
Figure 2-1: Option and Part Number for S6J3350 Series
Notes:
−This table only shows the relations between the optional function and the part numbers. That is, all products are not
necessarily available for orders. See 11 Ordering Information, and confirm actual availabilities of products.
−The main RAM size is configured as follows according to Digit.
E: TCRAM 128KB + System-RAM 384KB
D: TCRAM 128KB + System-RAM 256KB
x x x x x x x x x x xx33J6S
Ordering options 7 digit
Revision:
Digit
C
D
E
Description
Fixed Operation frequency of embedded Program Flash and CPU,
Fixed Stabilization time for sub oscillator
Fixed TCFLASH Sector Write Permission and Data Retention after Reset
Leakage current improvement
Option:
Digit
S
B
U
SHE
ONA
MK_CEER*
OFFC
D
Fixed to
Enable
VCC5 DVCC
5V
5V
3V
3V
5V
5V
3V
3V
F
V
E
G
H
T
ON
OFF
Selectable
5V
5V
3V
3V
5V
5V
3V
3V
* Chip Erase Enable Register
Pin count:
Digit
H
K
J
Pin Count
144pin
208pin
176pin
Memory Size:
Digit
D
Flash
4,160KBE
RAM
512KB 16+16KB112KB
Program Work Main Backup
3,136KB 384KB 16+16KB112KB
Function:
Digit
5
Ethernet
Yes
Product series
Identifier: Automotive MCU

Document Number: 002-10634 Rev. *J Page 7 of 307
S6J3350 Series
2.2.2 ID
ID is specified for each function digit and revision which is defined at Figure 2-1.
Function Digit
Revision
Chip ID
JTAG ID
S,U,T,V
C
0x10122100
0x1000B5CF
D, E
0x10122200
A,C,E,G
C
0x10128100
D, E
0x10128200
B,D,F,H
C
0x10120100
D, E
0x10120200
2.2.3 Restriction
Some functions have restrictions which depend on package pin counts.
Table 2-2: Pin Restriction
Function
TEQFP176
TEQFP144
Analog input port (12bit-ADC)
AN0~3, AN19~20,
AN22~23, AN27, AN33~38,
AN48
AN0~7, AN10~11,
AN14~15, AN19~20,
AN22~23, AN25~30,
AN33~38, AN48
General Purpose I/O
P4_00 ~ P4_31
P4_00 ~ P4_31
P3_00 ~ P3_31
CAN
RX0_2, TX0_2
RX3_2, TX3_2
RX4_0, TX4_0
RX7_0, TX7_0
RX7_1, TX7_1
RX0_1, TX0_1
RX0_2, TX0_2
RX1_1, TX1_1
RX2_1, TX2_1
RX3_1, TX3_1
RX3_2, TX3_2
RX4_0, TX4_0
RX5_1, TX5_1
RX6_1, TX6_1
RX7_0, TX7_0
RX7_1, TX7_1
BaseTimer
PPG16/17/18/19_TOUT0_0
PPG16/17/18/19_TOUT2_0
PPG20/21/22/23_TOUT0_0
PPG20/21/22/23_TOUT2_0
PPG24/25/26/27_TOUT0_0
PPG24/25/26/27_TOUT2_0
PPG28/29/30/31_TOUT0_0
PPG28/29/30/31_TOUT2_0
PPG16/17/18/19/20/21_TIN1_0
PPG22/23/24/25/26/27_TIN1_0
PPG28/29/30/31_TIN1_0
PPG16/17/18/19_TOUT0_0
PPG16/17/18/19_TOUT2_0
PPG20/21/22/23_TOUT0_0
PPG20/21/22/23_TOUT2_0
PPG24/25/26/27_TOUT0_0
PPG24/25/26/27_TOUT2_0
PPG28/29/30/31_TOUT0_0
PPG28/29/30/31_TOUT2_0
PPG16/17/18/19/20/21_TIN1_0
PPG22/23/24/25/26/27_TIN1_0
PPG28/29/30/31_TIN1_0
PPG4/5/6/7/8/9_TOUT0_1
PPG4/5/6/7/8/9_TOUT2_1
PPG10/11/12/13/15_TOUT0_1
PPG10/11/12/13/14/15_TOUT2_1
PPG0/1/2/3/4/5_TIN1_1
PPG6/7/8/9/10/11_TIN1_1
PPG12/13/14/15_TIN1_1
ExtBus
-
MDQM1
MAD15~21
MDATA8~15

Document Number: 002-10634 Rev. *J Page 8 of 307
S6J3350 Series
Function
TEQFP176
TEQFP144
External Interrupt
EINT1_4, EINT1_5
EINT2_1, EINT2_2
EINT3_2, EINT4_2
EINT5_4, EINT5_5
EINT6_4, EINT7_1
EINT7_4, EINT8_4
EINT8_5, EINT9_1
EINT10_1, EINT10_4
EINT10_5, EINT13_2
EINT13_3, EINT14_2
EINT14_3, EINT15_3
EINT16_1, EINT16_3
EINT16_4, EINT19_4
EINT20_3, EINT21_3
EINT22_1, EINT22_3
EINT23_3, EINT23_4
EINT0_4, EINT1_1
EINT1_4, EINT1_5
EINT2_1, EINT2_2
EINT2_4, EINT3_1
EINT3_2, EINT3_4
EINT4_2, EINT4_4
EINT5_4, EINT5_5
EINT6_1, EINT6_4
EINT7_1, EINT7_4
EINT8_1, EINT8_4
EINT8_5, EINT9_1
EINT9_2, EINT10_1
EINT10_2, EINT10_4
EINT10_5, EINT11_2
EINT11_5, EINT12_1
EINT12_2, EINT12_5
EINT13_2, EINT13_3
EINT13_5, EINT14_1
EINT14_2, EINT14_3
EINT14_5, EINT15_2
EINT15_3, EINT16_1
EINT16_2, EINT16_3
EINT16_4, EINT16_5
EINT17_1, EINT17_3
EINT17_5, EINT18_1
EINT18_3, EINT18_5
EINT19_1, EINT19_3
EINT19_4, EINT20_1
EINT20_2, EINT20_3
EINT21_1, EINT21_3
EINT22_1, EINT22_3
EINT23_3, EINT23_4
Notes:
−See multiplexed functions on pin assignment sheet.
−The optional restriction will be added without notification.

Document Number: 002-10634 Rev. *J Page 9 of 307
S6J3350 Series
3. Product Description
3.1 Overview
This chapter explains the product features of S6J3350 series. The description of this chapter should precede the duplicated
description on Traveo™ Platform Hardware Manual.
3.2 Product Description
The table shows features.
Table 3-1: Product Features
Feature
Description
Technology
40 nm CMOS technology with embedded FLASH
Fully automotive qualified according to ISO/TS 16949 and AEC-Q100
Developed according to ISO26262, safety target ASIL-B
Functional Safety
The product series has some functional safety features suited for ASIL-B application.
Peripherals
See function list.
Power Domain (PD)
See the Traveo™ Platform Hardware Manual and chapter STATE TRANSITION in detail.
The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0,
PD4_1 and PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series,
and "0" is always read from the reset factor flags of them.
This series doesn't support partial wakeup for PD6.
Debug and Trace
See the Traveo™ Platform Hardware Manual in detail.
−Standard 5-pin JTAG interface
−4 kB Embedded Trace Buffer
4-bit trace support for TEQFP package.
System Control
See the Traveo™ Platform Hardware Manual in detail.
Main and sub oscillator is available.
−A wide range of 3.6 – 16 MHz is available for main oscillator
−32 KHz is available for sub oscillator
Sub clock is enable/disable by register settings
Clock
See the Traveo™ Platform Hardware Manual in detail.
CLK_CLKO (Clock Output Function) is supported.
Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value)
Embedded CR oscillation
See the Traveo™ Platform Hardware Manual in detail.
Stabilization time is as followings.
−30 us or more for 4 MHz (Fast clock)
−30 us or more for 100 kHz (Slow clock)
Clock Supervisor
See the Traveo™ Platform Hardware Manual in detail.
This product series doesn’t support clock supervisor output port. (Related register and internal
circuit is implemented.)
Reset
RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input)
−Occurrence factor: Simultaneously inputting “L” level to RSTX pin and inputting “L” level to MD
pin
−Release factor: Inputting “H” level to RSTX pin
See the Traveo™ Platform Hardware Manual in detail.
Following resets are not mounted on this device.
−SRSTX (and nSRST pin)
The product series does not support EX5VRST and writing EX5VRSTCNT bits in
SYSC0_SPECFGR has no effect.

Document Number: 002-10634 Rev. *J Page 10 of 307
S6J3350 Series
Feature
Description
Hardware watchdog
See the Traveo™ Platform Hardware Manual in detail.
Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the
bit
ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1).
The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and
internal circuit is implemented.)
Standby mode
See the Traveo™ Platform Hardware Manual in detail.
Standby mode with 5 V (or 3 V) single external power supply is available.
Turning off the 1.2 V external power supply in standby mode is available.
The long term pulse of the indicator PWM can be outputted during RTC Standby mode.
PLL / SSCG PLL
See the Traveo™ Platform Hardware Manual in detail.
Use case assumption is following.
PLL
−Peripherals
−Trace clock
SSCG
−CPU core
−Hyper BUS
−DDR-HSSPI
Product supports down spread and center spread modes with the conditions defined in 9.1.4.3
"Internal Clock Timing".
Stabilization time is as follows.
−100 us for PLL
−200 us for SSCG
External Interrupts
See the Traveo™ Platform Hardware Manual in detail.
NMI
See the Traveo™ Platform Hardware Manual in detail.
1 NMI pin.
Memory Protection
MPU16 AHB: See the Traveo™ Platform Hardware Manual in detail.
MPU for AXI: ch.0
MPU for AHB: ch.1
Additional MPU for Ethernet AVB. They are described on the chapter of MPU for AHB and MPU
for AXI
To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,
− Lock: 0x112ABB56
− Unlock: 0xACCABB56
Peripheral Protection
See the Traveo™ Platform Hardware Manual in detail.
Protected peripherals are described in the base address map.
Internal Memories
System SRAM
384 kByte
1 wait cycle is necessary for RAM read at over 120 MHz.
Internal Memories
TCRAM
128 kByte
Internal Memories
Backup RAM
32 kByte
Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the
memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM
is not supported and cannot be used.

Document Number: 002-10634 Rev. *J Page 11 of 307
S6J3350 Series
Feature
Description
Embedded
Program/Work Flash
Memory
Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80 MHz or less.
0-wait-cycle: 80 MHz or less.
1-wait-cycle: 160 MHz or less.
2-wait-cycle: more than 160 MHz.
Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5 MHz or less.
6-wait-cycle: 80 MHz or less.
12-wait-cycle: 160 MHz or less.
The wait-cycle setting see the Traveo™ Platform Hardware Manual in details.
The CLK_FCLK maximum frequency should be referred in 9.1.4.3.
Erase suspend is supported. Reading and writing to the other sector are possible when Flash
Erase is suspended.
Serial Flash programing and Parallel Flash programing are supported.
Margin mode is not supported.
Internal Power Domain
PD1: Always ON
PD2: Cortex R5F platform/ additional peripherals
PD4: Backup RAM in Always On domain
PD6: Peripherals in Always On domain
* The chapter of the block diagram explains in detail.
Power Supply
5 V, and 3 V, 1.2 V external power supply is required.
Built in LDO provides internal power supply for Always On region (PD1).
1.2 V external power supply control pin is supported.
3 V external power supply could be controlled by GPIO.
There are constraints of power on/off sequence.
Low Voltage Detection
LVD for external voltage is supported.
LVD for internal voltage is supported.
See 9.1.4.11 and 9.1.4.12 .
Low voltage detection for
RAM retention (RVD)
RVD for RAM retention is effective during the standby mode only. That is, it is only for the
Backup RAM of 32 KB that the function is available.
Resource inter-connect
The output signal of some resources can be inputted to the other resource.
I/O Ports
5 V general purpose I/O
3 V general purpose I/O
Multi input level and multi output drivability
Pull-up, pull-down function is available.
Resource input and output is multiplexed.
+B input is allowed many pins of 3.3 V, 5 V and 3.3 V/5 V I/O domain.
A/D Converter
12 bit resolution, 2 unit(Unit0 is possible to select channels 0-31. Unit1 is possible to select
channels 32-63.)
64 channels of analog input for TEQFP208
48 channels of analog input for TEQFP176
35 channel of analog input for TEQFP144
External trigger and timer trigger are available.
The description of the A/D converter function should be referred in the S6J3300 Hardware
Manual. Though the chapter of I/O port in Traveo™ Platform Hardware Manual describes
another A/D converter function, do not refer it.
A/D Channel Control Register (ADC12Bn_CHCTRL0)[bit5:0] ANIN[5:0]: Analog Input Selection
bits.
This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111).
AN39 to AN63 are not support for S6J335xxAx, S6J335xxCx, S6J335xxEx, and S6J335xxGx
option.
CRC
See the Traveo™ Platform Hardware Manual in detail.
Programmable CRC
DMA support

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S6J3350 Series
Feature
Description
Base Timer
See the Traveo™ Platform Hardware Manual in detail.
A unit consists of a pair of 16bit base timers. 32 units, that is, 64 channels of base timers are
available.
Reload Timer
See the Traveo™ Platform Hardware Manual in detail.
I/O Timer
See the Traveo™ Platform Hardware Manual in detail.
Up/Down Counter
See the Traveo™ Platform Hardware Manual in detail.
Multi-Functional Serial
(MFS)
See the Traveo™ Platform Hardware Manual in detail.
Only 2 ports of MFS have the dedicated I/O for I2C.
See I2C timing in 9.1.4.6 Multi-Function Serial in detail.
The I2C is not designed to be hot swappable.
CTS/RTS is not mounted (hardware flow control is not supported for this series.)
CAN-FD
Flexible data rate is supported.
16 KB/ch of message RAM is available.
The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function
of the message RAM is not supported for this device. Therefore, CAN FD ECC Error Insertion
Control Register (FDFECR) is not writeable.
Real Time Clock (RTC)
with auto-calibration
See the TraveoTM Platform Hardware Manual in detail.
DDR High Speed SPI
ch.0: HSSPI as a MCU peripheral
Hyper BUS I/F
ch.0: Hyper Bus as a MCU peripheral
The following register is not supported and cannot be used.
−Controller Status Register (HYPERBUSIn_CSR)
−Interrupt Enable Register (HYPERBUSIn_IEN)
−Interrupt Status Register (HYPERBUSIn_ISR)
−Write Protection Register (HYPERBUSIn_WPR)
−Test Register (HYPERBUSIn_TEST)
GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can
select using HyperBus of Traveo™ Platform Hardware Manual.
External Interrupt Capture
Unit (EICU)
See the TraveoTM Platform Hardware Manual in detail.
Ethernet AVB
10/100 Mbps
MII-Interface
Supports Audio-Video Bridging (AVB)
SHE
See the Traveo™ Platform Hardware Manual in detail.
Source Clock Timer
See the Traveo™ Platform Hardware Manual in detail.
External BUS
TEQFP208: 22 bit address and 16 bit data
TEQFP176: 22 bit address and 16 bit data
TEQFP144: 15 bit address and 8 bit data
Power Supply Control
(PSC)
PSC (PSC_1) output is used for external 1.2 V power supply module control and automatically
switched with the following condition.
"High": Request to supply VCC12
- "Power ON Reset" is released
- CPU wakes up from PSS shutdown mode
"Low": Request to stop supplying VCC12
- CPU transfers from RUN mode to PSS shutdown mode.
For timing chart of output signals include PSC in detail, see the "S6J3300 Hardware Manual"
and chapter "State Transition"

Document Number: 002-10634 Rev. *J Page 13 of 307
S6J3350 Series
3.2.1 Ethernet
The following functions are not supported.
Functions
Remarks
External FIFO Interface
Additional Low Latency TX FIFO Interface for DMA configurations
MAC Transmit Block
- half-duplex
- collision
- back pressure
MAC Filtering Block
- external address match
- Wakeup On Lan
Energy Efficient Ethernet support
LPI Operation in Cadence IP
PHY Interface
- GMII
- SGMII
- TBI
10/100/1000 Operation
- 1000 M
SGMII Operation
Jumbo Frames
Physical Control Sub-Layer

Document Number: 002-10634 Rev. *J Page 14 of 307
S6J3350 Series
4. Package and Pin Assignment
4.1 Pin Assignment
Alphabets with pin numbers are signs specify I/O circuit type.
4.1.1 TEQFP-208 Pin Assignment
Figure 4-1: TEQFP-208 (S6J335xKyz *1)
*1: x, y, z are selected from the following parameters:
x: E, D (Memory Size)
y: S, A, B, U, C, D, T, E, F, V, G, H (Option)
z: C, D, E (Revision)
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SCS43_0
SCS42_0
-
-
SDA4
SCL4
-
-
SCS32_1
SCS31_1
-
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-
-
-
-
-
SCS23_1
SCS22_1
SCS21_1
SCS20_1
SOT2_1
-
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-
SCL12
-
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-
-
SDA11
-
SCL11
-
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-
-
-
SDA10
SCL10
-
-
-
-
-
SDA9
-
-
TX7_1
RX7_1
SCS41_0
SCS40_0
SOT4_0
SCK4_0
SIN4_0
SCS33_1
EINT20_5
EINT19_5
SCS30_1
SOT3_1
SCK3_1
SIN3_1
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-
PPG14_TOUT0_1
PPG13_TOUT2_1
PPG13_TOUT0_1
PPG12_TOUT2_1
PPG12_TOUT0_1
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SDA12
SCK12_0
SIN12_0
-
SCS111_0
SCS110_0
SOT11_0
-
SCK11_0
-
-
SIN11_0
-
SCS100_0
SOT10_0
SCK10_0
-
SIN10_0
SCS91_0
SCS90_0
-
SOT9_0
-
-
EINT3_6
EINT2_6
EINT1_6
EINT0_6
EINT23_5
EINT22_5
EINT0_0
EINT21_5
ADTRG1_2
ADTRG0_1
PPG12/13/14/15_TIN1_1
PPG15_TOUT2_1
PPG15_TOUT0_1
PPG14_TOUT2_1
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-
-
EINT15_5
EINT14_5
EINT13_5
EINT12_5
EINT11_5
-
-
-
-
SCS120_0
-
SOT12_0
PPG12/13/14/15_TIN1_0
PPG15_TOUT2_0
-
PPG15_TOUT0_0
PPG14_TOUT2_0
PPG14_TOUT0_0
-
PPG13_TOUT2_0
-
-
PPG13_TOUT0_0
-
PPG12_TOUT2_0
PPG12_TOUT0_0
PPG6/7/8/9/10/11_TIN1_0
-
PPG11_TOUT2_0
PPG11_TOUT0_0
PPG10_TOUT2_0
-
PPG10_TOUT0_0
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EINT18_5
EINT17_5
EINT16_5
EINT3_1
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SCK2_1
SIN2_1
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-
EINT9_5
-
EINT7_5
EINT6_5
EINT23_0
-
EINT4_5
EINT3_5
EINT2_5
-
EINT0_5
-
-
EINT22_0
-
EINT22_4
EINT21_4
EINT20_4
-
EINT21_0
EINT18_4
EINT17_4
PPG28_TOUT2_0
EINT15_4
-
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MAD0
MDATA7
MDATA6
MDATA5
MDATA4
MDATA3
MDATA2
MDATA1
MDATA0
MCSX1
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-
MCSX0
MDATA11
MDATA10
MDATA9
MDATA8
PPG28/29/30/31_TIN1_0
PPG31_TOUT2_0
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PPG31_TOUT0_0
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PPG30_TOUT2_0
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PPG30_TOUT0_0
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PPG29_TOUT2_0
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PPG29_TOUT0_0
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EINT16_4
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MDATA15
MDATA14
MDATA13
MDATA12
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EINT10_5
EINT2_1
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-
AN63
EINT8_5
AN62
AN61
AN60
EINT5_5
AN59
AN58
AN57
EINT1_5
AN56
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-
AN55
EINT23_4
AN54
AN53
AN52
EINT19_4
AN51
AN50
AN49
AN48
AN47
-
VSS
P2_19
P2_18
P2_17
P2_16
P2_15
P2_14
P2_13
P2_12
P2_11
P2_10
P3_31
P3_30
P3_29
P3_28
VCC53
VSS
VCC12
P2_09
P3_27
P3_26
P3_25
P3_24
P4_31
P4_30
DVCC
DVSS
P2_08
P4_29
P2_07
P2_06
P2_05
P4_28
P2_04
P2_03
P2_02
P4_27
P2_01
DVCC
DVSS
P2_00
P4_26
P1_31
P1_30
P1_29
P4_25
P1_28
P1_27
P1_26
P4_24
P1_25
DVCC
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S
S
S
S
S
S
S
S2
S
S
S
S
S
S
-
-
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S
S
S
S
S
Q
Q
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P
Q
P
P
P
Q
P
P
P
Q
P
-
-
P
Q
P
P
P
Q
P
P
P
P
P
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208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
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183
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179
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175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
- - - - - - - - - - - - - VCC53 - 1 156 -DVSS - - - - - - - - - - - -
- - - - - - - - - EINT0_1 - MAD1 - P0_00 S 2 155 P P1_24 AN46 - EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - -
- - - - - - - - SIN1_0 EINT1_0 - MAD2 - P0_01 S 3 154 P P1_23 AN45 - EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - -
- - - - - - - SCL1 SCK1_0 EINT4_1 - MAD3 - P0_02 S 4 153 P P1_22 AN44 - EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - -
- - - - - - - SDA1 SOT1_0 EINT5_1 - MAD4 - P0_03 S 5 152 P P1_21 AN43 - EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - -
- - - - - - - - - RX0_2 PPG16_TOUT0_0 EINT7_1 RXCLK_1 P4_00 T 6 151 P P1_20 AN42 - EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - -
- - - - - - - - - TX0_2 PPG16_TOUT2_0 EINT9_1 RXER_1 P4_01 T 7 150 P P1_19 AN41 - EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - -
- - - - - - - - - - PPG17_TOUT0_0 EINT10_1 RXDV_1 P4_02 T 8 149 P P1_18 AN40 - EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - -
- - - - - - - SIN0_1 SCS10_0 EINT11_1 - MAD5 - P0_04 S 9 148 P P1_17 AN39 - EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - -
- - - - - - - SOT0_1 SCS11_0 EINT13_1 - MAD6 - P0_05 S 10 147 - DVCC - - - - - - - - - - - -
- - - - - SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 - MAD7 - - P0_06 S 11 146 -DVSS - - - - - - - - - - - -
- - - - - SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 - MAD8 - - P0_07 S 12 145 -AVSS - - - - - - - - - - - -
- - - - - - - PPG1_TOUT0_1 EINT0_2 - MAD9 - - P0_08 S 13 144 -AVRL5 - - - - - - - - - - - -
- - - - - - SIN17_1 PPG1_TOUT2_1 EINT1_2 - MAD10 - - P0_09 S 14 143 - AVRH5 - - - - - - - - - - - -
- - - - - - - - SCS170_1 RX3_2 PPG17_TOUT2_0 EINT2_2 TXCLK_1 P4_03 T 15 142 - AVCC5 - - - - - - - - - - - -
- - - - - - - - SCK17_1 TX3_2 PPG18_TOUT0_0 EINT3_2 TXEN_1 P4_04 T 16 141 G P4_23 AN38 EINT10_4 PPG28_TOUT0_0 TX7_0 SCS160_1 - - - - - - -
- - - - - - - - - SOT17_1 PPG18_TOUT2_0 EINT4_2 TXD0_1 P4_05 T 17 140 E P4_22 ADTRG1_0 EINT22_1 PPG22/23/24/25/26/27_TIN1_0 RX7_0 SCS161_1 - - - - - - -
- - - - - - SCS171_1 PPG2_TOUT0_1 EINT5_2 - MAD11 - - P0_10 S 18 139 H P1_16 ADTRG0_0 - EINT9_4 - PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 -
- - - - - - - PPG2_TOUT2_1 EINT6_2 - MAD12 - - P0_11 S 19 138 G P4_21 AN37 EINT8_4 PPG27_TOUT2_0 SCK16_1 - - - - - - - -
- - - - - - - PPG3_TOUT0_1 EINT7_2 - MAD13 - - P0_12 S 20 137 G P4_20 AN36 EINT7_4 PPG27_TOUT0_0 TX4_0 SOT16_1 - - - - - - -
- - - - - - - PPG3_TOUT2_1 EINT8_2 - MAD14 - - P0_13 S 21 136 G P4_19 AN35 EINT16_1 PPG26_TOUT2_0 RX4_0 SIN16_1 - - - - - - -
- - - - - - - - - - - - - VCC53 - 22 135 - VCC5 - - - - - - - - - - - -
- - - - - - - - - - - - - VSS -23 134 -VSS - - - - - - - - - - - -
- - - - - - - - - - - - - VCC12 - 24 133 - VCC12 - - - - - - - - - - - -
- - - - - - - - SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 TXD1_1 P3_00 T 25 132 - VCC12 - - - - - - - - - - - -
- - - - - - - - SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16 TXD2_1 P3_01 T 26 131 G P4_18 AN34 EINT6_4 PPG26_TOUT0_0 SIN12_1 - - - - - - - -
- - - - - - - - SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1 P3_02 T 27 130 G P4_17 AN33 EINT5_4 PPG25_TOUT2_0 SOT12_1 - - - - - - - -
- - - - - - - - SCS10_1 PPG5_TOUT2_1 EINT11_2 MAD18 TXER_1 P3_03 T 28 129 H P1_15 AN32 EINT16_0 - PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49_0 SCK17_0 SCK12_1 SCL17 INDICATOR0_1 -
- - - - - - - - SCS11_1 PPG0/1/2/3/4/5_TIN1_1 EINT12_2 MAD19 RXD0_1 P3_04 T 29 128 G P1_14 AN31 EINT15_0 - PPG5_TOUT0_0 OCU9_OTD1_0 ICU10_IN0_0 TOT48_0 TX3_0 SIN17_0 SYSC0_CLK_1 - -
- - - - - - - - - - PPG19_TOUT0_0 EINT13_2 RXD1_1 P4_06 T 30 127 G P3_23 AN30 EINT4_4 TX6_1 SCS120_1 - - - - - - - -
- - - - - - - - - - PPG19_TOUT2_0 EINT14_2 RXD2_1 P4_07 T 31 126 G P3_22 AN29 EINT19_1 RX6_1 SCS91_1 - - - - - - - -
- - - - - - - - SCS12_1 SIN4_1 EINT15_2 MAD20 RXD3_1 P3_05 T 32 125 G P3_21 AN28 EINT3_4 TOT49_1 SCS90_1 - - - - - - - -
- - - - - - - - SCS13_1 SOT4_1 EINT16_2 MAD21 MDIO_1 P3_06 T 33 124 E P3_20 EINT2_4 PPG6/7/8/9/10/11_TIN1_1 TIN49_1 TX5_1 SOT9_1 - - - - - - -
- - - - - - - - SCK4_1 EINT17_2 - MOEX - P0_14 S 34 123 E P3_19 EINT17_1 PPG11_TOUT2_1 OCU10_OTD1_1 ICU10_IN1_1 RX5_1 SCK9_1 - - - - - -
- - - - - - - - SCS40_1 EINT18_2 - MWEX - P0_15 S 35 122 E P3_18 EINT20_1 PPG11_TOUT0_1 OCU10_OTD0_1 ICU10_IN0_1 SIN9_1 - - - - - - -
- - - - - - - - SCS41_1 EINT19_2 - MCLK - P0_16 S 36 121 -VSS - - - - - - - - - - - -
- - - - - - - - - - SCS42_1 EINT20_2 MDQM1 P3_07 T 37 120 - C - - - - - - - - - - - -
- - - - - - - SCS43_1 EINT21_2 - MDQM0 - RXCLK_0 P0_17 V 38 119 O MODE - - - - - - - - - - - -
- - - - - - - - EINT22_2 - MCSX2 MDC_1 RXER_0 P0_18 V 39 118 D PSC_1 - - - - - - - - - - - -
- - - - - - - - EINT23_2 - MCSX3 COL_1 RXDV_0 P0_19 V 40 117 N RSTX - - - - - - - - - - - -
- - - - - - - - EINT0_3 - MRDY CRS_1 TXCLK_0 P0_20 U 41 116 G P4_16 AN27 EINT1_4 PPG25_TOUT0_0 - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 42 115 G P3_17 AN26 EINT0_4 - PPG10_TOUT2_1 OCU9_OTD1_1 ICU9_IN1_1 TOT48_1 TX3_1 - - - -
- - - - - - - - - - - - - VSS -43 114 G P3_16 AN25 EINT14_1 - PPG10_TOUT0_1 OCU9_OTD0_1 ICU9_IN0_1 TIN48_1 RX3_1 - - - -
- - - - - - - - - - - - - AVSS -44 113 G P1_13 AN24 EINT14_0 - OCU9_OTD0_0 TIN48_0 RX3_0 - - - - - -
- - - - - - - - - - - - - NC A45 112 L2 JTAG_TMS - - - - - - - - - - - -
- - - - - - - - - - - - - NC A46 111 L2 JTAG_TCK - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS -47 110 L2 JTAG_TDI - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 48 109 M JTAG_TDO - - - - - - - - - - - -
- - - - - - - - - - - - - NC A49 108 L JTAG_NTRST - - - - - - - - - - - -
- - - - - - - - - - - - - NC A50 107 KX0 - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS -51 106 KX1 - - - - - - - - - - - -
- - - - - - - - - - - - - VSS -52 105 -VSS - - - - - - - - - - - -
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
-
B
B
B
B
B
-
B
-
-
B
B
B
B
B
-
-
C
C
C
-
-
-
-
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
H
G
G
H
G
G
I
R
R
-
VCC3
P0_21
P0_22
P0_23
P0_24
P0_25
VSS
P0_26
VSS
VCC3
P0_27
P0_28
P0_29
P0_30
P0_31
VSS
VCC3
P1_00
P1_01
P1_02
VCC12
VCC12
VSS
VCC5
P4_08
P4_09
P4_10
P4_11
P3_08
P3_09
P3_10
P3_11
P1_03
P1_04
P3_12
P3_13
P1_05
P1_06
P3_14
P3_15
P1_07
P1_08
P1_09
P4_12
P4_13
P1_10
P4_14
P4_15
NMIX
X0A
X1A
VCC5
-
M_SDATA0_0
M_SDATA0_2
M_SDATA0_1
M_SSEL0
M_SDATA0_3
-
M_SCLK0
-
-
M_SDATA1_0
M_SDATA1_2
M_SDATA1_1
M_SSEL1
M_SDATA1_3
-
-
-
-
-
-
-
-
-
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
-
P1_11
P1_12
-
-
M_DQ3
M_DQ2
M_DQ1
M_DQ0
M_CS#_1
-
M_CK
-
-
M_RWDS
M_DQ4
M_DQ5
M_DQ6
M_DQ7
-
-
M_CS#_2
COL_0
CRS_0
-
-
-
-
EINT13_3
EINT14_3
EINT15_3
EINT16_3
EINT18_1
EINT6_1
EINT17_3
EINT8_1
EINT4_0
EINT5_0
EINT21_1
EINT18_3
EINT6_0
EINT7_0
EINT12_1
EINT19_3
EINT8_0
ADTRG1_1
EINT10_0
EINT20_3
EINT21_3
EINT11_0
EINT22_3
EINT23_3
-
EINT12_0
EINT13_0
-
-
TXEN_0
TXD0_0
TXD1_0
TXD2_0
TXD3_0
-
TXER_0
-
-
RXD0_0
RXD1_0
RXD2_0
RXD3_0
MDIO_0
-
-
MDC_0
EINT11_3
EINT12_3
-
-
-
-
PPG20_TOUT0_0
PPG20_TOUT2_0
PPG21_TOUT0_0
PPG21_TOUT2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
EINT9_0
-
PPG23_TOUT0_0
PPG23_TOUT2_0
-
PPG24_TOUT0_0
PPG24_TOUT2_0
-
PPG4_TOUT0_0
-
-
-
EINT2_0
EINT1_3
EINT2_3
EINT3_3
EINT4_3
-
EINT5_3
-
-
EINT6_3
EINT3_0
EINT7_3
EINT8_3
EINT9_3
-
-
EINT10_3
SCS32_0
SCS33_0
-
-
-
-
-
-
-
-
PPG16/17/18/19/20/21_TIN1_0
PPG22_TOUT0_0
PPG22_TOUT2_0
PPG7_TOUT2_1
PPG0_TOUT0_0
PPG0_TOUT2_0
PPG8_TOUT0_1
PPG8_TOUT2_1
-
-
PPG9_TOUT0_1
PPG9_TOUT2_1
-
-
-
-
-
-
-
-
-
OCU8_OTD0_0
OCU8_OTD1_0
-
-
SIN2_0
SCK2_0
SOT2_0
SCS20_0
SCS21_0
-
SCS22_0
-
-
SCS23_0
SIN3_0
SCK3_0
SOT3_0
SCS30_0
-
-
SCS31_0
-
-
-
-
-
-
-
-
-
-
PPG6_TOUT0_1
PPG6_TOUT2_1
PPG7_TOUT0_1
OCU1_OTD1_1
OCU0_OTD0_0
OCU0_OTD1_0
OCU2_OTD0_1
OCU2_OTD1_1
PPG1_TOUT0_0
PPG1_TOUT2_0
OCU8_OTD0_1
OCU8_OTD1_1
PPG2_TOUT0_0
-
PPG3_TOUT0_0
-
-
PPG3_TOUT2_0
-
-
-
ICU9_IN0_0
ICU9_IN1_0
-
-
SIN9_2
SOT9_2
SCK9_2
SCS90_2
SCS91_2
-
-
-
-
SIN8_2
SCK8_2
SOT8_2
SCS80_2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCU0_OTD0_1
OCU0_OTD1_1
OCU1_OTD0_1
ICU1_IN1_1
ICU0_IN0_0
ICU0_IN1_0
ICU2_IN0_1
ICU2_IN1_1
ICU1_IN0_0
ICU1_IN1_0
ICU8_IN0_1
ICU8_IN1_1
OCU1_OTD0_0
PPG2_TOUT2_0
OCU2_OTD0_0
-
-
OCU2_OTD1_0
-
-
-
TIN17_0
TOT17_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICU0_IN0_1
ICU0_IN1_1
ICU1_IN0_1
TOT1_1
AIN8
BIN8
TIN16_1
TOT16_1
ZIN8
AIN9
TIN17_1
TOT17_1
ICU2_IN0_0
OCU1_OTD1_0
ICU8_IN0_0
-
-
ICU8_IN1_0
-
-
-
RX2_0
TX2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIN0_1
TOT0_1
TIN1_1
RX1_1
TIN0_0
TOT0_0
TX1_1
SCK10_1
TIN1_0
TOT1_0
RX2_1
TX2_1
BIN9
ICU2_IN1_0
SCK16_0
-
-
SOT16_0
-
-
-
SCS160_0
SCS161_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIN8_1
RX0_1
TX0_1
SCS80_1
FRT0/1/2/3_TEXT
FRT4/8/9/10_TEXT
SIN10_1
TRACE3_1
RX0_0
TX0_0
SOT10_1
SCS100_1
TIN16_0
ZIN9
SCL16
-
-
SDA16
-
-
-
INDICATOR0_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCK8_1
SOT8_1
TRACE1_1
SIN0_0
SCK0_0
TRACE2_1
-
SOT0_0
SCS00_0
TRACE_CTL_1
TRACE_CLK_1
RX1_0
TOT16_0
TRACE_CTL_0
-
-
TRACE_CLK_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_1
-
-
SCL0
-
-
SDA0
TRACE1_0
-
-
TRACE2_0
TX1_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_0
-
-
-
-
SIN16_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE3_0
-
-
-
-
-
-
-
-
-
-
●
TOP VIEW
TEQFP-208

Document Number: 002-10634 Rev. *J Page 15 of 307
S6J3350 Series
4.1.2 TEQFP-176 Pin Assignment
Figure 4-2: TEQFP-176 (S6J335xJyz *1)
*1: x, y, z are selected from the following parameters:
x: E, D (Memory Size)
y: S, A, B, U, C, D, T, E, F, V, G, H (Option)
z: C, D, E (Revision)
-
-
-
-
-
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-
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-
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-
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-
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-
-
-
-
-
-
-
-
-
-
-
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-
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-
-
-
-
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-
-
-
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-
-
-
-
-
-
-
-
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-
-
-
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-
-
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-
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-
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-
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-
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-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCS43_0
SCS42_0
-
-
SDA4
SCL4
-
-
SCS32_1
SCS31_1
-
-
-
-
-
-
-
SCS23_1
SCS22_1
SCS21_1
SCS20_1
SOT2_1
-
-
-
-
SCL12
-
-
-
SDA11
SCL11
-
-
-
-
SDA10
SCL10
-
-
-
SDA9
-
-
-
-
SCS41_0
SCS40_0
SOT4_0
SCK4_0
SIN4_0
SCS33_1
EINT20_5
EINT19_5
SCS30_1
SOT3_1
SCK3_1
SIN3_1
-
-
-
PPG14_TOUT0_1
PPG13_TOUT2_1
PPG13_TOUT0_1
PPG12_TOUT2_1
PPG12_TOUT0_1
-
-
-
SDA12
SCK12_0
SIN12_0
SCS111_0
SCS110_0
SOT11_0
SCK11_0
-
-
SIN11_0
SCS100_0
SOT10_0
SCK10_0
SIN10_0
SCS91_0
SCS90_0
SOT9_0
-
-
EINT3_6
EINT2_6
EINT1_6
EINT0_6
EINT23_5
EINT22_5
EINT0_0
EINT21_5
ADTRG1_2
ADTRG0_1
PPG12/13/14/15_TIN1_1
PPG15_TOUT2_1
PPG15_TOUT0_1
PPG14_TOUT2_1
-
-
-
EINT15_5
EINT14_5
EINT13_5
EINT12_5
EINT11_5
-
-
SCS120_0
SOT12_0
PPG12/13/14/15_TIN1_0
PPG15_TOUT2_0
PPG15_TOUT0_0
PPG14_TOUT2_0
PPG14_TOUT0_0
PPG13_TOUT2_0
-
-
PPG13_TOUT0_0
PPG12_TOUT2_0
PPG12_TOUT0_0
PPG6/7/8/9/10/11_TIN1_0
PPG11_TOUT2_0
PPG11_TOUT0_0
PPG10_TOUT2_0
PPG10_TOUT0_0
-
-
-
-
-
-
-
-
-
-
-
-
EINT18_5
EINT17_5
EINT16_5
EINT3_1
-
-
-
-
-
-
-
-
-
-
EINT9_5
EINT7_5
EINT6_5
EINT23_0
EINT4_5
EINT3_5
EINT2_5
EINT0_5
-
-
EINT22_0
EINT22_4
EINT21_4
EINT20_4
EINT21_0
EINT18_4
EINT17_4
EINT15_4
-
-
MAD0
MDATA7
MDATA6
MDATA5
MDATA4
MDATA3
MDATA2
MDATA1
MDATA0
MCSX1
-
-
-
-
-
-
-
MCSX0
MDATA11
MDATA10
MDATA9
MDATA8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MDATA15
MDATA14
MDATA13
MDATA12
-
-
-
-
-
-
-
-
-
-
AN63
AN62
AN61
AN60
AN59
AN58
AN57
AN56
-
-
AN55
AN54
AN53
AN52
AN51
AN50
AN49
AN47
-
VSS
P2_19
P2_18
P2_17
P2_16
P2_15
P2_14
P2_13
P2_12
P2_11
P2_10
P3_31
P3_30
P3_29
P3_28
VCC53
VSS
VCC12
P2_09
P3_27
P3_26
P3_25
P3_24
DVCC
DVSS
P2_08
P2_07
P2_06
P2_05
P2_04
P2_03
P2_02
P2_01
DVCC
DVSS
P2_00
P1_31
P1_30
P1_29
P1_28
P1_27
P1_26
P1_25
DVCC
-
S
S
S
S
S
S
S
S2
S
S
S
S
S
S
-
-
-
S
S
S
S
S
-
-
P
P
P
P
P
P
P
P
-
-
P
P
P
P
P
P
P
P
-
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
- - - - - - - - - - - - - VCC53 - 1 132 -DVSS - - - - - - - - - - - -
- - - - - - - - - EINT0_1 - MAD1 - P0_00 S 2 131 P P1_24 AN46 - EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - -
- - - - - - - - SIN1_0 EINT1_0 - MAD2 - P0_01 S 3 130 P P1_23 AN45 - EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - -
- - - - - - - SCL1 SCK1_0 EINT4_1 - MAD3 - P0_02 S 4 129 P P1_22 AN44 - EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - -
- - - - - - - SDA1 SOT1_0 EINT5_1 - MAD4 - P0_03 S 5 128 P P1_21 AN43 - EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - -
- - - - - - - SIN0_1 SCS10_0 EINT11_1 - MAD5 - P0_04 S 6 127 P P1_20 AN42 - EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - -
- - - - - - - SOT0_1 SCS11_0 EINT13_1 - MAD6 - P0_05 S 7 126 P P1_19 AN41 - EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - -
- - - - - SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 - MAD7 - - P0_06 S 8 125 P P1_18 AN40 - EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - -
- - - - - SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 - MAD8 - - P0_07 S 9 124 P P1_17 AN39 - EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - -
- - - - - - - PPG1_TOUT0_1 EINT0_2 - MAD9 - - P0_08 S 10 123 - DVCC - - - - - - - - - - - -
- - - - - - SIN17_1 PPG1_TOUT2_1 EINT1_2 - MAD10 - - P0_09 S 11 122 -DVSS - - - - - - - - - - - -
- - - - - - SCS171_1 PPG2_TOUT0_1 EINT5_2 - MAD11 - - P0_10 S 12 121 -AVSS - - - - - - - - - - - -
- - - - - - - PPG2_TOUT2_1 EINT6_2 - MAD12 - - P0_11 S 13 120 - AVRL5 - - - - - - - - - - - -
- - - - - - - PPG3_TOUT0_1 EINT7_2 - MAD13 - - P0_12 S 14 119 - AVRH5 - - - - - - - - - - - -
- - - - - - - PPG3_TOUT2_1 EINT8_2 - MAD14 - - P0_13 S 15 118 - AVCC5 - - - - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 16 117 H P1_16 ADTRG0_0 - EINT9_4 - PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 -
- - - - - - - - - - - - - VSS -17 116 - VCC5 - - - - - - - - - - - -
- - - - - - - - - - - - - VCC12 - 18 115 -VSS - - - - - - - - - - - -
- - - - - - - - SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 TXD1_1 P3_00 T 19 114 - VCC12 - - - - - - - - - - - -
- - - - - - - - SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16 TXD2_1 P3_01 T 20 113 - VCC12 - - - - - - - - - - - -
- - - - - - - - SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1 P3_02 T 21 112 H P1_15 AN32 EINT16_0 - PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49_0 SCK17_0 SCK12_1 SCL17 INDICATOR0_1 -
- - - - - - - - SCS10_1 PPG5_TOUT2_1 EINT11_2 MAD18 TXER_1 P3_03 T 22 111 G P1_14 AN31 EINT15_0 - PPG5_TOUT0_0 OCU9_OTD1_0 ICU10_IN0_0 TOT48_0 TX3_0 SIN17_0 SYSC0_CLK_1 - -
- - - - - - - - SCS11_1 PPG0/1/2/3/4/5_TIN1_1 EINT12_2 MAD19 RXD0_1 P3_04 T 23 110 G P3_23 AN30 EINT4_4 TX6_1 SCS120_1 - - - - - - - -
- - - - - - - - SCS12_1 SIN4_1 EINT15_2 MAD20 RXD3_1 P3_05 T 24 109 G P3_22 AN29 EINT19_1 RX6_1 SCS91_1 - - - - - - - -
- - - - - - - - SCS13_1 SOT4_1 EINT16_2 MAD21 MDIO_1 P3_06 T 25 108 G P3_21 AN28 EINT3_4 TOT49_1 SCS90_1 - - - - - - - -
- - - - - - - - SCK4_1 EINT17_2 - MOEX - P0_14 S 26 107 E P3_20 EINT2_4 PPG6/7/8/9/10/11_TIN1_1 TIN49_1 TX5_1 SOT9_1 - - - - - - -
- - - - - - - - SCS40_1 EINT18_2 - MWEX - P0_15 S 27 106 E P3_19 EINT17_1 PPG11_TOUT2_1 OCU10_OTD1_1 ICU10_IN1_1 RX5_1 SCK9_1 - - - - - -
- - - - - - - - SCS41_1 EINT19_2 - MCLK - P0_16 S 28 105 E P3_18 EINT20_1 PPG11_TOUT0_1 OCU10_OTD0_1 ICU10_IN0_1 SIN9_1 - - - - - - -
- - - - - - - - - - SCS42_1 EINT20_2 MDQM1 P3_07 T 29 104 -VSS - - - - - - - - - - - -
- - - - - - - SCS43_1 EINT21_2 - MDQM0 - RXCLK_0 P0_17 V 30 103 - C - - - - - - - - - - - -
- - - - - - - - EINT22_2 - MCSX2 MDC_1 RXER_0 P0_18 V 31 102 O MODE - - - - - - - - - - - -
- - - - - - - - EINT23_2 - MCSX3 COL_1 RXDV_0 P0_19 V 32 101 D PSC_1 - - - - - - - - - - - -
- - - - - - - - EINT0_3 - MRDY CRS_1 TXCLK_0 P0_20 U 33 100 N RSTX - - - - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 34 99 G P3_17 AN26 EINT0_4 - PPG10_TOUT2_1 OCU9_OTD1_1 ICU9_IN1_1 TOT48_1 TX3_1 - - - -
- - - - - - - - - - - - - VSS -35 98 G P3_16 AN25 EINT14_1 - PPG10_TOUT0_1 OCU9_OTD0_1 ICU9_IN0_1 TIN48_1 RX3_1 - - - -
- - - - - - - - - - - - - AVSS -36 97 G P1_13 AN24 EINT14_0 - OCU9_OTD0_0 TIN48_0 RX3_0 - - - - - -
- - - - - - - - - - - - - NC A37 96 L2 JTAG_TMS - - - - - - - - - - - -
- - - - - - - - - - - - - NC A38 95 L2 JTAG_TCK - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS -39 94 L2 JTAG_TDI - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 40 93 M JTAG_TDO - - - - - - - - - - - -
- - - - - - - - - - - - - NC A41 92 L JTAG_NTRST - - - - - - - - - - - -
- - - - - - - - - - - - - NC A42 91 KX0 - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS -43 90 KX1 - - - - - - - - - - - -
- - - - - - - - - - - - - VSS -44 89 -VSS - - - - - - - - - - - -
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
-
B
B
B
B
B
-
B
-
-
B
B
B
B
B
-
-
C
C
C
-
-
-
-
G
G
G
G
G
G
G
G
G
G
G
G
G
G
H
H
I
R
R
-
VCC3
P0_21
P0_22
P0_23
P0_24
P0_25
VSS
P0_26
VSS
VCC3
P0_27
P0_28
P0_29
P0_30
P0_31
VSS
VCC3
P1_00
P1_01
P1_02
VCC12
VCC12
VSS
VCC5
P3_08
P3_09
P3_10
P3_11
P1_03
P1_04
P3_12
P3_13
P1_05
P1_06
P3_14
P3_15
P1_07
P1_08
P1_09
P1_10
NMIX
X0A
X1A
VCC5
-
M_SDATA0_0
M_SDATA0_2
M_SDATA0_1
M_SSEL0
M_SDATA0_3
-
M_SCLK0
-
-
M_SDATA1_0
M_SDATA1_2
M_SDATA1_1
M_SSEL1
M_SDATA1_3
-
-
-
-
-
-
-
-
-
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN21
-
P1_11
P1_12
-
-
M_DQ3
M_DQ2
M_DQ1
M_DQ0
M_CS#_1
-
M_CK
-
-
M_RWDS
M_DQ4
M_DQ5
M_DQ6
M_DQ7
-
-
M_CS#_2
COL_0
CRS_0
-
-
-
-
EINT18_1
EINT6_1
EINT17_3
EINT8_1
EINT4_0
EINT5_0
EINT21_1
EINT18_3
EINT6_0
EINT7_0
EINT12_1
EINT19_3
EINT8_0
ADTRG1_1
EINT10_0
EINT11_0
-
EINT12_0
EINT13_0
-
-
TXEN_0
TXD0_0
TXD1_0
TXD2_0
TXD3_0
-
TXER_0
-
-
RXD0_0
RXD1_0
RXD2_0
RXD3_0
MDIO_0
-
-
MDC_0
EINT11_3
EINT12_3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EINT9_0
-
-
-
PPG4_TOUT0_0
-
-
-
EINT2_0
EINT1_3
EINT2_3
EINT3_3
EINT4_3
-
EINT5_3
-
-
EINT6_3
EINT3_0
EINT7_3
EINT8_3
EINT9_3
-
-
EINT10_3
SCS32_0
SCS33_0
-
-
-
-
-
-
-
PPG7_TOUT2_1
PPG0_TOUT0_0
PPG0_TOUT2_0
PPG8_TOUT0_1
PPG8_TOUT2_1
-
-
PPG9_TOUT0_1
PPG9_TOUT2_1
-
-
-
-
-
OCU8_OTD0_0
OCU8_OTD1_0
-
-
SIN2_0
SCK2_0
SOT2_0
SCS20_0
SCS21_0
-
SCS22_0
-
-
SCS23_0
SIN3_0
SCK3_0
SOT3_0
SCS30_0
-
-
SCS31_0
-
-
-
-
-
-
PPG6_TOUT0_1
PPG6_TOUT2_1
PPG7_TOUT0_1
OCU1_OTD1_1
OCU0_OTD0_0
OCU0_OTD1_0
OCU2_OTD0_1
OCU2_OTD1_1
PPG1_TOUT0_0
PPG1_TOUT2_0
OCU8_OTD0_1
OCU8_OTD1_1
PPG2_TOUT0_0
-
PPG3_TOUT0_0
PPG3_TOUT2_0
-
ICU9_IN0_0
ICU9_IN1_0
-
-
SIN9_2
SOT9_2
SCK9_2
SCS90_2
SCS91_2
-
-
-
-
SIN8_2
SCK8_2
SOT8_2
SCS80_2
-
-
-
-
-
-
-
-
-
-
OCU0_OTD0_1
OCU0_OTD1_1
OCU1_OTD0_1
ICU1_IN1_1
ICU0_IN0_0
ICU0_IN1_0
ICU2_IN0_1
ICU2_IN1_1
ICU1_IN0_0
ICU1_IN1_0
ICU8_IN0_1
ICU8_IN1_1
OCU1_OTD0_0
PPG2_TOUT2_0
OCU2_OTD0_0
OCU2_OTD1_0
-
TIN17_0
TOT17_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICU0_IN0_1
ICU0_IN1_1
ICU1_IN0_1
TOT1_1
AIN8
BIN8
TIN16_1
TOT16_1
ZIN8
AIN9
TIN17_1
TOT17_1
ICU2_IN0_0
OCU1_OTD1_0
ICU8_IN0_0
ICU8_IN1_0
-
RX2_0
TX2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIN0_1
TOT0_1
TIN1_1
RX1_1
TIN0_0
TOT0_0
TX1_1
SCK10_1
TIN1_0
TOT1_0
RX2_1
TX2_1
BIN9
ICU2_IN1_0
SCK16_0
SOT16_0
-
SCS160_0
SCS161_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIN8_1
RX0_1
TX0_1
SCS80_1
FRT0/1/2/3_TEXT
FRT4/8/9/10_TEXT
SIN10_1
TRACE3_1
RX0_0
TX0_0
SOT10_1
SCS100_1
TIN16_0
ZIN9
SCL16
SDA16
-
INDICATOR0_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCK8_1
SOT8_1
TRACE1_1
SIN0_0
SCK0_0
TRACE2_1
-
SOT0_0
SCS00_0
TRACE_CTL_1
TRACE_CLK_1
RX1_0
TOT16_0
TRACE_CTL_0
TRACE_CLK_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_1
-
-
SCL0
-
-
SDA0
TRACE1_0
-
-
TRACE2_0
TX1_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_0
-
-
-
-
SIN16_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE3_0
-
-
-
-
-
-
●
TOP VIEW
TEQFP-176

Document Number: 002-10634 Rev. *J Page 16 of 307
S6J3350 Series
4.1.3 TEQFP-144 Pin Assignment
Figure 4-3: TEQFP-144 (S6J335xHyz *1)
*1: x, y, z are selected from the following parameters:
x: E, D (Memory Size)
y: S, A, B, U, C, D, T, E, F, V, G, H (Option)
z: C, D, E (Revision)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCS43_0
SCS42_0
-
-
SDA4
SCL4
-
-
SCS32_1
SCS31_1
-
-
-
SCS23_1
-
-
-
-
SCL12
-
-
-
SDA11
SCL11
-
-
-
-
SDA10
SCL10
-
-
-
SDA9
-
-
-
-
SCS41_0
SCS40_0
SOT4_0
SCK4_0
SIN4_0
SCS33_1
EINT20_5
EINT19_5
-
-
-
PPG14_TOUT0_1
-
-
-
SDA12
SCK12_0
SIN12_0
SCS111_0
SCS110_0
SOT11_0
SCK11_0
-
-
SIN11_0
SCS100_0
SOT10_0
SCK10_0
SIN10_0
SCS91_0
SCS90_0
SOT9_0
-
-
EINT3_6
EINT2_6
EINT1_6
EINT0_6
EINT23_5
EINT22_5
EINT0_0
EINT21_5
ADTRG1_2
ADTRG0_1
-
-
-
EINT15_5
-
-
SCS120_0
SOT12_0
PPG12/13/14/15_TIN1_0
PPG15_TOUT2_0
PPG15_TOUT0_0
PPG14_TOUT2_0
PPG14_TOUT0_0
PPG13_TOUT2_0
-
-
PPG13_TOUT0_0
PPG12_TOUT2_0
PPG12_TOUT0_0
PPG6/7/8/9/10/11_TIN1_0
PPG11_TOUT2_0
PPG11_TOUT0_0
PPG10_TOUT2_0
PPG10_TOUT0_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EINT9_5
EINT7_5
EINT6_5
EINT23_0
EINT4_5
EINT3_5
EINT2_5
EINT0_5
-
-
EINT22_0
EINT22_4
EINT21_4
EINT20_4
EINT21_0
EINT18_4
EINT17_4
EINT15_4
-
-
MAD0
MDATA7
MDATA6
MDATA5
MDATA4
MDATA3
MDATA2
MDATA1
MDATA0
MCSX1
-
-
-
MCSX0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN63
AN62
AN61
AN60
AN59
AN58
AN57
AN56
-
-
AN55
AN54
AN53
AN52
AN51
AN50
AN49
AN47
-
VSS
P2_19
P2_18
P2_17
P2_16
P2_15
P2_14
P2_13
P2_12
P2_11
P2_10
VCC53
VSS
VCC12
P2_09
DVCC
DVSS
P2_08
P2_07
P2_06
P2_05
P2_04
P2_03
P2_02
P2_01
DVCC
DVSS
P2_00
P1_31
P1_30
P1_29
P1_28
P1_27
P1_26
P1_25
DVCC
-
S
S
S
S
S
S
S
S2
S
S
-
-
-
S
-
-
P
P
P
P
P
P
P
P
-
-
P
P
P
P
P
P
P
P
-
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
- - - - - - - - - - - - - VCC53 - 1 108 -DVSS - - - - - - - - - - - - -
- - - - - - - - - EINT0_1 - MAD1 - P0_00 S 2 107 P P1_24 AN46 - EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - - -
- - - - - - - - SIN1_0 EINT1_0 - MAD2 - P0_01 S 3 106 P P1_23 AN45 - EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - - -
- - - - - - - SCL1 SCK1_0 EINT4_1 - MAD3 - P0_02 S 4 105 P P1_22 AN44 - EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - - -
- - - - - - - SDA1 SOT1_0 EINT5_1 - MAD4 - P0_03 S 5 104 P P1_21 AN43 - EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - - -
- - - - - - - SIN0_1 SCS10_0 EINT11_1 - MAD5 - P0_04 S 6 103 P P1_20 AN42 - EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - - -
- - - - - - - SOT0_1 SCS11_0 EINT13_1 - MAD6 - P0_05 S 7 102 P P1_19 AN41 - EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - - -
- - - - - SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 - MAD7 - - P0_06 S 8 101 P P1_18 AN40 - EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - - -
- - - - - SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 - MAD8 - - P0_07 S 9 100 P P1_17 AN39 - EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - - -
- - - - - - - PPG1_TOUT0_1 EINT0_2 - MAD9 - - P0_08 S 10 99 - DVCC - - - - - - - - - - - - -
- - - - - - SIN17_1 PPG1_TOUT2_1 EINT1_2 - MAD10 - - P0_09 S 11 98 -DVSS - - - - - - - - - - - - -
- - - - - - SCS171_1 PPG2_TOUT0_1 EINT5_2 - MAD11 - - P0_10 S 12 97 -AVSS - - - - - - - - - - - - -
- - - - - - - PPG2_TOUT2_1 EINT6_2 - MAD12 - - P0_11 S 13 96 - AVRL5 - - - - - - - - - - - - -
- - - - - - - PPG3_TOUT0_1 EINT7_2 - MAD13 - - P0_12 S 14 95 - AVRH5 - - - - - - - - - - - - -
- - - - - - - PPG3_TOUT2_1 EINT8_2 - MAD14 - - P0_13 S 15 94 - AVCC5 - - - - - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 16 93 H P1_16 ADTRG0_0 - EINT9_4 - PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 - -
- - - - - - - - - - - - - VSS -17 92 - VCC5 - - - - - - - - - - - - -
- - - - - - - - - - - - - VCC12 - 18 91 -VSS - - - - - - - - - - - - -
- - - - - - - - SCK4_1 EINT17_2 - MOEX - P0_14 S 19 90 - VCC12 - - - - - - - - - - - - -
- - - - - - - - SCS40_1 EINT18_2 - MWEX - P0_15 S 20 89 - VCC12 - - - - - - - - - - - - -
- - - - - - - - SCS41_1 EINT19_2 - MCLK - P0_16 S 21 88 H P1_15 AN32 EINT16_0 - PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49_0 SCK17_0 SCK12_1 SCL17 INDICATOR0_1 - -
- - - - - - - SCS43_1 EINT21_2 - MDQM0 - RXCLK_0 P0_17 V 22 87 G P1_14 AN31 EINT15_0 - PPG5_TOUT0_0 OCU9_OTD1_0 ICU10_IN0_0 TOT48_0 TX3_0 SIN17_0 SYSC0_CLK_1 - - -
- - - - - - - - EINT22_2 - MCSX2 MDC_1 RXER_0 P0_18 V 23 86 -VSS - - - - - - - - - - - - -
- - - - - - - - EINT23_2 - MCSX3 COL_1 RXDV_0 P0_19 V 24 85 - C - - - - - - - - - - - - -
- - - - - - - - EINT0_3 - MRDY CRS_1 TXCLK_0 P0_20 U 25 84 O MODE - - - - - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 26 83 D PSC_1 - - - - - - - - - - - - -
- - - - - - - - - - - - - VSS -27 82 N RSTX - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS -28 81 G P1_13 AN24 EINT14_0 - OCU9_OTD0_0 TIN48_0 RX3_0 - - - - - - -
- - - - - - - - - - - - - NC A29 80 L2 JTAG_TMS - - - - - - - - - - - - -
- - - - - - - - - - - - - NC A30 79 L2 JTAG_TCK - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS -31 78 L2 JTAG_TDI - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 32 77 M JTAG_TDO - - - - - - - - - - - - -
- - - - - - - - - - - - - NC A33 76 L JTAG_NTRST - - - - - - - - - - - - -
- - - - - - - - - - - - - NC A34 75 KX0 - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS -35 74 KX1 - - - - - - - - - - - - -
- - - - - - - - - - - - - VSS -36 73 -VSS - - - - - - - - - - - - -
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
-
B
B
B
B
B
-
B
-
-
B
B
B
B
B
-
-
C
C
C
-
-
-
-
G
G
G
G
G
G
H
H
I
R
R
-
VCC3
P0_21
P0_22
P0_23
P0_24
P0_25
VSS
P0_26
VSS
VCC3
P0_27
P0_28
P0_29
P0_30
P0_31
VSS
VCC3
P1_00
P1_01
P1_02
VCC12
VCC12
VSS
VCC5
P1_03
P1_04
P1_05
P1_06
P1_07
P1_08
P1_09
P1_10
NMIX
X0A
X1A
VCC5
-
M_SDATA0_0
M_SDATA0_2
M_SDATA0_1
M_SSEL0
M_SDATA0_3
-
M_SCLK0
-
-
M_SDATA1_0
M_SDATA1_2
M_SDATA1_1
M_SSEL1
M_SDATA1_3
-
-
-
-
-
-
-
-
-
AN8
AN9
AN12
AN13
AN16
AN17
AN18
AN21
-
P1_11
P1_12
-
-
M_DQ3
M_DQ2
M_DQ1
M_DQ0
M_CS#_1
-
M_CK
-
-
M_RWDS
M_DQ4
M_DQ5
M_DQ6
M_DQ7
-
-
M_CS#_2
COL_0
CRS_0
-
-
-
-
EINT4_0
EINT5_0
EINT6_0
EINT7_0
EINT8_0
ADTRG1_1
EINT10_0
EINT11_0
-
EINT12_0
EINT13_0
-
-
TXEN_0
TXD0_0
TXD1_0
TXD2_0
TXD3_0
-
TXER_0
-
-
RXD0_0
RXD1_0
RXD2_0
RXD3_0
MDIO_0
-
-
MDC_0
EINT11_3
EINT12_3
-
-
-
-
-
-
-
-
-
EINT9_0
-
-
-
PPG4_TOUT0_0
-
-
-
EINT2_0
EINT1_3
EINT2_3
EINT3_3
EINT4_3
-
EINT5_3
-
-
EINT6_3
EINT3_0
EINT7_3
EINT8_3
EINT9_3
-
-
EINT10_3
SCS32_0
SCS33_0
-
-
-
-
PPG0_TOUT0_0
PPG0_TOUT2_0
-
-
-
-
-
-
-
OCU8_OTD0_0
OCU8_OTD1_0
-
-
SIN2_0
SCK2_0
SOT2_0
SCS20_0
SCS21_0
-
SCS22_0
-
-
SCS23_0
SIN3_0
SCK3_0
SOT3_0
SCS30_0
-
-
SCS31_0
-
-
-
-
-
-
OCU0_OTD0_0
OCU0_OTD1_0
PPG1_TOUT0_0
PPG1_TOUT2_0
PPG2_TOUT0_0
-
PPG3_TOUT0_0
PPG3_TOUT2_0
-
ICU9_IN0_0
ICU9_IN1_0
-
-
SIN9_2
SOT9_2
SCK9_2
SCS90_2
SCS91_2
-
-
-
-
SIN8_2
SCK8_2
SOT8_2
SCS80_2
-
-
-
-
-
-
-
-
-
-
ICU0_IN0_0
ICU0_IN1_0
ICU1_IN0_0
ICU1_IN1_0
OCU1_OTD0_0
PPG2_TOUT2_0
OCU2_OTD0_0
OCU2_OTD1_0
-
TIN17_0
TOT17_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AIN8
BIN8
ZIN8
AIN9
ICU2_IN0_0
OCU1_OTD1_0
ICU8_IN0_0
ICU8_IN1_0
-
RX2_0
TX2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIN0_0
TOT0_0
TIN1_0
TOT1_0
BIN9
ICU2_IN1_0
SCK16_0
SOT16_0
-
SCS160_0
SCS161_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FRT0/1/2/3_TEXT
FRT4/8/9/10_TEXT
RX0_0
TX0_0
TIN16_0
ZIN9
SCL16
SDA16
-
INDICATOR0_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIN0_0
SCK0_0
SOT0_0
SCS00_0
RX1_0
TOT16_0
TRACE_CTL_0
TRACE_CLK_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCL0
SDA0
TRACE1_0
TRACE2_0
TX1_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_0
-
-
SIN16_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE3_0
-
-
-
-
-
-
●
TOP VIEW
TEQFP-144

Document Number: 002-10634 Rev. *J Page 17 of 307
S6J3350 Series
4.2 Package Dimensions
4.2.1 TEQFP208
Figure 4-4: TEQFP208
Package Type
Package Code
TEQFP 208pin
LEW208
D1
D
4
57
E
0.20 C A-B D 0.20 C A-B D
D3
D2
E3 E2
AA1
2
11
DETAIL A
e0.08 C
SEATING
PLANE
A
A'
b
0.08 C A-B D
8
SIDE VIEW
TOP VIEW
BOTTOM VIEW
b
SECTION A-A'
c
10
L1
L
θ
R1
R2
GAUGE
PLANE
DETAIL A
L2
E1
EXPOSED PAD
L11.00 REF
L
c
0.45
0.09
0.60 0.75
0.20
NOM.MIN.
28.00 BSC
D1
R2
E1
E
0°
0.08
4°
28.00 BSC
30.00 BSC
D
A
1A
30.00 BSC
0.05
SYMBOL
MAX.
8°
0.20
1.70
0.15
θ
D2
D3
E2
E3
7.05 REF
6.05 REF
7.05 REF
6.05 REF
b0.17 0.22 0.27
DIMENSION
1
R0.08
e0.50 BSC
L20.25
PACKAGE OUTLINE, 208 LEAD TEQFP
28.0X28.0X1.7 M MLEW208 REV**
002-12477 **

Document Number: 002-10634 Rev. *J Page 18 of 307
S6J3350 Series
4.2.2 TEQFP176
Figure 4-5: TEQFP176
Package Type
Package Code
TEQFP 176pin
LEV176
L11.00 REF
L
c
0.45
0.09
0.60 0.75
0.20
NOM .M IN.
24.00 BSC
D1
R2
E1
E
0°
0.08
2°
24.00 BSC
26.00 BSC
D
A
1A
26.00 BSC
0.05
SYM BOL
MAX.
8°
0.20
1.70
0.15
θ
D2
D3
E2
E3
6.65 REF
5.45 REF
6.65 REF
5.45 REF
b0.17 0.22 0.27
e0.50 BSC
DIM ENSION
1
R0.08
L20.25
EXPOSED PAD
D1
D
4
57
E1 E
0.20 C A -B D 0.20 C A-B D
D3
D2
E3 E2
A
A1
2
11
DETAIL A
e0.08 C
SEATI N G
PLA N E
A
A'
b0.08 C A-B D
8
SIDE VIEW
TOP VIEW BOTTO M VIEW
b
SECTION A -A'
c
10
L1
L
θ
R1
R2
GA U GE
PLA NE
DETAIL A
L2
24.0X24 .0X1.7 M MLEV176 REV**
PACKAGE OUTLINE, 176 LEAD TEQFP
002-13653 **

Document Number: 002-10634 Rev. *J Page 19 of 307
S6J3350 Series
4.2.3 TEQFP144
Figure 4-6: TEQFP144 (0.5mm Pitch)
Package Type
Package Code
TEQFP 144pin
LEX144
L11.00 REF
L
c
0.45
0.09
0.60 0.75
0.20
NOM .M IN .
20.00 BSC
D1
R2
E1
E
0°
0.08
4°
20.00 BSC
22.00 BSC
D
A
1A
22.00 BSC
0.05
SYM BOL
M AX.
8°
0.20
1.70
0.15
θ
D2
D3
E2
E3
5.80 REF
4.60 REF
5.80 REF
4.60 REF
b0.17 0.22 0.27
e0.50 BSC
DIM ENSION
1
R0.08
L20.25
D1
D
4
57
E1 E
0.20 C A-B D 0.20 C A-B D
D3
D2
E3 E2
A
A1
2
11
DETAIL A
e0.08 C
SEATING
PLANE
A
A'
b0.08 C A-B D
8
SID E VIEW
TOP VIEW
BOTTOM VIEW
b
SECTION A-A '
c
10
L1
L
θ
R1
R2
GAUGE
PLANE
DETAIL A
L2
EXPOSED PAD
20.0X20.0X1.7 M MLEX144 REV**
PACKAGE OUTLINE, 144 LEAD TEQFP
002-13553 **