Nations N32G43 Series User manual

N32G43x series
32-bit ARM®Cortex®-M4F microcontroller
User manual V2.0

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II
Contents
Abbreviations in the text .................................................................................................................................................1
Describes the list of abbreviations used in the register table ......................................................................................1
Available peripherals ..................................................................................................................................................1
Memory and bus architecture.........................................................................................................................................2
System architecture..................................................................................................................................................... 2
Bus architecture...................................................................................................................................................2
Bus address mapping...........................................................................................................................................3
Boot management................................................................................................................................................6
Memory system .......................................................................................................................................................... 8
FLASH specification........................................................................................................................................... 8
iCache................................................................................................................................................................ 20
SRAM................................................................................................................................................................ 22
FLASH registers................................................................................................................................................ 22
Power control (PWR) ....................................................................................................................................................32
General description................................................................................................................................................... 32
Power supply..................................................................................................................................................... 32
Power supply supervisor.................................................................................................................................... 33
Power modes ............................................................................................................................................................ 35
RUN mode......................................................................................................................................................... 37
SLEEP mode ..................................................................................................................................................... 38
LOW POWER RUN mode................................................................................................................................ 39
LOW POWER SLEEP mode............................................................................................................................. 40
STOP2 mode ..................................................................................................................................................... 40
STANDBY mode............................................................................................................................................... 41
Low-power auto-wakeup (AWU) mode ................................................................................................................... 42
PWR registers........................................................................................................................................................... 43
PWR register overview...................................................................................................................................... 43
Power control register 1 (PWR_CTRL1) .......................................................................................................... 43
Power control register 2 (PWR_CTRL2) .......................................................................................................... 44
Power control register 3 (PWR_CTRL3) .......................................................................................................... 45
Power status register 1 (PWR_STS1)................................................................................................................ 47
Power status register 1 (PWR_STS1)................................................................................................................ 48
Power status clear register (PWR_STSCLR) .................................................................................................... 49
Reset and clock control (RCC) .....................................................................................................................................50
Reset Control Unit.................................................................................................................................................... 50
Power reset ........................................................................................................................................................ 50
System reset....................................................................................................................................................... 50
Low power domain reset ................................................................................................................................... 51
Clock control unit..................................................................................................................................................... 52
Clock Tree Diagram .......................................................................................................................................... 53
HSE clock.......................................................................................................................................................... 53
HSI clock........................................................................................................................................................... 54
MSI clock.......................................................................................................................................................... 55
PLL clock .......................................................................................................................................................... 55
LSE clock.......................................................................................................................................................... 56
LSI clock ........................................................................................................................................................... 56
System clock (SYSCLK) selection.................................................................................................................... 57
Clock security system (CLKSS)........................................................................................................................ 57
LSE Clock security system (LSECSS)............................................................................................................ 57
RTC clock........................................................................................................................................................ 58
Watchdog clock ............................................................................................................................................... 58

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Clock output (MCO)........................................................................................................................................ 58
RCC Registers .......................................................................................................................................................... 58
RCC register overview ...................................................................................................................................... 59
Clock Control Register (RCC_CTRL) .............................................................................................................. 60
Clock Configuration Register (RCC_CFG)....................................................................................................... 62
Clock Interrupt Register (RCC_CLKINT) ........................................................................................................ 65
APB2 Peripheral Reset Register (RCC_APB2PRST) ....................................................................................... 68
APB1 Peripheral Reset Register (RCC_APB1PRST) ....................................................................................... 70
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN) ....................................................................... 72
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN).....................................................................73
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN).....................................................................75
LOW POWER Domain Control Register (RCC_LDCTRL)........................................................................... 77
Clock Control/Status Register (RCC_CTRLSTS)........................................................................................... 79
AHB Peripheral Reset Register (RCC_AHBPRST)........................................................................................ 81
Clock Configuration Register 2 (RCC_CFG2)................................................................................................ 82
Clock Configuration Register 3 (RCC_CFG3)................................................................................................ 84
Retention Domain Control Register (RCC_RDCTRL)................................................................................... 85
PLL and HSI Configuration Register (RCC_PLLHSIPRE)............................................................................ 86
SRAM Control/Status Register (RCC_SRAM_CTRLSTS)............................................................................ 87
GPIO andAFIO.............................................................................................................................................................88
Summary...................................................................................................................................................................88
I/O function description............................................................................................................................................ 89
I/O mode configuration ..................................................................................................................................... 89
Status after reset ................................................................................................................................................ 94
Individual bit setting and bit clearing................................................................................................................ 94
External interrupt/wake-up line......................................................................................................................... 95
Alternate function.............................................................................................................................................. 95
IO configuration of peripherals ....................................................................................................................... 105
GPIO locking mechanism................................................................................................................................ 107
GPIO registers ........................................................................................................................................................ 108
GPIO registers overview ................................................................................................................................. 108
GPIO mode description register (GPIOx_PMODE) ....................................................................................... 109
GPIO type definition (GPIOx_POTYPE) ....................................................................................................... 110
GPIO port slew rate configuration register (GPIOx_SR)................................................................................ 110
GPIO pull-up/pull-down description register (GPIOx_PUPD) ........................................................................111
GPIO input data register (GPIOx_PID)............................................................................................................111
GPIO output data register (GPIOx_POD) ....................................................................................................... 112
GPIO bit set/clear register (GPIOx_PBSC)..................................................................................................... 112
GPIO configuration lock register (GPIOx_PLOCK)....................................................................................... 113
GPIO alternate function low register (GPIOx_AFL)..................................................................................... 114
GPIO alternate function High register (GPIOx_AFH) .................................................................................. 114
GPIO bit clear register (GPIOx_PBC) .......................................................................................................... 115
GPIO driver strength configuration register (GPIOx_DS) ............................................................................ 115
AFIO registers ........................................................................................................................................................ 116
AFIO register overview................................................................................................................................... 116
AFIO mapping configuration control register (AFIO_RMP_CFG) ................................................................ 117
AFIO external interrupt configuration register 1(AFIO_EXTI_CFG1)........................................................... 118
AFIO external interrupt configuration register 2(AFIO_EXTI_CFG2)........................................................... 118
AFIO external interrupt configuration register 3(AFIO_EXTI_CFG3)........................................................... 119
AFIO external interrupt configuration register 4(AFIO_EXTI_CFG4)........................................................... 120
Interrupts and events................................................................................................................................................... 122
Nested vector interrupt register .............................................................................................................................. 122
SysTick calibration value register.................................................................................................................... 122
Interrupt and exception vectors ....................................................................................................................... 122
External interrupt/event controller (EXTI)............................................................................................................. 125
Introduction ..................................................................................................................................................... 125

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Main features................................................................................................................................................... 125
Functional description .....................................................................................................................................126
EXTI line mapping.......................................................................................................................................... 128
EXTI registers ........................................................................................................................................................ 129
EXTI register overview................................................................................................................................... 129
EXTI interrupt mask register (EXTI_IMASK) ............................................................................................... 129
EXTI event mask register (EXTI_EMASK) ...................................................................................................130
EXTI rising edge trigger configuration register (EXTI_RT_CFG) ................................................................. 130
EXTI falling edge trigger configuration register (EXTI_FT_CFG) ................................................................ 131
EXTI software interrupt event register (EXTI_SWIE).................................................................................... 131
EXTI pending register (EXTI_PEND) ............................................................................................................ 131
EXTI timestamp trigger source selection register (EXTI_TS_SEL)............................................................... 132
DMA controller............................................................................................................................................................ 133
Introduction ............................................................................................................................................................ 133
Main features.......................................................................................................................................................... 133
Block diagram ........................................................................................................................................................ 134
Function description ............................................................................................................................................... 134
DMAoperation................................................................................................................................................ 134
Channel priority and arbitration ...................................................................................................................... 135
DMAchannels and number of transfers.......................................................................................................... 135
Programmable data bit width, alignment and endians..................................................................................... 135
Peripheral/Memory address incrementation ....................................................................................................137
Channel configuration procedure .................................................................................................................... 137
Flow control .................................................................................................................................................... 138
Circular mode.................................................................................................................................................. 139
Error management ........................................................................................................................................... 139
Interrupt......................................................................................................................................................... 139
DMArequest mapping................................................................................................................................... 140
DMAregisters ........................................................................................................................................................ 141
DMAregister overview................................................................................................................................... 141
DMA interrupt status register (DMA_INTSTS).............................................................................................. 143
DMAinterrupt flag clear register (DMA_INTCLR) ....................................................................................... 144
DMA channel x configuration register (DMA_CHCFGx) .............................................................................. 144
DMA channel x transfer number register (DMA_TXNUMx)......................................................................... 146
DMA channel x peripheral address register (DMA_PADDRx)....................................................................... 147
DMA channel x memory address register (DMA_MADDRx)........................................................................ 147
DMA channel x channel request select register (DMA_CHSELx) ................................................................. 148
CRC calculation unit ................................................................................................................................................... 151
CRC introduction.................................................................................................................................................... 151
CRC main features.................................................................................................................................................. 151
CRC32 module................................................................................................................................................ 151
CRC16 module................................................................................................................................................ 151
CRC function description ....................................................................................................................................... 152
CRC32............................................................................................................................................................. 152
CRC16............................................................................................................................................................. 152
CRC registers.......................................................................................................................................................... 153
CRC register overview .................................................................................................................................... 153
CRC32 data register (CRC_CRC32DAT) ....................................................................................................... 153
CRC32 independent data register (CRC_CRC32IDAT).................................................................................. 153
CRC32 control register (CRC_CRC32CTRL) ................................................................................................ 154
CRC16 control register (CRC_CRC16CTRL) ................................................................................................ 154
CRC16 input data register (CRC_CRC16DAT).............................................................................................. 155
CRC cyclic redundancy check code register (CRC_CRC16D)....................................................................... 155
LRC result register (CRC_LRC) ..................................................................................................................... 156
Cryptographic algorithm hardware acceleration engine (SAC)..............................................................................157

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Advanced-control timers (TIM1 and TIM8) ...............................................................................................................158
TIM1 and TIM8 introduction .................................................................................................................................. 158
Main features of TIM1 and TIM8 ............................................................................................................................ 158
TIM1 and TIM8 function description ...................................................................................................................... 159
Time-base unit ................................................................................................................................................. 159
Counter mode .................................................................................................................................................. 160
Repetition counter ........................................................................................................................................... 167
Clock selection ................................................................................................................................................ 170
Capture/compare channels ............................................................................................................................... 173
Input capture mode .......................................................................................................................................... 176
PWM input mode ............................................................................................................................................ 177
Forced output mode ......................................................................................................................................... 178
Output compare mode ......................................................................................................................................179
PWM mode ................................................................................................................................................... 180
One-pulse mode ............................................................................................................................................. 183
Clearing the OCxREF signal on an external event ........................................................................................... 184
Complementary outputs with dead-time insertion ........................................................................................... 185
Break function ............................................................................................................................................... 187
Debug mode .................................................................................................................................................. 189
TIMx and external trigger synchronization ..................................................................................................... 189
Timer synchronization .................................................................................................................................... 193
6-step PWM generation .................................................................................................................................. 193
Encoder interface mode .................................................................................................................................. 194
Interfacing with Hall sensor ........................................................................................................................... 196
TIMx registers(x=1, 8) ............................................................................................................................................ 198
TIMx register overview .................................................................................................................................... 198
Control register 1 (TIMx_CTRL1) ................................................................................................................... 199
Control register 2 (TIMx_CTRL2) ................................................................................................................... 201
Slave mode control register (TIMx_SMCTRL) ................................................................................................. 203
DMA/Interrupt enable registers (TIMx_DINTEN) ............................................................................................ 206
Status registers (TIMx_STS) ............................................................................................................................ 207
Event generation registers (TIMx_EVTGEN) ...................................................................................................209
Capture/compare mode register 1 (TIMx_CCMOD1) ....................................................................................... 210
Capture/compare mode register 2 (TIMx_CCMOD2) ....................................................................................... 213
Capture/compare enable registers (TIMx_CCEN) ........................................................................................... 215
Counters (TIMx_CNT) .................................................................................................................................. 218
Prescaler (TIMx_PSC) ................................................................................................................................... 218
Auto-reload register (TIMx_AR) .................................................................................................................... 218
Repeat count registers (TIMx_REPCNT) ....................................................................................................... 219
Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 219
Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 220
Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 220
Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 221
Break and Dead-time registers (TIMx_BKDT) ............................................................................................... 221
DMA Control register (TIMx_DCTRL) .......................................................................................................... 223
DMA transfer buffer register (TIMx_DADDR) .............................................................................................. 224
Capture/compare mode registers 3(TIMx_CCMOD3) ..................................................................................... 225
Capture/compare register 5 (TIMx_CCDAT5) ................................................................................................ 225
Capture/compare register 6 (TIMx_CCDAT6) ................................................................................................ 226
General-purpose timers (TIM2, TIM3, TIM4, TIM5 and TIM9) ...............................................................................227
General-purpose timers introduction ........................................................................................................................ 227
Main features of General-purpose timers ................................................................................................................. 227
General-purpose timers description ......................................................................................................................... 228
Time-base unit ................................................................................................................................................. 228
Counter mode .................................................................................................................................................. 229
Clock selection ................................................................................................................................................ 235

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Capture/compare channels ............................................................................................................................... 239
Input capture mode .......................................................................................................................................... 242
PWM input mode ............................................................................................................................................. 243
Forced output mode ......................................................................................................................................... 244
Output compare mode ...................................................................................................................................... 244
PWM mode ..................................................................................................................................................... 246
One-pulse mode ............................................................................................................................................. 249
Clearing the OCxREF signal on an external event ........................................................................................... 250
Debug mode .................................................................................................................................................. 251
TIMx and external trigger synchronization ...................................................................................................... 251
Timer synchronization .................................................................................................................................... 251
Encoder interface mode ..................................................................................................................................256
Interfacing with Hall sensor ............................................................................................................................ 258
TIMx registers(x=2, 3 ,4 ,5 and 9) ........................................................................................................................... 258
TIMx register overview .................................................................................................................................... 258
Control register 1 (TIMx_CTRL1) ................................................................................................................... 260
Control register 2 (TIMx_CTRL2) ................................................................................................................... 262
Slave mode control register (TIMx_SMCTRL) ................................................................................................. 263
DMA/Interrupt enable registers (TIMx_DINTEN) ........................................................................................... 265
Status registers (TIMx_STS) ............................................................................................................................ 267
Event generation registers (TIMx_EVTGEN) ...................................................................................................268
Capture/compare mode register 1 (TIMx_CCMOD1) ....................................................................................... 269
Capture/compare mode register 2 (TIMx_CCMOD2) ....................................................................................... 272
Capture/compare enable registers (TIMx_CCEN) ........................................................................................... 274
Counters (TIMx_CNT) ................................................................................................................................... 275
Prescaler (TIMx_PSC) ................................................................................................................................... 276
Auto-reload register (TIMx_AR) .................................................................................................................... 276
Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 276
Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 277
Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 277
Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 278
DMA Control register (TIMx_DCTRL) .......................................................................................................... 278
DMA transfer buffer register (TIMx_DADDR)........................................................................................... 279
Basic timers (TIM6 and TIM7) ...................................................................................................................................281
Basic timers introduction ........................................................................................................................................ 281
Main features of Basic timers .................................................................................................................................. 281
Basic timers description........................................................................................................................................ 282
Time-base unit ................................................................................................................................................. 282
Counter mode .................................................................................................................................................. 283
Clock selection ................................................................................................................................................ 286
Debug mode .................................................................................................................................................... 286
TIMx registers(x = 6 and 7) .................................................................................................................................... 286
TIMx register overview.................................................................................................................................. 287
Control Register 1 (TIMx_CTRL1)............................................................................................................... 287
Control Register 2 (TIMx_CTRL2)............................................................................................................... 288
DMA/Interrupt Enable Registers (TIMx_DINTEN) ..................................................................................... 289
Status Registers (TIMx_STS)........................................................................................................................ 289
Event Generation registers (TIMx_EVTGEN).............................................................................................. 290
Counters (TIMx_CNT)..................................................................................................................................290
Prescaler (TIMx_PSC) .................................................................................................................................. 290
Automatic reload register (TIMx_AR) .......................................................................................................... 291
Low Power Timer (LPTIM) ......................................................................................................................................... 292
Introduction .......................................................................................................................................................... 292
Main Features....................................................................................................................................................... 292
Block diagram ...................................................................................................................................................... 293
Function description ............................................................................................................................................. 293

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LPTIM clocks and on-off control.................................................................................................................. 293
Prescaler ........................................................................................................................................................ 294
Glitch filter .................................................................................................................................................... 294
Timer enable.................................................................................................................................................. 295
Trigger multiplexer........................................................................................................................................ 295
Operating mode............................................................................................................................................. 296
Waveform generation..................................................................................................................................... 298
Register update.............................................................................................................................................. 299
Counter mode ................................................................................................................................................ 300
Encoder mode.............................................................................................................................................. 301
Non-orthogonal encoder mode .................................................................................................................... 302
Timeout function ......................................................................................................................................... 303
LPTIM interrupts......................................................................................................................................... 304
LPTIM registers.................................................................................................................................................... 304
LPTIM register overview .............................................................................................................................. 304
LPTIM interrupt and status register (LPTIM_INTSTS)................................................................................ 305
LPTIM interrupt clear register (LPTIM_INTCLR)....................................................................................... 306
LPTIM interrupt enable register (LPTIM_INTEN)....................................................................................... 307
LPTIM configuration register (LPTIM_CFG) .............................................................................................. 308
LPTIM control register (LPTIM_CTRL)...................................................................................................... 311
LPTIM compare register (LPTIM_COMP)................................................................................................... 311
LPTIM auto-reload register (LPTIM_ARR) ................................................................................................. 312
LPTIM counter register (LPTIM_CNT)........................................................................................................ 312
Real time clock (RTC) ...............................................................................................................................................314
Introduction .......................................................................................................................................................... 314
Main feature.......................................................................................................................................................... 314
Function description ............................................................................................................................................. 316
RTC block diagram........................................................................................................................................ 316
GPIO controlled by RTC............................................................................................................................... 317
RTC register write protection ........................................................................................................................ 317
RTC clock and prescaler................................................................................................................................ 317
RTC calendar................................................................................................................................................. 318
Calendar initialization and configuration ......................................................................................................318
Calendar reading............................................................................................................................................ 319
Calibration clock output ................................................................................................................................ 320
Programmable Alarm..................................................................................................................................... 320
Alarm configuration..................................................................................................................................... 320
Alarm output................................................................................................................................................ 320
Periodic automatic wakeup.......................................................................................................................... 321
Wakeup timer configuration ........................................................................................................................ 321
Timestamp function..................................................................................................................................... 321
Tamper detection ......................................................................................................................................... 322
Daylight saving time configuration ............................................................................................................. 323
RTC reset..................................................................................................................................................... 323
RTC sub-second register shift operation...................................................................................................... 323
RTC digital clock precision calibration ....................................................................................................... 323
RTC low power mode..................................................................................................................................325
RTC Registers....................................................................................................................................................... 325
RTC Register overview ................................................................................................................................. 325
RTC Calendar Time Register (RTC_TSH).................................................................................................... 326
RTC Calendar Date Register (RTC_DATE)..................................................................................................327
RTC Control Register (RTC_CTRL)............................................................................................................. 328
RTC Initial Status Register (RTC_INITSTS)................................................................................................ 330
RTC Prescaler Register (RTC_PRE) ............................................................................................................. 332
RTC Wakeup Timer Register (RTC_WKUPT).............................................................................................. 333
RTC Alarm A Register (RTC_ALARMA)..................................................................................................... 333
RTC Alarm B Register (RTC_ ALARMB).................................................................................................... 334

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RTC Write Protection register (RTC_WRP)................................................................................................ 335
RTC Sub-second Register (RTC_SUBS)..................................................................................................... 336
RTC Shift Control Register (RTC_ SCTRL)............................................................................................... 336
RTC Timestamp Time Register (RTC_TST) ............................................................................................... 337
RTC Timestamp Date Register (RTC_TSD) ............................................................................................... 337
RTC Timestamp Sub-second Register (RTC_TSSS)................................................................................... 338
RTC Calibration Register (RTC_CALIB) ................................................................................................... 339
RTC Tamper Configuration Register（RTC_ TMPCFG）......................................................................... 339
RTC Alarm A sub-second register (RTC_ ALRMASS)............................................................................... 342
RTC Alarm B sub-second register (RTC_ ALRMBSS)............................................................................... 343
RTC Option Register (RTC_ OPT).............................................................................................................. 344
RTC Backup registers (RTC_ BKP(1~20)) ................................................................................................. 344
Independent watchdog (IWDG) ...............................................................................................................................345
Introduction .......................................................................................................................................................... 345
Main features........................................................................................................................................................ 345
Function description ............................................................................................................................................. 346
Register access protection ............................................................................................................................. 346
Debugging mode ........................................................................................................................................... 347
User interface........................................................................................................................................................ 347
Operate flow.................................................................................................................................................. 347
IWDG configuration flow ............................................................................................................................. 348
IWDG registers..................................................................................................................................................... 348
IWDG register overview ............................................................................................................................... 348
IWDG key register (IWDG_KEY)................................................................................................................ 349
IWDG pre-scaler register (IWDG_PREDIV)................................................................................................ 349
IWDG reload register (IWDG_RELV).......................................................................................................... 350
IWDG status register (IWDG_STS).............................................................................................................. 350
Window watchdog (WWDG)....................................................................................................................................352
Introduction .......................................................................................................................................................... 352
Main features........................................................................................................................................................ 352
Function description ............................................................................................................................................. 352
Timing for refresh watchdog and interrupt generation ......................................................................................... 353
Debug mode.......................................................................................................................................................... 354
User interface........................................................................................................................................................ 354
WWDG configuration flow........................................................................................................................... 354
WWDG registers .................................................................................................................................................. 355
WWDG register overview............................................................................................................................. 355
WWDG control register (WWDG_CTRL).................................................................................................... 355
WWDG config register (WWDG_CFG)....................................................................................................... 355
WWDG status register (WWDG_STS)......................................................................................................... 356
Analog to digital conversion (ADC) .............................................................................................................................357
Introduction .......................................................................................................................................................... 357
Main features .......................................................................................................................................................... 357
Function Description ............................................................................................................................................ 358
ADC clock ...................................................................................................................................................... 359
ADC switch control ......................................................................................................................................... 360
Channel selection ............................................................................................................................................ 361
Internal channel ............................................................................................................................................. 363
Single conversion mode ................................................................................................................................... 363
Continuous conversion mode .......................................................................................................................... 363
Timing diagram ............................................................................................................................................... 363
Analog watchdog ............................................................................................................................................. 364
Scanning mode ................................................................................................................................................ 365
Injection channel management ....................................................................................................................... 365

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Discontinuous mode ...................................................................................................................................... 366
Calibration............................................................................................................................................................ 367
Data aligned ........................................................................................................................................................... 367
Programmable channel sampling time ..................................................................................................................... 368
Externally triggered conversion ............................................................................................................................... 368
DMArequests....................................................................................................................................................... 369
Temperature sensor ................................................................................................................................................. 369
Temperature sensor using flow...................................................................................................................... 370
ADC interrupt..................................................................................................................................................... 371
ADC registers...................................................................................................................................................... 371
ADC register overview ................................................................................................................................. 371
ADC status register (ADC_STS) .................................................................................................................... 372
ADC control register 1 (ADC_CTRL1)....................................................................................................... 374
ADC control register 2 (ADC_CTRL2)....................................................................................................... 376
ADC sampling time register 1 (ADC_SAMPT1) ........................................................................................ 378
ADC sampling time register 2 (ADC_ SAMPT2) ....................................................................................... 378
ADC injected channel data offset register x (ADC_JOFFSETx)(x=1…4) .................................................. 379
ADC watchdog high threshold register (ADC_WDGHIGH) ........................................................................... 379
ADC watchdog low threshold register (ADC_WDGLOW) ............................................................................. 380
ADC regular sequence register 1 (ADC_RSEQ1) ..................................................................................... 380
ADC regular sequence register 2 (ADC_RSEQ2) ..................................................................................... 381
ADC regular sequence register 3 (ADC_RSEQ3) ..................................................................................... 381
ADC Injection sequence register (ADC_JSEQ) ............................................................................................. 382
ADC injection data register x (ADC_JDATx) (x= 1…4) .......................................................................... 382
ADC regulars data register (ADC_DAT) ...................................................................................................... 383
ADC differential mode selection register (ADC_DIFSEL)....................................................................... 383
ADC calibration factor (ADC_CALFACT)............................................................................................... 384
ADC control register 3 (ADC_CTRL3)..................................................................................................... 384
ADC sampling time register 3 (ADC_SAMPT3) ...................................................................................... 386
Digital to analog conversion (DAC)..........................................................................................................................386
Introduction .......................................................................................................................................................... 386
Main features........................................................................................................................................................ 387
DAC function description and operation description ........................................................................................... 389
DAC enable................................................................................................................................................... 389
DAC output buffer......................................................................................................................................... 389
DAC data format ........................................................................................................................................... 389
DAC trigger................................................................................................................................................... 390
DAC conversion............................................................................................................................................ 390
DAC output voltage....................................................................................................................................... 391
DMArequests................................................................................................................................................ 391
The noise ....................................................................................................................................................... 391
Triangular wave generation ........................................................................................................................... 392
DAC register......................................................................................................................................................... 394
DAC registers overview ................................................................................................................................ 394
DAC control register (DAC_CTRL) ............................................................................................................. 394
DAC software trigger register (DAC_SOTTR)............................................................................................. 396
12 bit right aligned data hold register for DAC (DAC_DR12CH)................................................................ 396
12 bit left aligned data hold register for DAC (DAC_DL12CH) ..................................................................396
8-bit right-aligned data hold register for DAC (DAC_DR8CH) ................................................................... 397
DAC data output register (DAC_DATO) ......................................................................................................397
Comparator (COMP) ................................................................................................................................................399
COMP system connection block diagram............................................................................................................. 399
COMP features ..................................................................................................................................................... 400
COMP configuration process................................................................................................................................ 400
COMP working mode........................................................................................................................................... 401
Window mode................................................................................................................................................ 401

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Independent comparator................................................................................................................................ 401
Comparator interconnection ................................................................................................................................. 401
Interrupt................................................................................................................................................................ 402
COMP register...................................................................................................................................................... 403
COMP register overview............................................................................................................................... 403
COMP interrupt enable register (COMP_INTEN) ........................................................................................ 404
COMP low power select register (COMP_LPCKSEL)................................................................................. 404
COMP window mode register (COMP_WINMODE)................................................................................... 405
COMP lock register (COMP_LOCK) ........................................................................................................... 405
COMP control register (COMP1_CTRL)...................................................................................................... 406
COMP filter register (COMP1_FILC)........................................................................................................... 408
COMP filter frequency division register (COMP1_FILP) ............................................................................ 408
COMP control register (COMP2_CTRL)...................................................................................................... 409
COMP filter register (COMP2_FILC)......................................................................................................... 410
COMP filter frequency division register (COMP2_FILP)........................................................................... 411
COMP output select register (COMP2_OSEL)........................................................................................... 411
COMP reference voltage register (COMP_VREFSCL) .............................................................................. 412
COMP test register(COMP_TEST)............................................................................................................. 412
COMP interrupt status register (COMP_INTSTS)...................................................................................... 413
Operational Amplifier (OPAMP).............................................................................................................................. 414
Main features........................................................................................................................................................ 414
OPAMP function description......................................................................................................................... 414
OPAMP working mode......................................................................................................................................... 415
OPAMP independent op amp mode............................................................................................................... 415
OPAMP follow mode..................................................................................................................................... 416
OPAMP internal gain (PGA) mode ............................................................................................................... 417
OPAMP with filtered internal gain mode ...................................................................................................... 418
OPAMP calibration........................................................................................................................................ 419
OPAMP Independent write protection........................................................................................................... 419
OPAMP TIMER controls the switching mode............................................................................................... 419
OPAMP register.................................................................................................................................................... 419
OPAMP register overview............................................................................................................................. 419
OPAMP Control Status Register (OPAMP1_CS).......................................................................................... 420
OPAMP Control Status Register (OPAMP2_CS).......................................................................................... 421
OPAMP Lock register (OPAMP_LOCK)...................................................................................................... 423
I2C interface ............................................................................................................................................................... 424
Introduction .......................................................................................................................................................... 424
Main features........................................................................................................................................................ 424
Function description ............................................................................................................................................. 424
SDAand SCL line control............................................................................................................................. 425
Software communication process.................................................................................................................. 425
Error conditions description .......................................................................................................................... 435
DMA application ........................................................................................................................................... 436
Packet error check ......................................................................................................................................... 437
SMBus........................................................................................................................................................... 438
Debug mode.......................................................................................................................................................... 440
Interrupt request.................................................................................................................................................... 440
I2C registers.......................................................................................................................................................... 441
I2C register overview .................................................................................................................................... 441
I2C Control register 1 (I2C_CTRL1) ............................................................................................................ 442
I2C Control register 2 (I2C_CTRL2) ............................................................................................................ 444
I2C Own address register 1 (I2C_OADDR1)................................................................................................ 445
I2C Own address register 2 (I2C_OADDR2)................................................................................................ 446
I2C Data register (I2C_DAT) ........................................................................................................................ 446
I2C Status register 1 (I2C_STS1).................................................................................................................. 447
I2C Status register 2 (I2C_STS2).................................................................................................................. 450

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I2C Clock control register (I2C_CLKCTRL)................................................................................................ 451
I2C Rise time register (I2C_TMRISE)........................................................................................................ 452
Universal synchronous asynchronous receiver transmitter (USART) .................................................................. 454
Introduction .......................................................................................................................................................... 454
Main features........................................................................................................................................................ 454
Functional block diagram ..................................................................................................................................... 455
Function description ............................................................................................................................................. 455
USART frame format .................................................................................................................................... 456
Transmitter..................................................................................................................................................... 457
Receiver......................................................................................................................................................... 459
Generation of fractional baud rate................................................................................................................. 462
Receiver’s tolerance clock deviation ............................................................................................................. 464
Parity control................................................................................................................................................. 464
DMA application ........................................................................................................................................... 465
Hardware flow control................................................................................................................................... 467
Multiprocessor communication ..................................................................................................................... 469
Synchronous mode ......................................................................................................................................471
Single-wire half-duplex mode ..................................................................................................................... 473
IrDA SIR ENDEC mode ............................................................................................................................. 474
LIN mode .................................................................................................................................................... 475
Smartcard mode (ISO7816)......................................................................................................................... 478
Interrupt request.................................................................................................................................................... 480
Mode support........................................................................................................................................................ 481
USART registers................................................................................................................................................... 481
USART register overview.............................................................................................................................. 481
USART Status register (USART_STS) ......................................................................................................... 482
USART Data register (USART_DAT)........................................................................................................... 484
USART Baud rate register (USART_BRCF) ................................................................................................ 485
USART control register 1 register (USART_CTRL1)................................................................................... 485
USART control register 2 register (USART_CTRL2)................................................................................... 487
USART control register 3 register (USART_CTRL3)................................................................................... 488
USART guard time and prescaler register (USART_GTP) ........................................................................... 490
Low power universal asynchronous receiver transmitter (LPUART)...................................................................492
Introduction .......................................................................................................................................................... 492
Main features........................................................................................................................................................ 492
Functional block diagram ..................................................................................................................................... 493
Function description ............................................................................................................................................. 493
LPUART frame format.................................................................................................................................. 494
Transmitter..................................................................................................................................................... 494
Receiver......................................................................................................................................................... 496
Fractional baud rate generation ..................................................................................................................... 498
Parity control................................................................................................................................................. 499
DMA application ........................................................................................................................................... 500
Hardware flow control................................................................................................................................... 502
Low power wake up ...................................................................................................................................... 504
Interrupt request.................................................................................................................................................... 504
LPUART registers ................................................................................................................................................ 505
LPUART register overview........................................................................................................................... 505
LPUART status register (LPUART_STS) ..................................................................................................... 505
LPUART interrupt enable register (LPUART_INTEN) ................................................................................ 506
LPUART control register (LPUART_CTRL)................................................................................................ 507
LPUART baud rate configuration register 1 (LPUART_BRCFG1).............................................................. 508
LPUART data register (LPUART_DAT).......................................................................................................509
LPUART baud rate configuration register 2 (LPUART_BRCFG2).............................................................. 509
LPUART wake up data register (LPUART_WUDAT).................................................................................. 510

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Serial peripheral interface/Inter-IC Sound (SPI/I
2
S) .................................................................................................. 511
Introduction .......................................................................................................................................................... 511
Main features........................................................................................................................................................ 511
SPI features.................................................................................................................................................... 511
I2S features .................................................................................................................................................... 511
SPI function description ....................................................................................................................................... 512
General description........................................................................................................................................ 512
SPI work mode.............................................................................................................................................. 515
Status flag...................................................................................................................................................... 521
Disabling the SPI........................................................................................................................................... 522
SPI communication using DMA.................................................................................................................... 523
CRC calculation............................................................................................................................................. 524
Error flag ....................................................................................................................................................... 525
SPI interrupt .................................................................................................................................................. 526
I2S function description ........................................................................................................................................ 527
Supported audio protocols............................................................................................................................. 528
Clock generator ............................................................................................................................................. 535
I2S Transmission and reception sequence...................................................................................................... 536
Status flag...................................................................................................................................................... 538
Error flag ....................................................................................................................................................... 539
I2S interrupt ................................................................................................................................................... 539
DMA function................................................................................................................................................ 540
SPI and I2S registers ............................................................................................................................................. 540
SPI register overview .................................................................................................................................... 540
SPI control register 1 (SPI_CTRL1) (not used in I2S mode) ........................................................................ 541
SPI control register 2 (SPI_CTRL2).............................................................................................................. 543
SPI status register (SPI_STS)........................................................................................................................ 544
SPI data register (SPI_DAT).......................................................................................................................... 545
SPI CRC polynomial register (SPI_CRCPOLY) (not used in I2S mode) ...................................................... 546
SPI RX CRC register (SPI_CRCRDAT) (not used in I2S mode) .................................................................. 546
SPI TX CRC register (SPI_ CRCTDAT)....................................................................................................... 546
SPI_I2S configuration register (SPI_I2SCFG) .............................................................................................. 547
SPI_I2S prescaler register (SPI_I2SPREDIV) ............................................................................................ 548
Controller area network (CAN)................................................................................................................................550
Introduction to CAN............................................................................................................................................. 550
Main features of CAN .......................................................................................................................................... 550
CAN overall introduction ..................................................................................................................................... 550
CAN module.................................................................................................................................................. 551
CAN working mode ...................................................................................................................................... 551
Send mailbox................................................................................................................................................. 553
Receiving filter.............................................................................................................................................. 553
Receive FIFO ................................................................................................................................................ 553
CAN Test mode ............................................................................................................................................. 554
CAN Debugging mode.................................................................................................................................. 557
CAN function description..................................................................................................................................... 557
Send processing............................................................................................................................................. 557
Time triggered communication mode............................................................................................................ 558
Non-automatic retransmission mode............................................................................................................. 558
Receiving management ................................................................................................................................. 559
Identifier filtering .......................................................................................................................................... 561
Message storage............................................................................................................................................. 564
Bit time characteristic.................................................................................................................................... 565
CAN interrupt....................................................................................................................................................... 568
Error management ......................................................................................................................................... 569
Bus-Off recovery........................................................................................................................................... 569
CAN Configuration Flow..................................................................................................................................... 570

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CAN registers....................................................................................................................................................... 571
Register Description...................................................................................................................................... 571
CAN register overview.................................................................................................................................. 572
CAN control and status register..................................................................................................................... 575
CAN mailbox register.................................................................................................................................... 586
CAN filter register......................................................................................................................................... 591
Universal serial bus full-speed device interface (USB_FS_Device) .......................................................................596
Introduction .......................................................................................................................................................... 596
Main features........................................................................................................................................................ 596
Clock configuration.............................................................................................................................................. 597
Functional description .......................................................................................................................................... 597
Access Packet Buffer Memory ...................................................................................................................... 598
Buffer description table ................................................................................................................................. 599
Double-buffered endpoints............................................................................................................................ 600
USB transfer.................................................................................................................................................. 603
USB events and interrupts............................................................................................................................. 607
Endpoint initialization ................................................................................................................................... 609
USB registers........................................................................................................................................................ 609
USB register overview .................................................................................................................................. 610
USB endpoint n register (USB_EPn), n=[0..7].............................................................................................. 611
USB control register (USB_CTRL) .............................................................................................................. 614
USB interrupt status register (USB_STS) ..................................................................................................... 616
USB frame number register (USB_FN) ........................................................................................................ 618
USB device address register (USB_ADDR) ................................................................................................. 619
USB packet buffer description table address register (USB_BUFTAB) ....................................................... 619
Buffer description table ........................................................................................................................................ 619
Send buffer address register n (USB_ADDRn_TX)...................................................................................... 620
Send data byte number register n (USB_CNTn_TX).................................................................................... 620
Receive buffer address register n (USB_ADDRn_RX)................................................................................. 620
Receive data byte number register n (USB_CNTn_RX)............................................................................... 621
Debug support (DBG)................................................................................................................................................623
Overview .............................................................................................................................................................. 623
JTAG/SWD function ............................................................................................................................................ 624
Switch JTAG/SWD interface......................................................................................................................... 624
Pin allocation................................................................................................................................................. 624
MCU debug function............................................................................................................................................ 625
Low-power mode debug support................................................................................................................... 625
Peripherals debug support ............................................................................................................................. 626
DBG registers....................................................................................................................................................... 626
DBG register overview.................................................................................................................................. 626
ID register (DBG_ID).................................................................................................................................... 626
Debug control register (DBG_CTRL)........................................................................................................... 627
Unique device serial number (UID).......................................................................................................................... 629
Introduction .......................................................................................................................................................... 629
UID register.......................................................................................................................................................... 629
UCID register ....................................................................................................................................................... 629
Version history ........................................................................................................................................................... 630
Notice ..........................................................................................................................................................................631

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List of tables
Table 2-1 List of peripheral register addresses............................................................................................................ 4
Table 2-2 List of boot mode......................................................................................................................................... 7
Table 2-3 Flash bus address list................................................................................................................................... 9
Table 2-4 Option byte list.......................................................................................................................................... 13
Table 2-5 Read protection configuration list ............................................................................................................. 15
Table 2-6 Flash read-write-erase(1) permission control table..................................................................................... 16
Table 2-7 FLASH register overview.......................................................................................................................... 22
Table 3-1 Power modes ............................................................................................................................................. 35
Table 3-2 Blocks running state.................................................................................................................................. 36
Table 3-3 PWR register overview.............................................................................................................................. 43
Table 4-1 RCC register overview .............................................................................................................................. 59
Table 5-1 I/O port configuration table....................................................................................................................... 89
Table 5-2 Input and output characteristics of different configurations...................................................................... 90
Table 5-3 Debug port image...................................................................................................................................... 96
Table 5-4 ADC external trigger injection conversion alternate function remapping................................................. 96
Table 5-5 ADC external trigger regular conversion alternate function remapping.................................................... 97
Table 5-6 TIM1 alternate function remapping........................................................................................................... 97
Table 5-7 TIM2 alternate function remapping........................................................................................................... 97
Table 5-8 TIM3 alternate function remapping........................................................................................................... 98
Table 5-9 TIM4 alternate function remapping........................................................................................................... 98
Table 5-10 TIM5 alternate function remapping......................................................................................................... 98
Table 5-11 TIM8 alternate function remapping......................................................................................................... 98
Table 5-12 TIM9 alternate function remapping......................................................................................................... 99
Table 5-13 LPTIM alternate function remapping...................................................................................................... 99
Table 5-14 CAN alternate function remapping.......................................................................................................... 99
Table 5-15 USART1 alternate function remapping ................................................................................................. 100
Table 5-16 USART2 alternate function remapping ................................................................................................. 100
Table 5-17 USART3 alternate function remapping ................................................................................................. 100
Table 5-18 UART4 alternate function remapping ................................................................................................... 101
Table 5-19 UART5 alternate function remapping ................................................................................................... 101
Table 5-20 LPUART alternate function remapping................................................................................................. 101
Table 5-21 I2C1 alternate function remapping........................................................................................................ 102
Table 5-22 I2C2 alternate function remapping........................................................................................................ 103
Table 5-23 SPI1 alternate function remapping ........................................................................................................ 103
Table 5-24 SPI2/I2S2 alternate function remapping................................................................................................ 104

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Table 5-25 COMP1 alternate function remapping................................................................................................... 104
Table 5-26 COMP2 alternate function remapping................................................................................................... 104
Table 5-27 EVENTOUT alternate function remapping........................................................................................... 105
Table 5-28 RTC alternate function remapping......................................................................................................... 105
Table 5-29 ADC/DAC ............................................................................................................................................. 105
Table 5-30 TIM1/TIM8 ........................................................................................................................................... 105
Table 5-31 TIM2/3/4/5/9 ......................................................................................................................................... 105
Table 5-32 LPTIM................................................................................................................................................... 105
Table 5-33 CAN....................................................................................................................................................... 106
Table 5-34 USART.................................................................................................................................................. 106
Table 5-35 UART .................................................................................................................................................... 106
Table 5-36 LPUART................................................................................................................................................ 106
Table 5-37 I2C......................................................................................................................................................... 106
Table 5-38 SPI-I2S .................................................................................................................................................. 106
Table 5-39 USB ....................................................................................................................................................... 107
Table 5-40 JTAG/SWD............................................................................................................................................ 107
Table 5-41 Other...................................................................................................................................................... 107
Table 5-42 GPIO registers overview ....................................................................................................................... 108
Table 5-43 AFIO register overview..........................................................................................................................116
Table 6-1 Vector table.............................................................................................................................................. 122
Table 6-2 EXTI register overview ........................................................................................................................... 129
Table 7-1 Programmable data width and endian operation (when PINC = MINC = 1) .......................................... 136
Table 7-2 Flow control table.................................................................................................................................... 138
Table 7-3 DMAinterrupt request............................................................................................................................. 139
Table 7-4 DMArequest mapping............................................................................................................................. 140
Table 7-5 DMAregister overview........................................................................................................................... 141
Table 8-1 CRC register overview ............................................................................................................................ 153
Table 10-1 Counting direction versus encoder signals............................................................................................ 195
Table 10-2 TIMx register overview ........................................................................................................................... 198
Table 10-3 TIMx internal trigger connection........................................................................................................... 205
Table 10-4 Output control bits of complementary OCx and OCxN channels with break function......................... 217
Table 11-1 Counting direction versus encoder signals ............................................................................................ 257
Table 11-2 TIMx register overview ........................................................................................................................... 258
Table 11-3 TIMx internal trigger connection........................................................................................................... 265
Table 11-4 Output control bits of standard OCx channel ........................................................................................ 275
Table 12-1 TIMx register overview.......................................................................................................................... 287
Table 13-1 Pre-scaler division ratios ....................................................................................................................... 294

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Table 13-2 9 trigger inputs corresponding to LPTIM_CFG.TRGSEL[2:0] bits...................................................... 295
Table 13-3 Encoder counting scenarios................................................................................................................... 301
Table 13-4 Interruption events................................................................................................................................. 304
Table 14-1 RTC register overview........................................................................................................................... 325
Table 15-1 IWDG counting maximum and minimum reset time ............................................................................ 347
Table 15-2 IWDG registers overview...................................................................................................................... 348
Table 16-1 Maximum and minimum counting time of WWDG.............................................................................. 354
Table 16-2 WWDG register overview..................................................................................................................... 355
Table 17-1 ADC pins ............................................................................................................................................... 359
Table 17-2 Analog watchdog channel selection....................................................................................................... 364
Table 17-3 Right-align data..................................................................................................................................... 368
Table 17-4 Left-aligne data...................................................................................................................................... 368
Table 17-5ADC is used for external triggering of regular channels ....................................................................... 369
Table 17-6ADC is used for external triggering of injection channels..................................................................... 369
Table 17-7 ADC interrupt........................................................................................................................................ 371
Table 17-8 ADC register overview.......................................................................................................................... 371
Table 18-1 DAC pins............................................................................................................................................... 388
Table 18-2 DAC external trigger............................................................................................................................. 390
Table 18-3 DAC registers overview ........................................................................................................................ 394
Table 19-1 COMP register overview ....................................................................................................................... 403
Table 20-1 OPAMP register overview..................................................................................................................... 419
Table 21-1 Comparison between SMBus and I2C................................................................................................... 438
Table 21-2 I2C interrupt request............................................................................................................................... 440
Table 21-3 I2C register overview ............................................................................................................................ 441
Table 22-1 Stop bit configuration............................................................................................................................ 457
Table 22-2 Data sampling for noise detection ......................................................................................................... 462
Table 22-3 Error calculation when setting baud rate............................................................................................... 463
Table 22-4 When DIV_Decimal = 0. Tolerance of USART receiver ...................................................................... 464
Table 22-5 When DIV_Decimal != 0. Tolerance of USART receiver..................................................................... 464
Table 22-6 Frame format......................................................................................................................................... 464
Table 22-7 USART interrupt request....................................................................................................................... 480
Table 22-8 USART mode setting(1) ......................................................................................................................... 481
Table 22-9 USART register overview...................................................................................................................... 481
Table 23-1 Data sampling for noise detection ......................................................................................................... 498
Table 23-2 Parity frame format................................................................................................................................ 500
Table 23-3 LPUART interrupt requests................................................................................................................... 504
Table 23-4 LPUART register overview................................................................................................................... 505

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Table 24-1 SPI interrupt request.............................................................................................................................. 526
Table 24-2 I2S interrupt request............................................................................................................................... 540
Table 24-3 SPI register overview............................................................................................................................. 540
Table 25-1 Examples of filter numbers.................................................................................................................... 563
Table 25-2 Send mailbox register list ...................................................................................................................... 564
Table 25-3 Receive mailbox register list ................................................................................................................. 565
Table 25-4 CAN register overview.......................................................................................................................... 572
Table 26-1 DATTOG and SW_BUF definitions...................................................................................................... 601
Table 26-2 How to use double buffering ................................................................................................................. 601
Table 26-3 How to use isochronous double buffering............................................................................................. 607
Table 26-4 Resume event detection......................................................................................................................... 609
Table 26-5 USB register overview........................................................................................................................... 610
Table 26-6 Receive status code................................................................................................................................ 613
Table 26-7 Send status code .................................................................................................................................... 613
Table 26-8 Endpoint packet receive buffer size definition ...................................................................................... 621
Table 27-1 Debug port pin....................................................................................................................................... 625
Table 27-2 DBG register overview.......................................................................................................................... 626

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List of figures
Figure 2-1 Bus architecture ......................................................................................................................................... 2
Figure 2-2 Bus address map ........................................................................................................................................ 4
Figure 3-1 Power supply block diagram.................................................................................................................... 33
Figure 3-2 Brown-out reset (BOR) waveform........................................................................................................... 34
Figure 3-3 PVD threshold waveform ........................................................................................................................ 35
Figure 4-1 System reset generation ........................................................................................................................... 51
Figure 4-2 Clock Tree................................................................................................................................................ 53
Figure 4-3 HSE/LSE clock source............................................................................................................................. 54
Figure 4-4 PLL clock source selection ...................................................................................................................... 55
Figure 5-1 Basic structure of I/O port........................................................................................................................ 89
Figure 5-2 Input floating/pull-up/pull-down configuration....................................................................................... 91
Figure 5-3 Output mode configuration...................................................................................................................... 92
Figure 5-4 Alternate function configuration.............................................................................................................. 93
Figure 5-5 High impedance analog mode configuration........................................................................................... 94
Figure 6-1 External interrupt/event controller block diagram................................................................................. 126
Figure 6-2 External interrupt generic I/O mapping ................................................................................................. 128
Figure 7-1 DMA block diagram .............................................................................................................................. 134
Figure 8-1 CRC calculation unit block diagram...................................................................................................... 152
Figure 10-1 Block diagram of TIM1 and TIM8 ...................................................................................................... 159
Figure 10-2 Counter timing diagram with prescaler division change from 1 to 4................................................... 160
Figure 10-3 Timing diagram of up-counting. The internal clock divider factor = 2/N............................................ 162
Figure 10-4 Timing diagram of the up-counting, update event when ARPEN=0/1................................................. 163
Figure 10-5 Timing diagram of the down-counting, internal clock divided factor = 2/N........................................ 165
Figure 10-6 Timing diagram of the Center-aligned, internal clock divided factor =2/N......................................... 166
Figure 10-7 A center-aligned sequence diagram that includes counter overflows and underflows (ARPEN = 1).. 167
Figure 10-8 Repeat count sequence diagram in down-counting mode.................................................................... 168
Figure 10-9 Repeat count sequence diagram in up-counting mode......................................................................... 169
Figure 10-10 Repeat count sequence diagram in center-aligned mode ................................................................... 169
Figure 10-11 Control circuit in normal mode, internal clock divided by 1 ............................................................. 170
Figure 10-12 TI2 external clock connection example ............................................................................................. 171
Figure 10-13 Control circuit in external clock mode 1............................................................................................ 172
Figure 10-14 External trigger input block diagram................................................................................................. 172
Figure 10-15 Control circuit in external clock mode 2............................................................................................ 173
Figure 10-16 Capture/compare channel (example: channel 1 input stage).............................................................. 174
Figure 10-17 Capture/compare channel 1 main circuit............................................................................................ 175

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Figure 10-18 Output part of channelx (x= 1,2,3, take channel 1 as example)......................................................... 176
Figure 10-19 Output part of channelx (x= 4)........................................................................................................... 176
Figure 10-20 PWM input mode timing.................................................................................................................... 178
Figure 10-21 Output compare mode, toggle on OC1 .............................................................................................. 180
Figure 10-22 Center-aligned PWM waveform (AR=8)........................................................................................... 181
Figure 10-23 Edge-aligned PWM waveform (APR=8)........................................................................................... 182
Figure 10-24 Clearing the OCxREF of TIMx.......................................................................................................... 185
Figure 10-25 Complementary output with dead-time insertion............................................................................... 186
Figure 10-26 Output behavior in response to a break.............................................................................................. 189
Figure 10-27 Control circuit in reset mode.............................................................................................................. 190
Figure 10-28 Control circuit in Trigger mode ......................................................................................................... 191
Figure 10-29 Control circuit in Gated mode............................................................................................................ 192
Figure 10-30 Control circuit in Trigger Mode + External Clock Mode2................................................................. 193
Figure 10-31 6-step PWM generation, COM example (OSSR=1).......................................................................... 194
Figure 10-32 Example of counter operation in encoder interface mode.................................................................. 195
Figure 10-33 Encoder interface mode example with IC1FP1 polarity inverted...................................................... 196
Figure 10-34 Example of Hall sensor interface....................................................................................................... 197
Figure 11-1 Block diagram of TIMx（x=2, 3 ,4 ,5 and 9）.................................................................................... 228
Figure 11-2 Counter timing diagram with prescaler division change from 1 to 4................................................... 229
Figure 11-3 Timing diagram of up-counting. The internal clock divider factor = 2/N............................................ 231
Figure 11-4 Timing diagram of the up-counting, update event when ARPEN=0/1................................................. 232
Figure 11-5 Timing diagram of the down-counting, internal clock divided factor = 2/N........................................ 233
Figure 11-6 Timing diagram of the Center-aligned, internal clock divided factor =2/N......................................... 234
Figure 11-7 A center-aligned sequence diagram that includes counter overflows and underflows (ARPEN = 1) .. 235
Figure 11-8 Control circuit in normal mode, internal clock divided by 1 ............................................................... 236
Figure 11-9 TI2 external clock connection example................................................................................................ 237
Figure 11-10 Control circuit in external clock mode 1............................................................................................ 238
Figure 11-11 External trigger input block diagram.................................................................................................. 238
Figure 11-12 Control circuit in external clock mode 2............................................................................................ 239
Figure 11-13 Capture/compare channel (example: channel 1 input stage).............................................................. 240
Figure 11-14 Capture/compare channel 1 main circuit............................................................................................ 241
Figure 11-15 Output part of channelx （x = 1,2,3,4;take channel 4 as an example）........................................... 242
Figure 11-16 PWM input mode timing.................................................................................................................... 244
Figure 11-17 Output compare mode, toggle on OC1............................................................................................... 246
Figure 11-18 Center-aligned PWM waveform (AR=8)........................................................................................... 247
Figure 11-19 Edge-aligned PWM waveform (APR=8)........................................................................................... 248
Figure 11-20 Example of One-pulse mode.............................................................................................................. 249

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Figure 11-21 Control circuit in reset mode.............................................................................................................. 251
Figure 11-22 Block diagram of timer interconnection............................................................................................. 252
Figure 11-23 TIM2 gated by OC1REF of TIM1 ..................................................................................................... 253
Figure 11-24 TIM2 gated by enable signal of TIM1 ............................................................................................... 254
Figure 11-25 Trigger TIM2 with an update of TIM1............................................................................................... 255
Figure 11-26 Triggers timers 1 and 2 using the TI1 input of TIM1......................................................................... 256
Figure 11-27 Example of counter operation in encoder interface mode.................................................................. 257
Figure 11-28 Encoder interface mode example with IC1FP1 polarity inverted ...................................................... 258
Figure 12-1 Block diagram of TIMx（x = 6 and 7）............................................................................................. 281
Figure 12-2 Counter timing diagram with prescaler division change from 1 to 4................................................... 282
Figure 12-3 Timing diagram of up-counting. The internal clock divider factor = 2/N............................................ 284
Figure 12-4 Timing diagram of the up-counting, update event when ARPEN=0/1................................................. 285
Figure 12-5 Control circuit in normal mode, internal clock divided by 1 ............................................................... 286
Figure 13-1 LPTIM Diagram................................................................................................................................... 293
Figure 13-2 Glitch filter timing diagram ................................................................................................................. 295
Figure 13-3 LPTIM output waveform, Continuous counting mode configuration.................................................. 296
Figure 13-4 PTIM output waveform, single counting mode configuration............................................................. 297
Figure 13-5 LPTIM output waveform, Single counting mode configuration and One-time mode activated.......... 298
Figure 13-6 Waveform generation........................................................................................................................... 299
Figure 13-7 Encoder mode counting sequence........................................................................................................ 302
Figure 13-8 Input waveforms of Input1 and Input2 when the decoder module is working normally ..................... 303
Figure 13-9 Input1 and Input2 input waveforms when decoder module is not working......................................... 303
Figure 14-1 RTC Block Diagram............................................................................................................................. 316
Figure 15-1 Functional block diagram of the independent watchdog module......................................................... 346
Figure 16-1 Watchdog block diagram...................................................................................................................... 352
Figure 16-2 Refresh window and interrupt timing of WWDG................................................................................ 353
Figure 17-1 Block diagram of a single ADC........................................................................................................... 359
Figure 17-2 ADC clock............................................................................................................................................ 360
Figure 17-3ADC channels and Pin connections..................................................................................................... 362
Figure 17-4 Timing diagram.................................................................................................................................... 364
Figure 17-5 Injection conversion delay................................................................................................................... 366
Figure 17-6 Calibration sequence diagram.............................................................................................................. 367
Figure 17-7 Temperature sensor and VREFINT Diagram of the channel ............................................................... 370
Figure 18-1 Block diagram of a DAC channel........................................................................................................ 388
Figure 18-2 Data register of single DAC channel mode.......................................................................................... 389
Figure 18-3 Tine diagram of transitions with trigger disable .................................................................................. 391
Figure 18-4 LFSR algorithm for DAC .................................................................................................................... 392