Nations N32G43 Series User manual

N32G43x series
32-bit ARM®Cortex®-M4F microcontroller
User manual V2.0

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II
Contents
Abbreviations in the text .................................................................................................................................................1
Describes the list of abbreviations used in the register table ......................................................................................1
Available peripherals ..................................................................................................................................................1
Memory and bus architecture.........................................................................................................................................2
System architecture..................................................................................................................................................... 2
Bus architecture...................................................................................................................................................2
Bus address mapping...........................................................................................................................................3
Boot management................................................................................................................................................6
Memory system .......................................................................................................................................................... 8
FLASH specification........................................................................................................................................... 8
iCache................................................................................................................................................................ 20
SRAM................................................................................................................................................................ 22
FLASH registers................................................................................................................................................ 22
Power control (PWR) ....................................................................................................................................................32
General description................................................................................................................................................... 32
Power supply..................................................................................................................................................... 32
Power supply supervisor.................................................................................................................................... 33
Power modes ............................................................................................................................................................ 35
RUN mode......................................................................................................................................................... 37
SLEEP mode ..................................................................................................................................................... 38
LOW POWER RUN mode................................................................................................................................ 39
LOW POWER SLEEP mode............................................................................................................................. 40
STOP2 mode ..................................................................................................................................................... 40
STANDBY mode............................................................................................................................................... 41
Low-power auto-wakeup (AWU) mode ................................................................................................................... 42
PWR registers........................................................................................................................................................... 43
PWR register overview...................................................................................................................................... 43
Power control register 1 (PWR_CTRL1) .......................................................................................................... 43
Power control register 2 (PWR_CTRL2) .......................................................................................................... 44
Power control register 3 (PWR_CTRL3) .......................................................................................................... 45
Power status register 1 (PWR_STS1)................................................................................................................ 47
Power status register 1 (PWR_STS1)................................................................................................................ 48
Power status clear register (PWR_STSCLR) .................................................................................................... 49
Reset and clock control (RCC) .....................................................................................................................................50
Reset Control Unit.................................................................................................................................................... 50
Power reset ........................................................................................................................................................ 50
System reset....................................................................................................................................................... 50
Low power domain reset ................................................................................................................................... 51
Clock control unit..................................................................................................................................................... 52
Clock Tree Diagram .......................................................................................................................................... 53
HSE clock.......................................................................................................................................................... 53
HSI clock........................................................................................................................................................... 54
MSI clock.......................................................................................................................................................... 55
PLL clock .......................................................................................................................................................... 55
LSE clock.......................................................................................................................................................... 56
LSI clock ........................................................................................................................................................... 56
System clock (SYSCLK) selection.................................................................................................................... 57
Clock security system (CLKSS)........................................................................................................................ 57
LSE Clock security system (LSECSS)............................................................................................................ 57
RTC clock........................................................................................................................................................ 58
Watchdog clock ............................................................................................................................................... 58

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Clock output (MCO)........................................................................................................................................ 58
RCC Registers .......................................................................................................................................................... 58
RCC register overview ...................................................................................................................................... 59
Clock Control Register (RCC_CTRL) .............................................................................................................. 60
Clock Configuration Register (RCC_CFG)....................................................................................................... 62
Clock Interrupt Register (RCC_CLKINT) ........................................................................................................ 65
APB2 Peripheral Reset Register (RCC_APB2PRST) ....................................................................................... 68
APB1 Peripheral Reset Register (RCC_APB1PRST) ....................................................................................... 70
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN) ....................................................................... 72
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN).....................................................................73
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN).....................................................................75
LOW POWER Domain Control Register (RCC_LDCTRL)........................................................................... 77
Clock Control/Status Register (RCC_CTRLSTS)........................................................................................... 79
AHB Peripheral Reset Register (RCC_AHBPRST)........................................................................................ 81
Clock Configuration Register 2 (RCC_CFG2)................................................................................................ 82
Clock Configuration Register 3 (RCC_CFG3)................................................................................................ 84
Retention Domain Control Register (RCC_RDCTRL)................................................................................... 85
PLL and HSI Configuration Register (RCC_PLLHSIPRE)............................................................................ 86
SRAM Control/Status Register (RCC_SRAM_CTRLSTS)............................................................................ 87
GPIO andAFIO.............................................................................................................................................................88
Summary...................................................................................................................................................................88
I/O function description............................................................................................................................................ 89
I/O mode configuration ..................................................................................................................................... 89
Status after reset ................................................................................................................................................ 94
Individual bit setting and bit clearing................................................................................................................ 94
External interrupt/wake-up line......................................................................................................................... 95
Alternate function.............................................................................................................................................. 95
IO configuration of peripherals ....................................................................................................................... 105
GPIO locking mechanism................................................................................................................................ 107
GPIO registers ........................................................................................................................................................ 108
GPIO registers overview ................................................................................................................................. 108
GPIO mode description register (GPIOx_PMODE) ....................................................................................... 109
GPIO type definition (GPIOx_POTYPE) ....................................................................................................... 110
GPIO port slew rate configuration register (GPIOx_SR)................................................................................ 110
GPIO pull-up/pull-down description register (GPIOx_PUPD) ........................................................................111
GPIO input data register (GPIOx_PID)............................................................................................................111
GPIO output data register (GPIOx_POD) ....................................................................................................... 112
GPIO bit set/clear register (GPIOx_PBSC)..................................................................................................... 112
GPIO configuration lock register (GPIOx_PLOCK)....................................................................................... 113
GPIO alternate function low register (GPIOx_AFL)..................................................................................... 114
GPIO alternate function High register (GPIOx_AFH) .................................................................................. 114
GPIO bit clear register (GPIOx_PBC) .......................................................................................................... 115
GPIO driver strength configuration register (GPIOx_DS) ............................................................................ 115
AFIO registers ........................................................................................................................................................ 116
AFIO register overview................................................................................................................................... 116
AFIO mapping configuration control register (AFIO_RMP_CFG) ................................................................ 117
AFIO external interrupt configuration register 1(AFIO_EXTI_CFG1)........................................................... 118
AFIO external interrupt configuration register 2(AFIO_EXTI_CFG2)........................................................... 118
AFIO external interrupt configuration register 3(AFIO_EXTI_CFG3)........................................................... 119
AFIO external interrupt configuration register 4(AFIO_EXTI_CFG4)........................................................... 120
Interrupts and events................................................................................................................................................... 122
Nested vector interrupt register .............................................................................................................................. 122
SysTick calibration value register.................................................................................................................... 122
Interrupt and exception vectors ....................................................................................................................... 122
External interrupt/event controller (EXTI)............................................................................................................. 125
Introduction ..................................................................................................................................................... 125

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Main features................................................................................................................................................... 125
Functional description .....................................................................................................................................126
EXTI line mapping.......................................................................................................................................... 128
EXTI registers ........................................................................................................................................................ 129
EXTI register overview................................................................................................................................... 129
EXTI interrupt mask register (EXTI_IMASK) ............................................................................................... 129
EXTI event mask register (EXTI_EMASK) ...................................................................................................130
EXTI rising edge trigger configuration register (EXTI_RT_CFG) ................................................................. 130
EXTI falling edge trigger configuration register (EXTI_FT_CFG) ................................................................ 131
EXTI software interrupt event register (EXTI_SWIE).................................................................................... 131
EXTI pending register (EXTI_PEND) ............................................................................................................ 131
EXTI timestamp trigger source selection register (EXTI_TS_SEL)............................................................... 132
DMA controller............................................................................................................................................................ 133
Introduction ............................................................................................................................................................ 133
Main features.......................................................................................................................................................... 133
Block diagram ........................................................................................................................................................ 134
Function description ............................................................................................................................................... 134
DMAoperation................................................................................................................................................ 134
Channel priority and arbitration ...................................................................................................................... 135
DMAchannels and number of transfers.......................................................................................................... 135
Programmable data bit width, alignment and endians..................................................................................... 135
Peripheral/Memory address incrementation ....................................................................................................137
Channel configuration procedure .................................................................................................................... 137
Flow control .................................................................................................................................................... 138
Circular mode.................................................................................................................................................. 139
Error management ........................................................................................................................................... 139
Interrupt......................................................................................................................................................... 139
DMArequest mapping................................................................................................................................... 140
DMAregisters ........................................................................................................................................................ 141
DMAregister overview................................................................................................................................... 141
DMA interrupt status register (DMA_INTSTS).............................................................................................. 143
DMAinterrupt flag clear register (DMA_INTCLR) ....................................................................................... 144
DMA channel x configuration register (DMA_CHCFGx) .............................................................................. 144
DMA channel x transfer number register (DMA_TXNUMx)......................................................................... 146
DMA channel x peripheral address register (DMA_PADDRx)....................................................................... 147
DMA channel x memory address register (DMA_MADDRx)........................................................................ 147
DMA channel x channel request select register (DMA_CHSELx) ................................................................. 148
CRC calculation unit ................................................................................................................................................... 151
CRC introduction.................................................................................................................................................... 151
CRC main features.................................................................................................................................................. 151
CRC32 module................................................................................................................................................ 151
CRC16 module................................................................................................................................................ 151
CRC function description ....................................................................................................................................... 152
CRC32............................................................................................................................................................. 152
CRC16............................................................................................................................................................. 152
CRC registers.......................................................................................................................................................... 153
CRC register overview .................................................................................................................................... 153
CRC32 data register (CRC_CRC32DAT) ....................................................................................................... 153
CRC32 independent data register (CRC_CRC32IDAT).................................................................................. 153
CRC32 control register (CRC_CRC32CTRL) ................................................................................................ 154
CRC16 control register (CRC_CRC16CTRL) ................................................................................................ 154
CRC16 input data register (CRC_CRC16DAT).............................................................................................. 155
CRC cyclic redundancy check code register (CRC_CRC16D)....................................................................... 155
LRC result register (CRC_LRC) ..................................................................................................................... 156
Cryptographic algorithm hardware acceleration engine (SAC)..............................................................................157

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Advanced-control timers (TIM1 and TIM8) ...............................................................................................................158
TIM1 and TIM8 introduction .................................................................................................................................. 158
Main features of TIM1 and TIM8 ............................................................................................................................ 158
TIM1 and TIM8 function description ...................................................................................................................... 159
Time-base unit ................................................................................................................................................. 159
Counter mode .................................................................................................................................................. 160
Repetition counter ........................................................................................................................................... 167
Clock selection ................................................................................................................................................ 170
Capture/compare channels ............................................................................................................................... 173
Input capture mode .......................................................................................................................................... 176
PWM input mode ............................................................................................................................................ 177
Forced output mode ......................................................................................................................................... 178
Output compare mode ......................................................................................................................................179
PWM mode ................................................................................................................................................... 180
One-pulse mode ............................................................................................................................................. 183
Clearing the OCxREF signal on an external event ........................................................................................... 184
Complementary outputs with dead-time insertion ........................................................................................... 185
Break function ............................................................................................................................................... 187
Debug mode .................................................................................................................................................. 189
TIMx and external trigger synchronization ..................................................................................................... 189
Timer synchronization .................................................................................................................................... 193
6-step PWM generation .................................................................................................................................. 193
Encoder interface mode .................................................................................................................................. 194
Interfacing with Hall sensor ........................................................................................................................... 196
TIMx registers(x=1, 8) ............................................................................................................................................ 198
TIMx register overview .................................................................................................................................... 198
Control register 1 (TIMx_CTRL1) ................................................................................................................... 199
Control register 2 (TIMx_CTRL2) ................................................................................................................... 201
Slave mode control register (TIMx_SMCTRL) ................................................................................................. 203
DMA/Interrupt enable registers (TIMx_DINTEN) ............................................................................................ 206
Status registers (TIMx_STS) ............................................................................................................................ 207
Event generation registers (TIMx_EVTGEN) ...................................................................................................209
Capture/compare mode register 1 (TIMx_CCMOD1) ....................................................................................... 210
Capture/compare mode register 2 (TIMx_CCMOD2) ....................................................................................... 213
Capture/compare enable registers (TIMx_CCEN) ........................................................................................... 215
Counters (TIMx_CNT) .................................................................................................................................. 218
Prescaler (TIMx_PSC) ................................................................................................................................... 218
Auto-reload register (TIMx_AR) .................................................................................................................... 218
Repeat count registers (TIMx_REPCNT) ....................................................................................................... 219
Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 219
Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 220
Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 220
Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 221
Break and Dead-time registers (TIMx_BKDT) ............................................................................................... 221
DMA Control register (TIMx_DCTRL) .......................................................................................................... 223
DMA transfer buffer register (TIMx_DADDR) .............................................................................................. 224
Capture/compare mode registers 3(TIMx_CCMOD3) ..................................................................................... 225
Capture/compare register 5 (TIMx_CCDAT5) ................................................................................................ 225
Capture/compare register 6 (TIMx_CCDAT6) ................................................................................................ 226
General-purpose timers (TIM2, TIM3, TIM4, TIM5 and TIM9) ...............................................................................227
General-purpose timers introduction ........................................................................................................................ 227
Main features of General-purpose timers ................................................................................................................. 227
General-purpose timers description ......................................................................................................................... 228
Time-base unit ................................................................................................................................................. 228
Counter mode .................................................................................................................................................. 229
Clock selection ................................................................................................................................................ 235

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Capture/compare channels ............................................................................................................................... 239
Input capture mode .......................................................................................................................................... 242
PWM input mode ............................................................................................................................................. 243
Forced output mode ......................................................................................................................................... 244
Output compare mode ...................................................................................................................................... 244
PWM mode ..................................................................................................................................................... 246
One-pulse mode ............................................................................................................................................. 249
Clearing the OCxREF signal on an external event ........................................................................................... 250
Debug mode .................................................................................................................................................. 251
TIMx and external trigger synchronization ...................................................................................................... 251
Timer synchronization .................................................................................................................................... 251
Encoder interface mode ..................................................................................................................................256
Interfacing with Hall sensor ............................................................................................................................ 258
TIMx registers(x=2, 3 ,4 ,5 and 9) ........................................................................................................................... 258
TIMx register overview .................................................................................................................................... 258
Control register 1 (TIMx_CTRL1) ................................................................................................................... 260
Control register 2 (TIMx_CTRL2) ................................................................................................................... 262
Slave mode control register (TIMx_SMCTRL) ................................................................................................. 263
DMA/Interrupt enable registers (TIMx_DINTEN) ........................................................................................... 265
Status registers (TIMx_STS) ............................................................................................................................ 267
Event generation registers (TIMx_EVTGEN) ...................................................................................................268
Capture/compare mode register 1 (TIMx_CCMOD1) ....................................................................................... 269
Capture/compare mode register 2 (TIMx_CCMOD2) ....................................................................................... 272
Capture/compare enable registers (TIMx_CCEN) ........................................................................................... 274
Counters (TIMx_CNT) ................................................................................................................................... 275
Prescaler (TIMx_PSC) ................................................................................................................................... 276
Auto-reload register (TIMx_AR) .................................................................................................................... 276
Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 276
Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 277
Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 277
Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 278
DMA Control register (TIMx_DCTRL) .......................................................................................................... 278
DMA transfer buffer register (TIMx_DADDR)........................................................................................... 279
Basic timers (TIM6 and TIM7) ...................................................................................................................................281
Basic timers introduction ........................................................................................................................................ 281
Main features of Basic timers .................................................................................................................................. 281
Basic timers description........................................................................................................................................ 282
Time-base unit ................................................................................................................................................. 282
Counter mode .................................................................................................................................................. 283
Clock selection ................................................................................................................................................ 286
Debug mode .................................................................................................................................................... 286
TIMx registers(x = 6 and 7) .................................................................................................................................... 286
TIMx register overview.................................................................................................................................. 287
Control Register 1 (TIMx_CTRL1)............................................................................................................... 287
Control Register 2 (TIMx_CTRL2)............................................................................................................... 288
DMA/Interrupt Enable Registers (TIMx_DINTEN) ..................................................................................... 289
Status Registers (TIMx_STS)........................................................................................................................ 289
Event Generation registers (TIMx_EVTGEN).............................................................................................. 290
Counters (TIMx_CNT)..................................................................................................................................290
Prescaler (TIMx_PSC) .................................................................................................................................. 290
Automatic reload register (TIMx_AR) .......................................................................................................... 291
Low Power Timer (LPTIM) ......................................................................................................................................... 292
Introduction .......................................................................................................................................................... 292
Main Features....................................................................................................................................................... 292
Block diagram ...................................................................................................................................................... 293
Function description ............................................................................................................................................. 293

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LPTIM clocks and on-off control.................................................................................................................. 293
Prescaler ........................................................................................................................................................ 294
Glitch filter .................................................................................................................................................... 294
Timer enable.................................................................................................................................................. 295
Trigger multiplexer........................................................................................................................................ 295
Operating mode............................................................................................................................................. 296
Waveform generation..................................................................................................................................... 298
Register update.............................................................................................................................................. 299
Counter mode ................................................................................................................................................ 300
Encoder mode.............................................................................................................................................. 301
Non-orthogonal encoder mode .................................................................................................................... 302
Timeout function ......................................................................................................................................... 303
LPTIM interrupts......................................................................................................................................... 304
LPTIM registers.................................................................................................................................................... 304
LPTIM register overview .............................................................................................................................. 304
LPTIM interrupt and status register (LPTIM_INTSTS)................................................................................ 305
LPTIM interrupt clear register (LPTIM_INTCLR)....................................................................................... 306
LPTIM interrupt enable register (LPTIM_INTEN)....................................................................................... 307
LPTIM configuration register (LPTIM_CFG) .............................................................................................. 308
LPTIM control register (LPTIM_CTRL)...................................................................................................... 311
LPTIM compare register (LPTIM_COMP)................................................................................................... 311
LPTIM auto-reload register (LPTIM_ARR) ................................................................................................. 312
LPTIM counter register (LPTIM_CNT)........................................................................................................ 312
Real time clock (RTC) ...............................................................................................................................................314
Introduction .......................................................................................................................................................... 314
Main feature.......................................................................................................................................................... 314
Function description ............................................................................................................................................. 316
RTC block diagram........................................................................................................................................ 316
GPIO controlled by RTC............................................................................................................................... 317
RTC register write protection ........................................................................................................................ 317
RTC clock and prescaler................................................................................................................................ 317
RTC calendar................................................................................................................................................. 318
Calendar initialization and configuration ......................................................................................................318
Calendar reading............................................................................................................................................ 319
Calibration clock output ................................................................................................................................ 320
Programmable Alarm..................................................................................................................................... 320
Alarm configuration..................................................................................................................................... 320
Alarm output................................................................................................................................................ 320
Periodic automatic wakeup.......................................................................................................................... 321
Wakeup timer configuration ........................................................................................................................ 321
Timestamp function..................................................................................................................................... 321
Tamper detection ......................................................................................................................................... 322
Daylight saving time configuration ............................................................................................................. 323
RTC reset..................................................................................................................................................... 323
RTC sub-second register shift operation...................................................................................................... 323
RTC digital clock precision calibration ....................................................................................................... 323
RTC low power mode..................................................................................................................................325
RTC Registers....................................................................................................................................................... 325
RTC Register overview ................................................................................................................................. 325
RTC Calendar Time Register (RTC_TSH).................................................................................................... 326
RTC Calendar Date Register (RTC_DATE)..................................................................................................327
RTC Control Register (RTC_CTRL)............................................................................................................. 328
RTC Initial Status Register (RTC_INITSTS)................................................................................................ 330
RTC Prescaler Register (RTC_PRE) ............................................................................................................. 332
RTC Wakeup Timer Register (RTC_WKUPT).............................................................................................. 333
RTC Alarm A Register (RTC_ALARMA)..................................................................................................... 333
RTC Alarm B Register (RTC_ ALARMB).................................................................................................... 334

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RTC Write Protection register (RTC_WRP)................................................................................................ 335
RTC Sub-second Register (RTC_SUBS)..................................................................................................... 336
RTC Shift Control Register (RTC_ SCTRL)............................................................................................... 336
RTC Timestamp Time Register (RTC_TST) ............................................................................................... 337
RTC Timestamp Date Register (RTC_TSD) ............................................................................................... 337
RTC Timestamp Sub-second Register (RTC_TSSS)................................................................................... 338
RTC Calibration Register (RTC_CALIB) ................................................................................................... 339
RTC Tamper Configuration Register（RTC_ TMPCFG）......................................................................... 339
RTC Alarm A sub-second register (RTC_ ALRMASS)............................................................................... 342
RTC Alarm B sub-second register (RTC_ ALRMBSS)............................................................................... 343
RTC Option Register (RTC_ OPT).............................................................................................................. 344
RTC Backup registers (RTC_ BKP(1~20)) ................................................................................................. 344
Independent watchdog (IWDG) ...............................................................................................................................345
Introduction .......................................................................................................................................................... 345
Main features........................................................................................................................................................ 345
Function description ............................................................................................................................................. 346
Register access protection ............................................................................................................................. 346
Debugging mode ........................................................................................................................................... 347
User interface........................................................................................................................................................ 347
Operate flow.................................................................................................................................................. 347
IWDG configuration flow ............................................................................................................................. 348
IWDG registers..................................................................................................................................................... 348
IWDG register overview ............................................................................................................................... 348
IWDG key register (IWDG_KEY)................................................................................................................ 349
IWDG pre-scaler register (IWDG_PREDIV)................................................................................................ 349
IWDG reload register (IWDG_RELV).......................................................................................................... 350
IWDG status register (IWDG_STS).............................................................................................................. 350
Window watchdog (WWDG)....................................................................................................................................352
Introduction .......................................................................................................................................................... 352
Main features........................................................................................................................................................ 352
Function description ............................................................................................................................................. 352
Timing for refresh watchdog and interrupt generation ......................................................................................... 353
Debug mode.......................................................................................................................................................... 354
User interface........................................................................................................................................................ 354
WWDG configuration flow........................................................................................................................... 354
WWDG registers .................................................................................................................................................. 355
WWDG register overview............................................................................................................................. 355
WWDG control register (WWDG_CTRL).................................................................................................... 355
WWDG config register (WWDG_CFG)....................................................................................................... 355
WWDG status register (WWDG_STS)......................................................................................................... 356
Analog to digital conversion (ADC) .............................................................................................................................357
Introduction .......................................................................................................................................................... 357
Main features .......................................................................................................................................................... 357
Function Description ............................................................................................................................................ 358
ADC clock ...................................................................................................................................................... 359
ADC switch control ......................................................................................................................................... 360
Channel selection ............................................................................................................................................ 361
Internal channel ............................................................................................................................................. 363
Single conversion mode ................................................................................................................................... 363
Continuous conversion mode .......................................................................................................................... 363
Timing diagram ............................................................................................................................................... 363
Analog watchdog ............................................................................................................................................. 364
Scanning mode ................................................................................................................................................ 365
Injection channel management ....................................................................................................................... 365

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Discontinuous mode ...................................................................................................................................... 366
Calibration............................................................................................................................................................ 367
Data aligned ........................................................................................................................................................... 367
Programmable channel sampling time ..................................................................................................................... 368
Externally triggered conversion ............................................................................................................................... 368
DMArequests....................................................................................................................................................... 369
Temperature sensor ................................................................................................................................................. 369
Temperature sensor using flow...................................................................................................................... 370
ADC interrupt..................................................................................................................................................... 371
ADC registers...................................................................................................................................................... 371
ADC register overview ................................................................................................................................. 371
ADC status register (ADC_STS) .................................................................................................................... 372
ADC control register 1 (ADC_CTRL1)....................................................................................................... 374
ADC control register 2 (ADC_CTRL2)....................................................................................................... 376
ADC sampling time register 1 (ADC_SAMPT1) ........................................................................................ 378
ADC sampling time register 2 (ADC_ SAMPT2) ....................................................................................... 378
ADC injected channel data offset register x (ADC_JOFFSETx)(x=1…4) .................................................. 379
ADC watchdog high threshold register (ADC_WDGHIGH) ........................................................................... 379
ADC watchdog low threshold register (ADC_WDGLOW) ............................................................................. 380
ADC regular sequence register 1 (ADC_RSEQ1) ..................................................................................... 380
ADC regular sequence register 2 (ADC_RSEQ2) ..................................................................................... 381
ADC regular sequence register 3 (ADC_RSEQ3) ..................................................................................... 381
ADC Injection sequence register (ADC_JSEQ) ............................................................................................. 382
ADC injection data register x (ADC_JDATx) (x= 1…4) .......................................................................... 382
ADC regulars data register (ADC_DAT) ...................................................................................................... 383
ADC differential mode selection register (ADC_DIFSEL)....................................................................... 383
ADC calibration factor (ADC_CALFACT)............................................................................................... 384
ADC control register 3 (ADC_CTRL3)..................................................................................................... 384
ADC sampling time register 3 (ADC_SAMPT3) ...................................................................................... 386
Digital to analog conversion (DAC)..........................................................................................................................386
Introduction .......................................................................................................................................................... 386
Main features........................................................................................................................................................ 387
DAC function description and operation description ........................................................................................... 389
DAC enable................................................................................................................................................... 389
DAC output buffer......................................................................................................................................... 389
DAC data format ........................................................................................................................................... 389
DAC trigger................................................................................................................................................... 390
DAC conversion............................................................................................................................................ 390
DAC output voltage....................................................................................................................................... 391
DMArequests................................................................................................................................................ 391
The noise ....................................................................................................................................................... 391
Triangular wave generation ........................................................................................................................... 392
DAC register......................................................................................................................................................... 394
DAC registers overview ................................................................................................................................ 394
DAC control register (DAC_CTRL) ............................................................................................................. 394
DAC software trigger register (DAC_SOTTR)............................................................................................. 396
12 bit right aligned data hold register for DAC (DAC_DR12CH)................................................................ 396
12 bit left aligned data hold register for DAC (DAC_DL12CH) ..................................................................396
8-bit right-aligned data hold register for DAC (DAC_DR8CH) ................................................................... 397
DAC data output register (DAC_DATO) ......................................................................................................397
Comparator (COMP) ................................................................................................................................................399
COMP system connection block diagram............................................................................................................. 399
COMP features ..................................................................................................................................................... 400
COMP configuration process................................................................................................................................ 400
COMP working mode........................................................................................................................................... 401
Window mode................................................................................................................................................ 401

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Independent comparator................................................................................................................................ 401
Comparator interconnection ................................................................................................................................. 401
Interrupt................................................................................................................................................................ 402
COMP register...................................................................................................................................................... 403
COMP register overview............................................................................................................................... 403
COMP interrupt enable register (COMP_INTEN) ........................................................................................ 404
COMP low power select register (COMP_LPCKSEL)................................................................................. 404
COMP window mode register (COMP_WINMODE)................................................................................... 405
COMP lock register (COMP_LOCK) ........................................................................................................... 405
COMP control register (COMP1_CTRL)...................................................................................................... 406
COMP filter register (COMP1_FILC)........................................................................................................... 408
COMP filter frequency division register (COMP1_FILP) ............................................................................ 408
COMP control register (COMP2_CTRL)...................................................................................................... 409
COMP filter register (COMP2_FILC)......................................................................................................... 410
COMP filter frequency division register (COMP2_FILP)........................................................................... 411
COMP output select register (COMP2_OSEL)........................................................................................... 411
COMP reference voltage register (COMP_VREFSCL) .............................................................................. 412
COMP test register(COMP_TEST)............................................................................................................. 412
COMP interrupt status register (COMP_INTSTS)...................................................................................... 413
Operational Amplifier (OPAMP).............................................................................................................................. 414
Main features........................................................................................................................................................ 414
OPAMP function description......................................................................................................................... 414
OPAMP working mode......................................................................................................................................... 415
OPAMP independent op amp mode............................................................................................................... 415
OPAMP follow mode..................................................................................................................................... 416
OPAMP internal gain (PGA) mode ............................................................................................................... 417
OPAMP with filtered internal gain mode ...................................................................................................... 418
OPAMP calibration........................................................................................................................................ 419
OPAMP Independent write protection........................................................................................................... 419
OPAMP TIMER controls the switching mode............................................................................................... 419
OPAMP register.................................................................................................................................................... 419
OPAMP register overview............................................................................................................................. 419
OPAMP Control Status Register (OPAMP1_CS).......................................................................................... 420
OPAMP Control Status Register (OPAMP2_CS).......................................................................................... 421
OPAMP Lock register (OPAMP_LOCK)...................................................................................................... 423
I2C interface ............................................................................................................................................................... 424
Introduction .......................................................................................................................................................... 424
Main features........................................................................................................................................................ 424
Function description ............................................................................................................................................. 424
SDAand SCL line control............................................................................................................................. 425
Software communication process.................................................................................................................. 425
Error conditions description .......................................................................................................................... 435
DMA application ........................................................................................................................................... 436
Packet error check ......................................................................................................................................... 437
SMBus........................................................................................................................................................... 438
Debug mode.......................................................................................................................................................... 440
Interrupt request.................................................................................................................................................... 440
I2C registers.......................................................................................................................................................... 441
I2C register overview .................................................................................................................................... 441
I2C Control register 1 (I2C_CTRL1) ............................................................................................................ 442
I2C Control register 2 (I2C_CTRL2) ............................................................................................................ 444
I2C Own address register 1 (I2C_OADDR1)................................................................................................ 445
I2C Own address register 2 (I2C_OADDR2)................................................................................................ 446
I2C Data register (I2C_DAT) ........................................................................................................................ 446
I2C Status register 1 (I2C_STS1).................................................................................................................. 447
I2C Status register 2 (I2C_STS2).................................................................................................................. 450