Atmel AT91CAP9A-DK User manual

6321B–CAP–02-Jul-07
AT91CAP9A-DK Development Kit
....................................................................................................................
User Guide

1-2 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07

AT91CAP9A-DK Development Kit User Guide i
6321B–CAP–02-Jul-07
Table of Contents
Section 1
AT91CAP9A-DK Development Board
and AT91CAP-DKM Motherboard
Overview ....................................................................................................................1-1
1.1 Scope................................................................................................................................. 1-1
1.2 Purpose.............................................................................................................................. 1-2
Section 2
Setting Up the AT91CAP-DKM Motherboard .............................................................2-1
2.1 Electrostatic Warning......................................................................................................... 2-1
2.2 Requirements..................................................................................................................... 2-1
2.3 Layout ................................................................................................................................ 2-1
2.4 Powering Up the Board...................................................................................................... 2-2
Section 3
AT91CAP-DKM Motherboard.....................................................................................3-1
3.1 Block Diagram.................................................................................................................... 3-2
3.2 Clock Circuity ..................................................................................................................... 3-3
3.3 Reset Circuity..................................................................................................................... 3-3
3.4 Shutdown Controller ..........................................................................................................3-3
3.5 Power Supply Circuity........................................................................................................3-3
3.6 Memory.............................................................................................................................. 3-3
3.7 Remote Communication .................................................................................................... 3-3
3.7.1 CAN Interface ...................................................................................................... 3-3
3.7.2 Host USB Interface.............................................................................................. 3-3
3.7.3 Device USB Interface .......................................................................................... 3-4
3.7.4 Ethernet Interface ................................................................................................ 3-4
3.8 Audio Stereo Interface .......................................................................................................3-4
3.8.1 AC97.................................................................................................................... 3-4
3.8.2 I2S ....................................................................................................................... 3-4
3.9 Analog Interface................................................................................................................. 3-4
3.10 User Interface .................................................................................................................... 3-4
3.11 Debug Interface ................................................................................................................. 3-5
3.12 Memory Expansion Slots ................................................................................................... 3-5
3.13 PIO Connectors ................................................................................................................. 3-5
3.14 FPGA Extension ................................................................................................................ 3-5
3.14.1 Overview.............................................................................................................. 3-5

Table of Contents (Continued)
ii AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
3.14.2 AT91CAP-DKM Extension Connectors ............................................................... 3-6
3.14.3 “Mistral” Extension Connectors............................................................................ 3-6
3.14.4 USB Device interfaces....................................................................................... 3-23
3.15 AT91CAP9 Mezzanine Extension.................................................................................... 3-24
3.16 PIO Usage ....................................................................................................................... 3-24
Section 4
AT91CAP-DKM Configuration....................................................................................4-1
4.1 Configuration...................................................................................................................... 4-1
4.2 Configuration Jumpers and Straps .................................................................................... 4-1
Section 5
Overview AT91CAP9A-DKZ Mezzanine ....................................................................5-1
5.1 Scope................................................................................................................................. 5-1
5.2 Purpose.............................................................................................................................. 5-1
Section 6
Setting Up the AT91CAP9A-DKZ Mezzanine ............................................................6-1
6.1 Electrostatic Warning......................................................................................................... 6-1
6.2 Requirements..................................................................................................................... 6-1
6.3 Layout ................................................................................................................................ 6-1
6.3.1 AT91CAP9 Specific ............................................................................................. 6-1
6.3.2 FPGA Specific (Altera Stratix-II EP2S90F1020C5) ............................................. 6-2
6.4 Powering Up the Board...................................................................................................... 6-2
Section 7
AT91CAP9A-DKZ Mezzanine Board..........................................................................7-1
7.1 Block Diagram.................................................................................................................... 7-2
7.2 Reset Path ......................................................................................................................... 7-4
7.3 Clocking Paths ................................................................................................................... 7-4
7.3.1 AT91CAP9 Clock Sources................................................................................... 7-4
7.3.2 FPGA Clock Sources........................................................................................... 7-4
7.4 Power Supply Circuitry.......................................................................................................7-4
7.5 Memory.............................................................................................................................. 7-4
7.6 Host USB Port.................................................................................................................... 7-5
7.7 FPGA Connections ............................................................................................................ 7-5
7.7.1 FPGA Banking Allocations................................................................................... 7-5
7.7.2 CAP/MPIO Bus Connections............................................................................... 7-5
7.7.3 SODIMM Connection........................................................................................... 7-9
7.7.4 PISMO-II Connector .......................................................................................... 7-13
7.7.5 User LEDs and I/O Grid..................................................................................... 7-22

Table of Contents (Continued)
AT91CAP9A-DK Development Kit User Guide iii
6321B–CAP–02-Jul-07
7.7.6 FPGA Pinout Tables.......................................................................................... 7-25
Section 8
AT91CAP9A-DKZ Configuration ................................................................................8-1
8.1 Configuration...................................................................................................................... 8-1
8.2 Configuration Items............................................................................................................ 8-2
Section 9
Overview AT91CAP-MEM18 (CAP 1.8V Memory Board) ..........................................9-1
9.1 Scope................................................................................................................................. 9-1
9.2 Purpose.............................................................................................................................. 9-1
Section 10
Setting Up the AT91CAP-MEM18 Board .................................................................10-1
10.1 Electrostatic Warning.......................................................................................................10-1
10.2 Requirements................................................................................................................... 10-1
10.3 Layout .............................................................................................................................. 10-1
10.4 Powering Up the Board.................................................................................................... 10-2
Section 11
AT91CAP-MEM18 Configuration .............................................................................11-1
11.1 Configuration.................................................................................................................... 11-1
Section 12
Overview AT91CAP-MEM33 (CAP 3.3V Memory Board) ........................................12-1
12.1 Scope............................................................................................................................... 12-1
12.2 Purpose............................................................................................................................ 12-1
Section 13
Setting Up the AT91CAP-MEM33 Board .................................................................13-1
13.1 Electrostatic Warning.......................................................................................................13-1
13.2 Requirements................................................................................................................... 13-1
13.3 Layout .............................................................................................................................. 13-1
13.4 Powering Up the Board.................................................................................................... 13-2
Section 14
AT91CAP-MEM33 Configuration .............................................................................14-1
14.1 Configuration.................................................................................................................... 14-1
Section 15
AT91CAP-DKM Schematics.....................................................................................15-1
15.1 Schematics ...................................................................................................................... 15-1

Table of Contents (Continued)
iv AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
Section 16
AT91CAP9A-DKZ Schematics .................................................................................16-1
16.1 Schematics ...................................................................................................................... 16-1
Section 17
AT91CAP-MEM18 Schematics ................................................................................17-1
17.1 Schematics ...................................................................................................................... 17-1
Section 18
AT91CAP-MEM33 Schematics ................................................................................18-1
18.1 Schematics ...................................................................................................................... 18-1
Section 19
Errata........................................................................................................................19-1
19.1 Known Errata ................................................................................................................... 19-1
Section 20
Revision History .......................................................................................................20-1
20.1 Revision History ............................................................................................................... 20-1

AT91CAP9A-DK Development Kit User Guide 1-1
6321B–CAP–02-Jul-07
Section 1
AT91CAP9A-DK Development Board
and AT91CAP-DKM Motherboard
Overview
1.1 Scope
The AT91CAP9/Altera®development board (AT91CAP9A-DK) or “kit” is composed of three associated
boards, namely Motherboard, Mezzanine and Memory Extension to be used jointly in order to develop
AT91CAP9 processor applications.
The AT91CAP9A-DK development board implements the fixed portion of the AT91CAP9 device as a
microcontroller standard product, tightly coupled to a high-density FPGA that emulates the MP Block.
The boards also include a range of memories and physical interfaces/connectors representing external
system components. This configuration enables parallel hardware/software testing of the application
under development at close to operational speed, with no penalty for hardware modifications. This
enables software development to proceed in parallel with hardware development, and significantly
reduces the design cycle time, increasing confidence in a right-first-time system solution.
Section 1 through Section 4provide essential usage documentation for the AT91CAP-DKM
Motherboard.

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Figure 1-1. Overview of AT91CAP9A-DK Development Kit/AT91CAP-DKM Motherboard
1.2 Purpose
The AT91CAP-DKM Motherboard provides all the service items of an AT91CAP9A-DK development
system. That is:
Power supply input, conversion and distribution,
Standard user interfaces,
Prototyping interface and extension means.
Memory extension
CAP Mezzanine
Motherboard

AT91CAP9A-DK Development Kit User Guide 2-1
6321B–CAP–02-Jul-07
Section 2
Setting Up the AT91CAP-DKM Motherboard
2.1 Electrostatic Warning
Upon delivery, the AT91CAP-DKM motherboard is wrapped in a protective anti-static bag. The board
must not be exposed to electrostatic discharges. A grounding strap or similar protective device should be
worn when handling the board. Avoid touching the component pins or any other on-board metallic
element.
2.2 Requirements
In order to set up an AT91CAP9A-DK development system, the following items are needed:
AT91CAP-DKM motherboard
PC/ATX standard power supply unit
AT91CAP9A-DKZ mezzanine board (see Sections 5 through 8), with a memory extension (see
sections 9 through 14)
2.3 Layout
The AT91CAP-DKM motherboard features the following on-board interfaces:
ATX power supply connector
2x Full-speed Host USB interfaces
100-base TX Ethernet PHY with three status LEDs
DBGU serial communication port
4x analog inputs
AC97 interface with three 3.5 mm audio jack connectors (MIC IN, LINE IN, LINE OUT)
I2S audio codec with two 3.5 mm audio jack connectors (LINE IN, LINE OUT)
2x SD/MMC card slots
Atmel TWI serial EEPROM
1/4 inch TFT LCD VGA interface
Touch Screen Controller
Image Sensor expansion connector
16 push buttons arranged in a keypad form
CAN bus interface
Software controlled Power LED
2x general-purpose LEDs

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6321B–CAP–02-Jul-07
PIO expansion connectors (PIOA, PIOB, PIOC, PIOD)
CAP Mezzanine extension connectors (2x 320 pins)
PCI64 form FPGA I/O extension connector
Custom mezzanine-style FPGA I/O extension connector
3x USB device PHY interfaces with USB B connectors (FPGA controlled)
Figure 2-1. AT91CAP-DKM Motherboard Layout - Top View
2.4 Powering Up the Board
A complete AT91CAP9A-DK system is powered through the AT91CAP-DKM motherboard via a stan-
dard ATX PC power supply.
The power control signal is connected to the SHDN signal, generated by the AT91CAP9 chip from the
AT91CAP9A-DKZ mezzanine board.
In case the AT91CAP-DKM motherboard has to be powered without a mezzanine or an AT91CAP9 chip
in place, the “Force Power ON” jumper J5 must be installed.
Dual
Host USB
interface
Ethernet
interface
DBGU port
4x analog
inputs
CAP mezzanine site
ATX power
supply header
CAN
interface
3x Device USB ports
FPGA IO - J9
PCI64 connector
Push buttons keyboard
and user LEDs
AC97
interface
I2S
interface
SD/MMC card slots
TFT LCD
interface
PIO
connectors
ISI interface
FPGA IO
"Mistral"
connection
J10
J8

AT91CAP9A-DK Development Kit User Guide 3-1
6321B–CAP–02-Jul-07
Section 3
AT91CAP-DKM Motherboard

3-2 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
3.1 Block Diagram
Figure 3-1. AT91CAP-DKM Motherboard (see the complete schematic in Section 15, “AT91CAP-DKM Schematics”
..31]..31]..31] ..31]
LCDD[10..15]
J23
J24
J26
J21
page 7, 8
J35, J36
J30, J31,J32
J33
page 10,11,12
ETXCK
ETXEN
ETX0
ETX1
ERX0
ERX1
ERXER
ERXDV
EMDIO
EMDC
NRST
PB11
DTXD
DRXD
CANTX
CANRX
PC12
HDMA
HDPA
HDMB
HDPB
TWD
TWCK
AC97FS
AC97CK
AC97TX
AC97RX
NRST
TF1
TK1
TD1
RD1
TF0
TK0
TD0
RD0
BCK
DATAI
DATAO
WS
PCK1
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AC97 I2S ETHERNET USB CANADC
J3-3
J3-3
7
8
9
J3-4
J3-4
10
11
12
SOUND & ADC
EXTCLK
SDATA_OUT
SYNC
RST#
BITCLK
SDATA_IN
SYSCLK
L3DATA
L3CLOCK
ADC1
ADC3
ADC4
ADC2
GND
5V
3V3
DATAO
BCK
DATAI
WS
J1-1
J1-1
1
2
3
J1-2
J1-2
4
5
6
J1-3
J1-3
7
8
9
J3-1
J3-1
1
2
3
J1-4
J1-4
10
11
12
COMMUNICATION
DRXD
DTXD
CANRS
CANTX
CANRX
HDMA
HDPA
HDMB
HDPB
NRST
TXD0
TXD1
TX_EN
RXD0
RXD1
RX_DV
RX_ER
MDINTR
MDC
MDIO
TX_CLK
GND
3V3
5V
J3-2
J3-2
4
5
6
NRST
LCDD[18..23]
LCDD[2..7]
LCDHSYNC
LCDDOTCK
LCDDEN
PWM0
PC0
SPI0_MOSI
SPI0_MISO
SPI0_SPCK
PC4
PC5
FPGA[0..275]
FPGA[0..275]
NRST
FPGA[0..275]
PB[0..31]
PC[0..31]
PD[0..31]
PA[0..31]
HDMA
HDPA
HDMB
HDPB
VDDIOP1
SPI0_NPCS3
SPI0_NPCS2
VCCIO3
VCCIO2
VCCIO1
LCD
page 2
J4
page 3
J6, J7
FPGA UPSTREAM
FPGA[0..275]
GND
3V3
VCCIO3
MEZZANINE CONNECTORS
FPGA[0..275]
WKUP
HDMA
VDDIOP1
HDMB
PC[0..31]
NRST
PA[0..31]
PD[0..31]
PB[0..31]
HDPA
SHDN
HDPB
2V5
1V8
GND
1V2
5V
3V3
VCCIO1
VCCIO2
VCCIO3
LCD & TSC
IRQ
SPCK
BUSY
MOSI
MISO
NPCS
B[0..5]
G[0..5]
R[0..5]
PCI
VCTRL
DTMG
HSYNC
DCLK
GND
3V3
ATX POWER SUPPLY
SHDN
12V
2V5
1V8
-12V
GND
1V2
5V
3V3
J2
J2
1
2
3
FPGA CONNECTORS
FPGA[0..275]
NRST
12V
-12V
GND
5V
VCCIO1
VCCIO2
VCCIO3
page 4 J12 J14 J16
page 5 page 13
PB[0..31]
PC[0..31]
PA[0..31]
PD[6..13]
PWM3
PWM1
PWM2
PD[0..31]
UI & PIO CONNECTORS
PB[0..31]
PA[0..31]
PD[0..31]
PC[0..31]
KBD[0..7]
PWRLED
USERLED1
USERLED2
GND
3V3
page 6
ISI_D[0..11]
ISI_MCK
ISI_VSYNC
ISI_HSYNC
ISI_PCK
PA14
PA15
VDDIOP1
TWD
TWCK
PC20
PC21
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_CDA
MCI1_CK
MCI0_CDA
MCI0_CK
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCIMCIISI
(PA0 (PA3 (PA4 (PA5 (PA1 (PA2
SERIAL DEVICES
ISI_D[0..11]
CTRL1
SCL
CTRL2
SDA
ISI_VSYNC
ISI_HSYNC
ISI_MCK
ISI_PCK
MCI0_DA3
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_CDA
MCI0_CD
MCI1_CD
MCI1_DA3
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_CDA
MCI1_CK
MCI0_CK
VDDIOP1
2V5
1V8
GND
3V3
J28 J29
page 9
/SPI0_MISO)
CAP9 PIO USAGE
/SPI0_NPCS1) /SPI0_NPCS1) /SPI0_NPCS0) /SPI0_MOSI) /SPI0_SPCK)
PD24
PD29
PD30
PD31
PD28
PD[0
PD0 SPI0_NPCS2
PA1 MCI0_CDA
PA2 MCI0_CK
PA3 MCI0_DA1
PA5 MCI0_DA3
PA6 AC97FS
PA7 AC97CK
PA4 MCI0_DA2
PA9 AC97RX
PA10 PWM1
PA11 PWM3
PA8 AC97TX
PA13 CANRX
PA14
PA15
PA12 CANTX
PA17 ISI_D1
PA18 ISI_D2
PA19 ISI_D3
PA16 ISI_D0
PA21 ISI_D5
PA22 ISI_D6
PA23 ISI_D7
PA20 ISI_D4
PA25 ISI_HSYNC
PA26 ISI_VSYNC
PA27 ISI_MCK
PA24 ISI_PCK
PA29 ISI_D9
PA30 ISI_D10
PA31 ISI_D11
PA28 ISI_D8
PB1 TK0
PB2 TD0
PB3 RD0
PB5 TWCK
PB6 TF1
PB7 TK1
PB4 TWD
PB9 RD1
PB10 PCK1
PB11
PB8 TD1
PB13 AD0
PB14 AD1
PB15 AD2
PB12
PB17 AD4
PB18 AD5
PB19 AD6
PB16 AD3
PB21 ETXCK
PB22 ERXDV
PB23 ETX0
PB20 AD7
PB25 ERX0
PB26 ERX1
PB27 ERXER
PB24 ETX1
PB29 EMDC
PB30 EMDIO
PB31
PB28 ETXEN
PB[0
PB0 TF0
PA[0
PC1 LCDHSYNC
PC2 LCDDOTCK
PC3 LCDDEN
PC5
PC6 LCDD2
PC7 LCDD3
PC4
PC9 LCDD5
PC10 LCDD6
PC11 LCDD7
PC8 LCDD4
PC13
PC14 LCDD10
PC15 LCDD11
PC12
PC17 LCDD13
PC18 LCDD14
PC19 LCDD15
PC16 LCDD12
PC21
PC22 LCDD18
PC23 LCDD19
PC20
PC25 LCDD21
PC26 LCDD22
PC27 LCDD23
PC24 LCDD20
PC29 PWM2
PC30 DRXD
PC31 DTXD
PC28 PWM0
PC[0
PC0
PA0 MCI0_DA0
PD1 SPI0_NPCS3
PD2
PD3
PD5
PD6
PD7
PD4
PD9
PD10
PD11
PD8
PD13
PD14
PD15
PD12
PD17
PD18
PD19
PD16
PD21
PD22
PD23
PD20
PD25
PD26
PD27
SPI0_MISO PA0
SPI0_MOSI PA1
SPI0_SPCK PA2
MCI1_CDA
PA17
MCI1_CK
PA16
MCI1_DA0
PA18
MCI1_DA1
PA19
MCI1_DA2
PA20
MCI1_DA3
PA21
4X4 KEYPADS
(ISI_CTRL1) (ISI_CTRL2)
(ETH_MDINTR)
(MCI0_CD) (MCI1_CD) (LCD_PCI) (LCD_IRQ) (LCD_BUSY) (CANRS)
(KBD0) (KBD1) (KBD2) (KBD3) (KBD4) (KBD5) (KBD6) (KBD7)

AT91CAP9A-DK Development Kit User Guide 3-3
6321B–CAP–02-Jul-07
3.2 Clock Circuity
There are two on-board clock sources:
24.576 MHz standard crystal for the AC97 audio interface
50.000 MHz oscillator for the RMII Ethernet interface
3.3 Reset Circuity
The AT91CAP9A-DKZ mezzanine board generates the NRST signal for the whole system.
3.4 Shutdown Controller
The SHDN signal issued by the Reset Controller of the AT91CAP9 chip is provided by the AT91CAP9A-
DKZ mezzanine board and routed to the ATW connector, in order to control the power supply unit.
As explained in Section 2.4 “Powering Up the Board” on page 2-2, the remote controlling of the power
supply can be bypassed with jumper J5.
3.5 Power Supply Circuity
The AT91CAP-DKM motherboard derives the necessary system voltages from the ATX supply.
On-board switching regulators provide the following voltage sources:
1.2V
1.8V
2.5V
3.6 Memory
The only memory resource available on the AT91CAP-DKM motherboard is an Atmel serial EEPROM
(TWI bus connection).
System memory resources are to be connected directly to the AT91CAP9A-DKZ mezzanine via the
AT91CAP9-MEMxx extension boards.
3.7 Remote Communication
3.7.1 CAN Interface
The AT91CAP-DKM board features one serial CAN 2.0B communication port which is physically con-
nected to a J24 3-way screw-style connector.
An on-board standard 120-Ohm terminator is available. Simply install jumper J25 to enable termination.
3.7.2 Host USB Interface
A dual host connection (J26 = dual Type A socket) is available on the AT91CAP-DKM motherboard.

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These two ports are routed directly from/to the AT91CAP9 chip installed on the mezzanine. In function of
the AT91CAP9 chip connected in the system, these two ports can be non operating. For further informa-
tion, please refer to the documentation specific to the mezzanine you intend to use.
3.7.3 Device USB Interface
Please refer to Section 3.14 “FPGA Extension” on page 3-5.
3.7.4 Ethernet Interface
On-board RMII 100-base TX PHY: DM9161 MN7 connected to a standard RJ45 socket J21. Three sta-
tus LEDs (DS4, 5, 6) provide network activity feedback.
3.8 Audio Stereo Interface
3.8.1 AC97
One AC97 2.3 compliant Codec (MN11 = AD1981B, 20-bit PCM DAC) with the following connectors:
32-ohm stereo headset line-out
stereo line input
stereo electret microphone input
This interface has some configuration elements. Please refer to Section 4 “AT91CAP-DKM Configura-
tion” and/or “AT91CAP-DKM Schematics” for in-depth details.
3.8.2 I2S
One I2S audio codec MN14 = UDA1342TS with the following connectors:
line-out
line-in
3.9 Analog Interface
Four analog inputs (range up to 3.3V). These are available through the J33 connector and are buffered
by a quadruple gain-1 amplifier, MN12 = AD8040ARZ.
These four buffered signals can be connected to the eight AT91CAP9 analog input channels via the four
configuration jumpers J3-1 to J3-4. Refer to Table 4-1 for more details.
3.10 User Interface
The various items interfaced with the AT91CAP-DKM motherboard are all driven by the PIO busses of
the AT91CAP9 chip. (Refer to “AT91CAP-DKM Schematics” for detailed assignation)
4x4 keypad: uses 8 PIO lines in a matrix scheme, each button shunts two of them
Two green LEDs
One yellow power LED (note that it is software controlled)
One 3.5 inch VGA display LCD with Touch Panel and white LED backlight

AT91CAP9A-DK Development Kit User Guide 3-5
6321B–CAP–02-Jul-07
One ISI connector (camera interface)
3.11 Debug Interface
The AT91CAP standard serial debug interface (DBGU) is carried through the DB9 male socket, J23. It is
routed to the DBGU port of the AT91CAP9 chip installed on the mezzanine.
3.12 Memory Expansion Slots
Two memory card dedicated connectors:
J28 for DataFlash, SD/SDIO/MMC card slot
J29 for SD/SDIO/MMC card slot
Note that both adopt the same connector but that J28 is also DataFlash®compatible due to its signal
muxing (refer to “PIO Usage” on page 3-24, (PIO A muxing table) and “AT91CAP-DKM Schematics”).
3.13 PIO Connectors
All PIOs of the AT91CAP9 are routed to peripheral extension connectors (J17 to J20). This allows the
developer to add external hardware components or boards.
Note: Most of the PIO lines already have an assignment on board. Therefore be aware of the
schematic routing prior to customizing these lines in any way. Do not cause electrical con-
tention as this may potentially damage the boards and the AT91CAP9 chip.
3.14 FPGA Extension
3.14.1 Overview
The AT91CAP-DKM motherboard routes most of the FPGA IOs coming from the mezzanine to on-board
prototyping ports (free for custom user board implementation). These are grouped on sheet 4/13 of Sec-
tion 15 “AT91CAP-DKM Schematics”:
J9 = PCI64 female connector for FPGA I/O expansion
J8/J10 = two 200-pin connectors for “Mistral” extension board
Warning: FPGA IOs are distributed among J8, J9 and J10 connectors and also the three USB device
ports, some having dual connections as follows:

3-6 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
3.14.2 AT91CAP-DKM Extension Connectors
Figure 3-2. J8 and J10 (Top View)
3.14.3 “Mistral” Extension Connectors
Pins not listed in Table 3-2 below are not connected.
Table 3-1. FPGA IO Overlapping Table
Net Name Range J8 J10 J9 USB
FPGA000
FPGA001
FPGA004..FPGA 093
FPGA098..FPGA117
X
FPGA250..FPGA 252
FPGA260..FPGA 262 XX
FPGA118..FPGA174 X
FPGA175..FPGA 189
FPGA191..FPGA 228
FPGA270
XX
FPGA229..FPGA245 X
FPGA190
FPGA246..FPGA 249
FPGA253..FPGA 259
FPGA263..FPGA 269
FPGA271..FPGA 275
XX
FPGA002
FPGA003
FPGA094..FPGA 097
X
1
J10
6
5
10
196
J8 and J10 as seen on AT91CAP9-DKM from above
200
1
J8
65
10
196 200

AT91CAP9A-DK Development Kit User Guide 3-7
6321B–CAP–02-Jul-07
Table 3-2. J-8 (male) Pin Assignment Table
J8 Pin
FPGA
Bank
FPGA Pin
Function
Other FPGA Pin
Information FPGA Ball Board Net
1 B1 IO CLK2p/DIFFIO_RX_C1p U32 FPGA0
2 GND
3 B1 IO CLK2n/DIFFIO_RX_C1n U31 FPGA1
4 GND
5 B3 IO DQ15T E26 FPGA250
6 B3 IO F21 FPGA251
7 GND
8 B1 IO DIFFIO_RX28p V31 FPGA4
9 GND
10 B1 IO DIFFIO_RX28n V30 FPGA5
11 B1 IO DIFFIO_TX28p U23 FPGA6
12 GND
13 B1 IO DIFFIO_TX28n U22 FPGA7
14 GND
15 B1 IO DIFFIO_RX27p W32 FPGA8
16 B1 IO DIFFIO_RX27n W31 FPGA9
17 GND
18 B1 IO DIFFIO_TX27p U28 FPGA10
19 GND
20 B1 IO DIFFIO_TX27n U27 FPGA11
21 B1 IO DIFFIO_RX26p AA32 FPGA12
22 GND
23 B1 IO DIFFIO_RX26n AA31 FPGA13
24 GND
25 B1 IO DIFFIO_TX26p V29 FPGA14
26 B1 IO DIFFIO_TX26n V28 FPGA15
27 GND
28 B1 IO DIFFIO_RX25p Y31 FPGA16
29 GND
30 B1 IO DIFFIO_RX25n Y30 FPGA17
31 B1 IO DIFFIO_TX25p V24 FPGA18
32 GND
33 B1 IO DIFFIO_TX25n V23 FPGA19
34 GND
35 B1 IO DIFFIO_RX24p AB32 FPGA20
36 B1 IO DIFFIO_RX24n AB31 FPGA21

3-8 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
37 GND
38 B1 IO DIFFIO_TX24p W29 FPGA22
39 GND
40 B1 IO DIFFIO_TX24n W28 FPGA23
41 B1 IO DIFFIO_RX23p AA30 FPGA24
42 GND
43 B1 IO DIFFIO_RX23n AA29 FPGA25
44 GND
45 B1 IO DIFFIO_TX23p W27 FPGA26
46 B1 IO DIFFIO_TX23n W26 FPGA27
47 GND
48 B1 IO DIFFIO_RX22p Y29 FPGA28
49 GND
50 B1 IO DIFFIO_RX22n Y28 FPGA29
51 B1 IO DIFFIO_TX22p W25 FPGA30
52 GND
53 B1 IO DIFFIO_TX22n W24 FPGA31
54 GND
55 B1 IO DIFFIO_RX21p AB30 FPGA32
56 B1 IO DIFFIO_RX21n AB29 FPGA33
57 GND
58 B1 IO DIFFIO_TX21p Y27 FPGA34
59 GND
60 B1 IO DIFFIO_TX21n Y26 FPGA35
61 B1 IO DIFFIO_RX20p AC32 FPGA36
62 GND
63 B1 IO DIFFIO_RX20n AC31 FPGA37
64 GND
65 B1 IO DIFFIO_TX20p AA27 FPGA38
66 B1 IO DIFFIO_TX20n AA26 FPGA39
67 GND
68 B1 IO DIFFIO_RX19p AB28 FPGA40
69 GND
70 B1 IO DIFFIO_RX19n AB27 FPGA41
71 B1 IO DIFFIO_TX19p Y25 FPGA42
72 GND
Table 3-2. J-8 (male) Pin Assignment Table (Continued)
J8 Pin
FPGA
Bank
FPGA Pin
Function
Other FPGA Pin
Information FPGA Ball Board Net

AT91CAP9A-DK Development Kit User Guide 3-9
6321B–CAP–02-Jul-07
73 B1 IO DIFFIO_TX19n Y24 FPGA43
74 GND
75 B1 IO DIFFIO_RX18p AD32 FPGA44
76 B1 IO DIFFIO_RX18n AD31 FPGA45
77 GND
78 B1 IO DIFFIO_TX18p W23 FPGA46
79 GND
80 B1 IO DIFFIO_TX18n W22 FPGA47
81 B1 IO DIFFIO_RX17p AE32 FPGA48
82 GND
83 B1 IO DIFFIO_RX17n AE31 FPGA49
84 GND
85 B1 IO DIFFIO_TX17p AD27 FPGA50
86 B1 IO DIFFIO_TX17n AD26 FPGA51
87 GND
88 B1 IO DIFFIO_RX16p AF32 FPGA52
89 GND
90 B1 IO DIFFIO_RX16n AF31 FPGA53
91 B1 IO DIFFIO_TX16p AC27 FPGA54
92 GND
93 B1 IO DIFFIO_TX16n AC26 FPGA55
94 GND
95 B1 IO DIFFIO_RX15p AG32 FPGA56
96 NRST
97 GND
98 B1 IO DIFFIO_RX15n AG31 FPGA57
99 GND
100 B1 IO DIFFIO_TX15p Y23 FPGA58
101 B1 IO DIFFIO_TX15n Y22 FPGA59
102 GND
103 B1 IO DIFFIO_RX14p AC30 FPGA60
104 GND
105 B1 IO DIFFIO_RX14n AC29 FPGA61
106 B1 IO DIFFIO_TX14p AA25 FPGA62
107 GND
108 B1 IO DIFFIO_TX14n AA24 FPGA63
Table 3-2. J-8 (male) Pin Assignment Table (Continued)
J8 Pin
FPGA
Bank
FPGA Pin
Function
Other FPGA Pin
Information FPGA Ball Board Net

3-10 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
109 GND
110 B1 IO DIFFIO_RX13p AD30 FPGA64
111 B1 IO DIFFIO_RX13n AD29 FPGA65
112 GND
113 B1 IO DIFFIO_TX13p AB26 FPGA66
114 GND
115 B1 IO DIFFIO_TX13n AB25 FPGA67
116 B1 IO DIFFIO_RX12p AH32 FPGA68
117 GND
118 B1 IO DIFFIO_RX12n AH31 FPGA69
119 GND
120 B1 IO DIFFIO_TX12p AA23 FPGA70
121 B1 IO DIFFIO_TX12n AA22 FPGA71
122 GND
123 B1 IO DIFFIO_RX11p AE30 FPGA72
124 GND
125 B1 IO DIFFIO_RX11n AE29 FPGA73
126 B1 IO DIFFIO_TX11p AB24 FPGA74
127 GND
128 B1 IO DIFFIO_TX11n AB23 FPGA75
129 GND
130 B1 IO DIFFIO_RX10p AJ32 FPGA76
131 B1 IO DIFFIO_RX10n AJ31 FPGA77
132 GND
133 B1 IO DIFFIO_TX10p AC25 FPGA78
134 GND
135 B1 IO DIFFIO_TX10n AC24 FPGA79
136 B1 IO DIFFIO_RX9p AF30 FPGA80
137 GND
138 B1 IO DIFFIO_RX9n AF29 FPGA81
139 GND
140 B1 IO DIFFIO_TX9p AD25 FPGA82
141 B1 IO DIFFIO_TX9n AD24 FPGA83
142 GND
143 B1 IO DIFFIO_RX8p AG30 FPGA84
144 GND
Table 3-2. J-8 (male) Pin Assignment Table (Continued)
J8 Pin
FPGA
Bank
FPGA Pin
Function
Other FPGA Pin
Information FPGA Ball Board Net