Nations N32G45 Series User manual

N32G45x series
32-bit ARM®Cortex®-M4 microcontroller
User manual V3.0

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Contents
Abbreviations in the text ...............................................................................................................................................36
List of abbreviations for registers.............................................................................................................................36
Available peripherals ................................................................................................................................................36
Interrupts and events.....................................................................................................................................................37
Nested vectored interrupt controller .........................................................................................................................37
2.1.1 SysTick calibration value register......................................................................................................................37
2.1.2 Interrupt and exception vectors .........................................................................................................................37
External interrupt/event controller (EXTI)............................................................................................................... 40
2.2.1 Introduction .......................................................................................................................................................40
2.2.2 Main features.....................................................................................................................................................40
2.2.3 Functional description .......................................................................................................................................41
2.2.4 EXTI line mapping............................................................................................................................................42
EXTI registers ..........................................................................................................................................................44
2.3.1 EXTI register review .........................................................................................................................................44
2.3.2 EXTI interrupt mask register (EXTI_IMASK) .................................................................................................44
2.3.3 EXTI event mask register (EXTI_EMASK) ..................................................................................................... 45
2.3.4 Rising trigger selection register (EXTI_RT_CFG)............................................................................................45
2.3.5 Falling trigger selection register (EXTI_FT_CFG)...........................................................................................45
2.3.6 EXTI software interrupt event register (EXTI_SWIE)......................................................................................46
2.3.7 EXTI pending register (EXTI_PEND)..............................................................................................................46
2.3.8 EXTI timestamp trigger source selection register (EXTI_TS_SEL).................................................................47
Memory and bus architecture.......................................................................................................................................48
System architecture................................................................................................................................................... 48
3.1.1 Bus architecture.................................................................................................................................................48
3.1.2 Bus address mapping.........................................................................................................................................49
3.1.3 Boot management..............................................................................................................................................51
Memory system ........................................................................................................................................................52
3.2.1 FLASH specification.........................................................................................................................................52
3.2.2 iCache................................................................................................................................................................64
3.2.3 SRAM................................................................................................................................................................65
3.2.4 R-SRAM（Retention SRAM）........................................................................................................................66
3.2.5 FLASH register .................................................................................................................................................67
Power control (PWR) ....................................................................................................................................................76
General description...................................................................................................................................................76
4.1.1 Power supply.....................................................................................................................................................76
4.1.2 Power supply supervisor....................................................................................................................................78
Power modes ............................................................................................................................................................ 80
4.2.1 SLEEP mode .....................................................................................................................................................84

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4.2.2 STOP0 mode .....................................................................................................................................................85
4.2.3 STOP2 mode .....................................................................................................................................................86
4.2.4 STANDBY mode...............................................................................................................................................87
4.2.5 VBAT mode.......................................................................................................................................................87
Low-power auto-wakeup（AWU）mode................................................................................................................88
PWR registers...........................................................................................................................................................88
4.4.1 PWR register overview......................................................................................................................................88
4.4.2 Power control register (PWR_CTRL) ...............................................................................................................89
4.4.3 Power control status register(PWR_CTRLSTS) ............................................................................................... 90
4.4.4 Power control register 2 (PWR_CTRL2) ..........................................................................................................91
4.4.5 Power control register 3 (PWR_CTRL3) ..........................................................................................................92
Backup registers (BKP).................................................................................................................................................94
Introduction ..............................................................................................................................................................94
Main features............................................................................................................................................................94
Function description ................................................................................................................................................. 94
BKP registers............................................................................................................................................................ 95
5.4.1 BKP register overview....................................................................................................................................... 95
5.4.2 Backup Data Register x (BKP_DATx) (x = 1 … 42) ........................................................................................ 97
5.4.3 Backup Control Register (BKP_CTRL)............................................................................................................97
5.4.4 Backup Control/Status Register (BKP_CTRLSTS) .......................................................................................... 98
Reset and clock control (RCC) ...................................................................................................................................100
Reset Control Unit.................................................................................................................................................. 100
6.1.1 Power reset ...................................................................................................................................................... 100
6.1.2 System reset.....................................................................................................................................................100
6.1.3 Backup domain reset .......................................................................................................................................101
Clock control unit...................................................................................................................................................102
6.2.1 Clock Tree Diagram ........................................................................................................................................103
6.2.2 HSE clock........................................................................................................................................................103
6.2.3 HSI clock.........................................................................................................................................................104
6.2.4 PLL clock ........................................................................................................................................................ 105
6.2.5 LSE clock ........................................................................................................................................................105
6.2.6 LSI clock .........................................................................................................................................................105
6.2.7 System clock (SYSCLK) selection.................................................................................................................. 106
6.2.8 Clock security system (CLKSS)......................................................................................................................106
6.2.9 RTC clock........................................................................................................................................................ 107
6.2.10 Watchdog clock .............................................................................................................................................107
6.2.11 Clock output(MCO)....................................................................................................................................... 107
RCC Registers ........................................................................................................................................................ 107
6.3.1 RCC register overview .................................................................................................................................... 108
6.3.2 Clock Control Register (RCC_CTRL) ............................................................................................................109
6.3.3 Clock Configuration Register (RCC_CFG)..................................................................................................... 110
6.3.4 Clock Interrupt Register (RCC_CLKINT) ...................................................................................................... 114

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6.3.5 APB2 Peripheral Reset Register (RCC_APB2PRST) ..................................................................................... 116
6.3.6 APB1 Peripheral Reset Register (RCC_APB1PRST) ..................................................................................... 118
6.3.7 AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN) .....................................................................120
6.3.8 APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)...................................................................122
6.3.9 APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)...................................................................124
6.3.10 Backup Domain Control Register (RCC_BDCTRL) ....................................................................................127
6.3.11 Clock Control/Status Register (RCC_CTRLSTS)......................................................................................... 128
6.3.12 AHB Peripheral Reset Register (RCC_AHBPRST)......................................................................................130
6.3.13 Clock Configuration Register 2 (RCC_CFG2).............................................................................................. 131
6.3.14 Clock Configuration Register 3 (RCC_CFG3)..............................................................................................133
GPIO andAFIO...........................................................................................................................................................135
Summary.................................................................................................................................................................135
I/O function description.......................................................................................................................................... 136
7.2.1 I/O mode configuration ...................................................................................................................................136
7.2.2 Status after reset ..............................................................................................................................................141
7.2.3 Individual bit setting and bit clearing..............................................................................................................142
7.2.4 External interrupt/wake-up line.......................................................................................................................142
7.2.5 Alternate function............................................................................................................................................142
7.2.6 I/O configuration of peripherals ...................................................................................................................... 154
7.2.7 GPIO locking mechanism................................................................................................................................ 158
GPIO registers ........................................................................................................................................................ 159
7.3.1 GPIO register overview...................................................................................................................................159
7.3.2 GPIO port low configuration register (GPIOx_PL_CFG)...............................................................................160
7.3.3 GPIO port high configuration register (GPIOx_PH_CFG) .............................................................................161
7.3.4 GPIO port input data register (GPIOx_PID) ...................................................................................................162
7.3.5 GPIO port output data register (GPIOx_POD)................................................................................................ 162
7.3.6 GPIO port bit setting/clearing register (GPIOx_PBSC) ..................................................................................163
7.3.7 GPIO port bit clear register (GPIOx_PBC).....................................................................................................163
7.3.8 GPIO port lock configuration register (GPIOx_PLOCK_CFG ) .................................................................... 164
7.3.9 GPIO driver capability configuration register (GPIOx_DS_CFG ).................................................................165
7.3.10 GPIO flip rate configuration register (GPIOx_SR_CFG) .............................................................................165
AFIO registers ........................................................................................................................................................ 166
7.4.1 AFIO register overview...................................................................................................................................166
7.4.2 AFIO event control register (AFIO_ECTRL).................................................................................................. 167
7.4.3 AFIO alternate remap configuration register (AFIO_RMP_CFG )................................................................. 167
7.4.4 AFIO external interrupt configuration register 1(AFIO_EXTI_CFG1)...........................................................171
7.4.5 AFIO external interrupt configuration register 2(AFIO_EXTI_CFG2)...........................................................172
7.4.6 AFIO external interrupt configuration register 3(AFIO_EXTI_CFG3)...........................................................172
7.4.7 AFIO external interrupt configuration register 4(AFIO_EXTI_CFG4)...........................................................173
7.4.8 AFIO alternate remapping configuration register 3(AFIO_RMP_CFG3).......................................................174
7.4.9 AFIO alternate remap configuration register 4 (AFIO_ RMP_CFG4 )...........................................................177
7.4.10 AFIO alternate remapping configuration register 5(AFIO_RMP_CFG5).....................................................180

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DMA controller............................................................................................................................................................183
Introduction ............................................................................................................................................................183
Main features..........................................................................................................................................................183
Block diagram ........................................................................................................................................................ 184
Function description ............................................................................................................................................... 184
8.4.1 DMA operation................................................................................................................................................184
8.4.2 Channel priority and arbitration ...................................................................................................................... 185
8.4.3 DMA channels and number of transfers .......................................................................................................... 185
8.4.4 Programmable data bit width...........................................................................................................................185
8.4.5 Peripheral/Memory address incrementation ....................................................................................................187
8.4.6 Channel configuration procedure ....................................................................................................................187
8.4.7 Flow control ....................................................................................................................................................188
8.4.8 Circular mode..................................................................................................................................................188
8.4.9 Error management ........................................................................................................................................... 189
8.4.10 Interrupt......................................................................................................................................................... 189
8.4.11 DMA request mapping................................................................................................................................... 189
DMAregisters ........................................................................................................................................................ 193
8.5.1 DMA register overview ...................................................................................................................................193
8.5.2 DMA interrupt status register (DMA_INTSTS).............................................................................................. 195
8.5.3 DMA interrupt flag clear register (DMA_INTCLR) .......................................................................................195
8.5.4 DMA channel x configuration register (DMA_CHCFGx) ..............................................................................196
8.5.5 DMA channel x transfer number register (DMA_TXNUMx).........................................................................198
8.5.6 DMA channel x peripheral address register (DMA_PADDRx)....................................................................... 198
8.5.7 DMA channel x memory address register (DMA_MADDRx)........................................................................ 199
8.5.8 DMA1 channel x channel request select register (DMA1_CHSELx) ............................................................. 199
8.5.9 DMA2 channel x channel request select register (DMA2_CHSELx) ............................................................. 201
8.5.10 DMA channel MAP enable register (DMA_CHMAPEN) ............................................................................ 202
Analog to digital conversion (ADC) ...............................................................................................................................204
Introduction ............................................................................................................................................................204
Main features ............................................................................................................................................................204
Function Description .................................................................................................................................................205
9.3.1 ADC clock ........................................................................................................................................................ 206
9.3.2 ADC switch control ...........................................................................................................................................207
9.3.3 Channel selection ..............................................................................................................................................207
9.3.4 Internal channel............................................................................................................................................... 211
9.3.5 Single conversion mode ..................................................................................................................................... 211
9.3.6 Continuous conversion mode ............................................................................................................................ 211
9.3.7 Timing diagram .................................................................................................................................................212
9.3.8 Analog watchdog ...............................................................................................................................................212
9.3.9 Scanning mode ..................................................................................................................................................213
9.3.10 Injection channel management .........................................................................................................................213
9.3.11 Discontinuous mode ........................................................................................................................................214

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Calibration..............................................................................................................................................................215
Data aligned .............................................................................................................................................................215
Programmable channel sampling time .......................................................................................................................216
Externally triggered conversion ................................................................................................................................. 216
DMA requests......................................................................................................................................................... 218
ADC Mode..............................................................................................................................................................218
9.9.1 Independent mode ........................................................................................................................................... 219
9.9.2 Synchronous regular mode..............................................................................................................................219
9.9.3 Synchronous injection mode ...........................................................................................................................220
9.9.4 Fast alternate mode..........................................................................................................................................221
9.9.5 Slow alternate mode ........................................................................................................................................ 222
9.9.6 Rotation trigger Mode .....................................................................................................................................223
9.9.7 Mixed synchronous regular mode + synchronous injection mode .................................................................. 224
9.9.8 Mixed synchronous regular mode + rotation trigger mode ............................................................................. 224
9.9.9 Mixed synchronous injection mode + alternate mode..................................................................................... 225
Temperature sensor ................................................................................................................................................. 226
9.10.1 Temperature sensor using flow......................................................................................................................227
ADC interrupt ....................................................................................................................................................... 227
ADC registers........................................................................................................................................................228
9.12.1 ADC register overview ...................................................................................................................................228
9.12.2 ADC status register (ADC_STS) ......................................................................................................................229
9.12.3 ADC control register 1 (ADC_CTRL1) ........................................................................................................230
9.12.4 ADC control register 2 (ADC_CTRL2) ........................................................................................................ 233
9.12.5 ADC sampling time register 1 (ADC_SAMPT1)..........................................................................................235
9.12.6 ADC sampling time register 2 (ADC_ SAMPT2).........................................................................................235
9.12.7 ADC injected channel data offset register x (ADC_JOFFSETx) (x=1…4)................................................... 236
9.12.8 ADC watchdog high threshold register (ADC_WDGHIGH) .............................................................................236
9.12.9 ADC watchdog low threshold register (ADC_WDGLOW) ...............................................................................237
9.12.10 ADC regular sequence register 1 (ADC_RSEQ1).......................................................................................237
9.12.11ADC regular sequence register 2 (ADC_RSEQ2) ....................................................................................... 238
9.12.12 ADC regular sequence register 3 (ADC_RSEQ3).......................................................................................238
9.12.13 ADC Injection sequence register (ADC_JSEQ) ............................................................................................... 239
9.12.14 ADC injection data register x (ADC_JDATx) (x= 1…4) ............................................................................240
9.12.15 ADC regulars data register (ADC_DAT) ........................................................................................................ 240
9.12.16 ADC differential mode selection register (ADC_DIFSEL)......................................................................... 240
9.12.17 ADC calibration factor (ADC_CALFACT).................................................................................................241
9.12.18 ADC control register 3 (ADC_CTRL3) ......................................................................................................242
9.12.19 ADC sampling time register 3 (ADC_SAMPT3)........................................................................................243
Digital to analog conversion (DAC)..........................................................................................................................244
Introduction .......................................................................................................................................................... 244
Main features........................................................................................................................................................244
DAC function description and operation description ...........................................................................................246
10.3.1 DAC enable ...................................................................................................................................................246

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10.3.2 DAC output buffer.........................................................................................................................................246
10.3.3 DAC data format ...........................................................................................................................................246
10.3.4 DAC trigger...................................................................................................................................................248
10.3.5 DAC conversion............................................................................................................................................249
10.3.6 DAC output voltage....................................................................................................................................... 249
10.3.7 DMA requests................................................................................................................................................250
10.3.8 The noise ....................................................................................................................................................... 250
10.3.9 Triangular wave generation ........................................................................................................................... 251
DAC dual-channel conversion.............................................................................................................................. 252
10.4.1 Independent trigger without waveform generator..........................................................................................252
10.4.2 Independent triggers producing the same noise.............................................................................................252
10.4.3 Independent triggers that generate different noises .......................................................................................253
10.4.4 Independent triggers that generate the same triangle wave ...........................................................................253
10.4.5 Independent trigger to generate different triangle waves...............................................................................254
10.4.6 Simultaneous software startup....................................................................................................................... 254
10.4.7 Synchronous trigger without waveform generator ........................................................................................255
10.4.8 Synchronous triggers that generate the same noise ....................................................................................... 255
10.4.9 Synchronous triggers that generate different noises ......................................................................................255
10.4.10 Synchronous trigger to generate the same triangle wave.............................................................................256
10.4.11 Synchronous trigger to generate different triangle waves............................................................................256
DAC register.........................................................................................................................................................257
10.5.1 DAC registers overview ................................................................................................................................ 257
10.5.2 DAC control register (DAC_CTRL) ............................................................................................................. 257
10.5.3 DAC software trigger register (DAC_SOTTR)............................................................................................. 260
10.5.4 12 bit right aligned data hold register for DAC1 (DAC_DR12CH1) ............................................................ 260
10.5.5 12 bit left aligned data hold register for DAC1 (DAC_DL12CH1) ..............................................................261
10.5.6 8-bit right-aligned data hold register for DAC1 (DAC_DR8CH1) ............................................................... 261
10.5.7 12 bit right aligned data hold register for DAC2 (DAC_DR12CH2)............................................................ 262
10.5.8 12 bit left aligned data hold register for DAC2 (DAC_DL12CH2) .............................................................. 262
10.5.9 8-bit right-aligned data hold register for DAC2 (DAC_DR8CH2) ............................................................... 262
10.5.10 12 bit right aligned data hold register for dual DAC (DAC_DR12DCH) ................................................... 263
10.5.11 12 bit left aligned data hold register for dual DAC (DAC_DL12DCH)......................................................263
10.5.12 8 bit right aligned data hold register for dual DAC (DAC_DR8DCH) ....................................................... 264
10.5.13 DAC1 data output register (DAC_DATO1) ................................................................................................264
10.5.14 DAC2 data output register (DAC_DATO2) ................................................................................................265
Advanced-control timers (TIM1 and TIM8) ................................................................................................................266
TIM1 and TIM8 introduction ..................................................................................................................................266
Main features of TIM1 and TIM8 ............................................................................................................................ 266
TIM1 and TIM8 function description ....................................................................................................................... 267
11.3.1 Time-base unit ................................................................................................................................................. 267
11.3.2 Counter mode ..................................................................................................................................................268
11.3.3 Repetition counter ............................................................................................................................................273
11.3.4 Clock selection ................................................................................................................................................276

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11.3.5 Capture/compare channels ...............................................................................................................................279
11.3.6 Input capture mode ..........................................................................................................................................282
11.3.7 PWM input mode ............................................................................................................................................. 283
11.3.8 Forced output mode ......................................................................................................................................... 284
11.3.9 Output compare mode ......................................................................................................................................285
11.3.10 PWM mode ................................................................................................................................................... 286
11.3.11 One-pulse mode .............................................................................................................................................289
11.3.12 Clearing the OCxREF signal on an external event ...........................................................................................290
11.3.13 Complementary outputs with dead-time insertion ............................................................................................291
11.3.14 Break function ............................................................................................................................................... 293
11.3.15 Debug mode .................................................................................................................................................. 295
11.3.16 TIMx and external trigger synchronization ......................................................................................................295
11.3.17 Timer synchronization .................................................................................................................................... 298
11.3.18 6-step PWM generation .................................................................................................................................. 298
11.3.19 Encoder interface mode ..................................................................................................................................299
11.3.20 Interfacing with Hall sensor ............................................................................................................................302
TIMx register (x=1, 8) ............................................................................................................................................ 304
11.4.1 Register Overview ........................................................................................................................................... 304
11.4.2 Control register 1 (TIMx_CTRL1) ................................................................................................................... 305
11.4.3 Control register 2 (TIMx_CTRL2) ................................................................................................................... 308
11.4.4 Slave mode control register (TIMx_SMCTRL) .................................................................................................309
11.4.5 DMA/Interrupt enable registers (TIMx_DINTEN) ............................................................................................312
11.4.6 Status registers (TIMx_STS) ............................................................................................................................313
11.4.7 Event generation registers (TIMx_EVTGEN) ...................................................................................................315
11.4.8 Capture/compare mode register 1 (TIMx_CCMOD1) .......................................................................................316
11.4.9 Capture/compare mode register 2 (TIMx_CCMOD2) .......................................................................................320
11.4.10 Capture/compare enable registers (TIMx_CCEN) ...........................................................................................321
11.4.11 Counters (TIMx_CNT) ................................................................................................................................... 324
11.4.12 Prescaler (TIMx_PSC) ................................................................................................................................... 324
11.4.13 Auto-reload register (TIMx_AR) ....................................................................................................................324
11.4.14 Repeat count registers (TIMx_REPCNT) ........................................................................................................325
11.4.15 Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 325
11.4.16 Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 326
11.4.17 Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 326
11.4.18 Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 327
11.4.19 Break and Dead-time registers (TIMx_BKDT) ...............................................................................................327
11.4.20 DMA Control register (TIMx_DCTRL) .......................................................................................................... 329
11.4.21 DMA transfer buffer register (TIMx_DADDR) ..............................................................................................330
11.4.22 Capture/compare mode registers 3(TIMx_CCMOD3) ..................................................................................... 331
11.4.23 Capture/compare register 5 (TIMx_CCDAT5) ................................................................................................ 331
11.4.24 Capture/compare register 6 (TIMx_CCDAT6) ................................................................................................332
General-purpose timers (TIM2, TIM3, TIM4 and TIM5) ..........................................................................................333
General-purpose timers introduction ........................................................................................................................ 333

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Main features of General-purpose timers .................................................................................................................333
General-purpose timers description .........................................................................................................................334
12.3.1 Time-base unit ................................................................................................................................................. 334
12.3.2 Counter mode ..................................................................................................................................................335
12.3.3 Clock selection ................................................................................................................................................340
12.3.4 Capture/compare channels ............................................................................................................................... 344
12.3.5 Input capture mode ..........................................................................................................................................347
12.3.6 PWM input mode ............................................................................................................................................348
12.3.7 Forced output mode ......................................................................................................................................... 349
12.3.8 Output compare mode ......................................................................................................................................349
12.3.9 PWM mode ..................................................................................................................................................... 351
12.3.10 One-pulse mode .............................................................................................................................................354
12.3.11 Clearing the OCxREF signal on an external event ...........................................................................................355
12.3.12 Debug mode .................................................................................................................................................. 356
12.3.13 TIMx and external trigger synchronization .....................................................................................................356
12.3.14 Timer synchronization ....................................................................................................................................356
12.3.15 Encoder interface mode .................................................................................................................................. 361
12.3.16 Interfacing with Hall sensor ...........................................................................................................................363
TIMx register description(x=2, 3 ,4 and 5) ............................................................................................................... 363
12.4.1 Register Overview ........................................................................................................................................... 363
12.4.2 Control register 1 (TIMx_CTRL1) ................................................................................................................... 365
12.4.3 Control register 2 (TIMx_CTRL2) ................................................................................................................... 367
12.4.4 Slave mode control register (TIMx_SMCTRL) .................................................................................................368
12.4.5 DMA/Interrupt enable registers (TIMx_DINTEN) ...........................................................................................371
12.4.6 Status registers (TIMx_STS) ............................................................................................................................372
12.4.7 Event generation registers (TIMx_EVTGEN) ...................................................................................................373
12.4.8 Capture/compare mode register 1 (TIMx_CCMOD1) .......................................................................................374
12.4.9 Capture/compare mode register 2 (TIMx_CCMOD2) .......................................................................................377
12.4.10 Capture/compare enable registers (TIMx_CCEN) ...........................................................................................379
12.4.11 Counters (TIMx_CNT) ..................................................................................................................................380
12.4.12 Prescaler (TIMx_PSC) ................................................................................................................................... 381
12.4.13 Auto-reload register (TIMx_AR) ....................................................................................................................381
12.4.14 Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 381
12.4.15 Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 382
12.4.16 Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 382
12.4.17 Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 383
12.4.18 DMA Control register (TIMx_DCTRL) .......................................................................................................... 383
12.4.19 DMA transfer buffer register (TIMx_DADDR)...........................................................................................384
Basic timers (TIM6 and TIM7) ...................................................................................................................................386
Introduction ............................................................................................................................................................ 386
Main features .......................................................................................................................................................... 386
Basic timers description ..........................................................................................................................................387
13.3.1 Time-base unit ................................................................................................................................................. 387

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13.3.2 Counter mode ..................................................................................................................................................388
13.3.3 Clock selection ................................................................................................................................................ 391
13.3.4 Debug mode .................................................................................................................................................... 391
TIMx register description(x = 6 and 7) ....................................................................................................................391
13.4.1 Register overview..........................................................................................................................................392
13.4.2 Control Register 1 (TIMx_CTRL1)............................................................................................................... 392
13.4.3 Control Register 2 (TIMx_CTRL2)............................................................................................................... 393
13.4.4 DMA/Interrupt Enable Registers (TIMx_DINTEN) .....................................................................................394
13.4.5 Status Registers (TIMx_STS)........................................................................................................................395
13.4.6 Event Generation registers (TIMx_EVTGEN).............................................................................................. 395
13.4.7 Counter (TIMx_CNT) ................................................................................................................................... 396
13.4.8 Prescaler (TIMx_PSC) .................................................................................................................................. 396
13.4.9 Automatic reload register (TIMx_AR) ..........................................................................................................396
Real-time clock (RTC)...............................................................................................................................................398
Description ...........................................................................................................................................................398
14.1.1 Specification..................................................................................................................................................398
RTC function description...................................................................................................................................... 399
14.2.1 RTC block diagram........................................................................................................................................ 399
14.2.2 GPIOs of RTC ............................................................................................................................................... 400
14.2.3 RTC register write protection ........................................................................................................................ 400
14.2.4 RTC clock and prescaler................................................................................................................................400
14.2.5 RTC calendar.................................................................................................................................................401
14.2.6 Calendar initialization and configuration ...................................................................................................... 401
14.2.7 Calendar reading............................................................................................................................................401
14.2.8 Calibration clock output ................................................................................................................................402
14.2.9 Programmable alarms....................................................................................................................................403
14.2.10 Alarm configuration.....................................................................................................................................403
14.2.11 Alarm output................................................................................................................................................ 403
14.2.12 Periodic automatic wakeup..........................................................................................................................403
14.2.13 Wakeup timer configuration ........................................................................................................................404
14.2.14 Timestamp function.....................................................................................................................................404
14.2.15 Daylight saving time configuration ............................................................................................................. 404
14.2.16 RTC sub-second register shift......................................................................................................................405
14.2.17 RTC digital clock precision calibration .......................................................................................................405
14.2.18 RTC low power mode.................................................................................................................................. 406
RTC Registers....................................................................................................................................................... 407
14.3.1 RTC Register overview .................................................................................................................................407
14.3.2 RTC Calendar Time Register (RTC_TSH)....................................................................................................408
14.3.3 RTC Calendar Date Register (RTC_DATE)..................................................................................................408
14.3.4 RTC Control Register (RTC_CTRL)............................................................................................................. 409
14.3.5 RTC Initial Status Register (RTC_INITSTS)................................................................................................ 411
14.3.6 RTC Prescaler Register (RTC_PRE) .............................................................................................................413
14.3.7 RTC Wakeup Timer Register (RTC_WKUPT).............................................................................................. 413