Nations N32G45 Series User manual

N32G45x series
32-bit ARM®Cortex®-M4 microcontroller
User manual V3.0

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Contents
Abbreviations in the text ...............................................................................................................................................36
List of abbreviations for registers.............................................................................................................................36
Available peripherals ................................................................................................................................................36
Interrupts and events.....................................................................................................................................................37
Nested vectored interrupt controller .........................................................................................................................37
2.1.1 SysTick calibration value register......................................................................................................................37
2.1.2 Interrupt and exception vectors .........................................................................................................................37
External interrupt/event controller (EXTI)............................................................................................................... 40
2.2.1 Introduction .......................................................................................................................................................40
2.2.2 Main features.....................................................................................................................................................40
2.2.3 Functional description .......................................................................................................................................41
2.2.4 EXTI line mapping............................................................................................................................................42
EXTI registers ..........................................................................................................................................................44
2.3.1 EXTI register review .........................................................................................................................................44
2.3.2 EXTI interrupt mask register (EXTI_IMASK) .................................................................................................44
2.3.3 EXTI event mask register (EXTI_EMASK) ..................................................................................................... 45
2.3.4 Rising trigger selection register (EXTI_RT_CFG)............................................................................................45
2.3.5 Falling trigger selection register (EXTI_FT_CFG)...........................................................................................45
2.3.6 EXTI software interrupt event register (EXTI_SWIE)......................................................................................46
2.3.7 EXTI pending register (EXTI_PEND)..............................................................................................................46
2.3.8 EXTI timestamp trigger source selection register (EXTI_TS_SEL).................................................................47
Memory and bus architecture.......................................................................................................................................48
System architecture................................................................................................................................................... 48
3.1.1 Bus architecture.................................................................................................................................................48
3.1.2 Bus address mapping.........................................................................................................................................49
3.1.3 Boot management..............................................................................................................................................51
Memory system ........................................................................................................................................................52
3.2.1 FLASH specification.........................................................................................................................................52
3.2.2 iCache................................................................................................................................................................64
3.2.3 SRAM................................................................................................................................................................65
3.2.4 R-SRAM（Retention SRAM）........................................................................................................................66
3.2.5 FLASH register .................................................................................................................................................67
Power control (PWR) ....................................................................................................................................................76
General description...................................................................................................................................................76
4.1.1 Power supply.....................................................................................................................................................76
4.1.2 Power supply supervisor....................................................................................................................................78
Power modes ............................................................................................................................................................ 80
4.2.1 SLEEP mode .....................................................................................................................................................84

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4.2.2 STOP0 mode .....................................................................................................................................................85
4.2.3 STOP2 mode .....................................................................................................................................................86
4.2.4 STANDBY mode...............................................................................................................................................87
4.2.5 VBAT mode.......................................................................................................................................................87
Low-power auto-wakeup（AWU）mode................................................................................................................88
PWR registers...........................................................................................................................................................88
4.4.1 PWR register overview......................................................................................................................................88
4.4.2 Power control register (PWR_CTRL) ...............................................................................................................89
4.4.3 Power control status register(PWR_CTRLSTS) ............................................................................................... 90
4.4.4 Power control register 2 (PWR_CTRL2) ..........................................................................................................91
4.4.5 Power control register 3 (PWR_CTRL3) ..........................................................................................................92
Backup registers (BKP).................................................................................................................................................94
Introduction ..............................................................................................................................................................94
Main features............................................................................................................................................................94
Function description ................................................................................................................................................. 94
BKP registers............................................................................................................................................................ 95
5.4.1 BKP register overview....................................................................................................................................... 95
5.4.2 Backup Data Register x (BKP_DATx) (x = 1 … 42) ........................................................................................ 97
5.4.3 Backup Control Register (BKP_CTRL)............................................................................................................97
5.4.4 Backup Control/Status Register (BKP_CTRLSTS) .......................................................................................... 98
Reset and clock control (RCC) ...................................................................................................................................100
Reset Control Unit.................................................................................................................................................. 100
6.1.1 Power reset ...................................................................................................................................................... 100
6.1.2 System reset.....................................................................................................................................................100
6.1.3 Backup domain reset .......................................................................................................................................101
Clock control unit...................................................................................................................................................102
6.2.1 Clock Tree Diagram ........................................................................................................................................103
6.2.2 HSE clock........................................................................................................................................................103
6.2.3 HSI clock.........................................................................................................................................................104
6.2.4 PLL clock ........................................................................................................................................................ 105
6.2.5 LSE clock ........................................................................................................................................................105
6.2.6 LSI clock .........................................................................................................................................................105
6.2.7 System clock (SYSCLK) selection.................................................................................................................. 106
6.2.8 Clock security system (CLKSS)......................................................................................................................106
6.2.9 RTC clock........................................................................................................................................................ 107
6.2.10 Watchdog clock .............................................................................................................................................107
6.2.11 Clock output(MCO)....................................................................................................................................... 107
RCC Registers ........................................................................................................................................................ 107
6.3.1 RCC register overview .................................................................................................................................... 108
6.3.2 Clock Control Register (RCC_CTRL) ............................................................................................................109
6.3.3 Clock Configuration Register (RCC_CFG)..................................................................................................... 110
6.3.4 Clock Interrupt Register (RCC_CLKINT) ...................................................................................................... 114

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6.3.5 APB2 Peripheral Reset Register (RCC_APB2PRST) ..................................................................................... 116
6.3.6 APB1 Peripheral Reset Register (RCC_APB1PRST) ..................................................................................... 118
6.3.7 AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN) .....................................................................120
6.3.8 APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)...................................................................122
6.3.9 APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)...................................................................124
6.3.10 Backup Domain Control Register (RCC_BDCTRL) ....................................................................................127
6.3.11 Clock Control/Status Register (RCC_CTRLSTS)......................................................................................... 128
6.3.12 AHB Peripheral Reset Register (RCC_AHBPRST)......................................................................................130
6.3.13 Clock Configuration Register 2 (RCC_CFG2).............................................................................................. 131
6.3.14 Clock Configuration Register 3 (RCC_CFG3)..............................................................................................133
GPIO andAFIO...........................................................................................................................................................135
Summary.................................................................................................................................................................135
I/O function description.......................................................................................................................................... 136
7.2.1 I/O mode configuration ...................................................................................................................................136
7.2.2 Status after reset ..............................................................................................................................................141
7.2.3 Individual bit setting and bit clearing..............................................................................................................142
7.2.4 External interrupt/wake-up line.......................................................................................................................142
7.2.5 Alternate function............................................................................................................................................142
7.2.6 I/O configuration of peripherals ...................................................................................................................... 154
7.2.7 GPIO locking mechanism................................................................................................................................ 158
GPIO registers ........................................................................................................................................................ 159
7.3.1 GPIO register overview...................................................................................................................................159
7.3.2 GPIO port low configuration register (GPIOx_PL_CFG)...............................................................................160
7.3.3 GPIO port high configuration register (GPIOx_PH_CFG) .............................................................................161
7.3.4 GPIO port input data register (GPIOx_PID) ...................................................................................................162
7.3.5 GPIO port output data register (GPIOx_POD)................................................................................................ 162
7.3.6 GPIO port bit setting/clearing register (GPIOx_PBSC) ..................................................................................163
7.3.7 GPIO port bit clear register (GPIOx_PBC).....................................................................................................163
7.3.8 GPIO port lock configuration register (GPIOx_PLOCK_CFG ) .................................................................... 164
7.3.9 GPIO driver capability configuration register (GPIOx_DS_CFG ).................................................................165
7.3.10 GPIO flip rate configuration register (GPIOx_SR_CFG) .............................................................................165
AFIO registers ........................................................................................................................................................ 166
7.4.1 AFIO register overview...................................................................................................................................166
7.4.2 AFIO event control register (AFIO_ECTRL).................................................................................................. 167
7.4.3 AFIO alternate remap configuration register (AFIO_RMP_CFG )................................................................. 167
7.4.4 AFIO external interrupt configuration register 1(AFIO_EXTI_CFG1)...........................................................171
7.4.5 AFIO external interrupt configuration register 2(AFIO_EXTI_CFG2)...........................................................172
7.4.6 AFIO external interrupt configuration register 3(AFIO_EXTI_CFG3)...........................................................172
7.4.7 AFIO external interrupt configuration register 4(AFIO_EXTI_CFG4)...........................................................173
7.4.8 AFIO alternate remapping configuration register 3(AFIO_RMP_CFG3).......................................................174
7.4.9 AFIO alternate remap configuration register 4 (AFIO_ RMP_CFG4 )...........................................................177
7.4.10 AFIO alternate remapping configuration register 5(AFIO_RMP_CFG5).....................................................180

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DMA controller............................................................................................................................................................183
Introduction ............................................................................................................................................................183
Main features..........................................................................................................................................................183
Block diagram ........................................................................................................................................................ 184
Function description ............................................................................................................................................... 184
8.4.1 DMA operation................................................................................................................................................184
8.4.2 Channel priority and arbitration ...................................................................................................................... 185
8.4.3 DMA channels and number of transfers .......................................................................................................... 185
8.4.4 Programmable data bit width...........................................................................................................................185
8.4.5 Peripheral/Memory address incrementation ....................................................................................................187
8.4.6 Channel configuration procedure ....................................................................................................................187
8.4.7 Flow control ....................................................................................................................................................188
8.4.8 Circular mode..................................................................................................................................................188
8.4.9 Error management ........................................................................................................................................... 189
8.4.10 Interrupt......................................................................................................................................................... 189
8.4.11 DMA request mapping................................................................................................................................... 189
DMAregisters ........................................................................................................................................................ 193
8.5.1 DMA register overview ...................................................................................................................................193
8.5.2 DMA interrupt status register (DMA_INTSTS).............................................................................................. 195
8.5.3 DMA interrupt flag clear register (DMA_INTCLR) .......................................................................................195
8.5.4 DMA channel x configuration register (DMA_CHCFGx) ..............................................................................196
8.5.5 DMA channel x transfer number register (DMA_TXNUMx).........................................................................198
8.5.6 DMA channel x peripheral address register (DMA_PADDRx)....................................................................... 198
8.5.7 DMA channel x memory address register (DMA_MADDRx)........................................................................ 199
8.5.8 DMA1 channel x channel request select register (DMA1_CHSELx) ............................................................. 199
8.5.9 DMA2 channel x channel request select register (DMA2_CHSELx) ............................................................. 201
8.5.10 DMA channel MAP enable register (DMA_CHMAPEN) ............................................................................ 202
Analog to digital conversion (ADC) ...............................................................................................................................204
Introduction ............................................................................................................................................................204
Main features ............................................................................................................................................................204
Function Description .................................................................................................................................................205
9.3.1 ADC clock ........................................................................................................................................................ 206
9.3.2 ADC switch control ...........................................................................................................................................207
9.3.3 Channel selection ..............................................................................................................................................207
9.3.4 Internal channel............................................................................................................................................... 211
9.3.5 Single conversion mode ..................................................................................................................................... 211
9.3.6 Continuous conversion mode ............................................................................................................................ 211
9.3.7 Timing diagram .................................................................................................................................................212
9.3.8 Analog watchdog ...............................................................................................................................................212
9.3.9 Scanning mode ..................................................................................................................................................213
9.3.10 Injection channel management .........................................................................................................................213
9.3.11 Discontinuous mode ........................................................................................................................................214

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Calibration..............................................................................................................................................................215
Data aligned .............................................................................................................................................................215
Programmable channel sampling time .......................................................................................................................216
Externally triggered conversion ................................................................................................................................. 216
DMA requests......................................................................................................................................................... 218
ADC Mode..............................................................................................................................................................218
9.9.1 Independent mode ........................................................................................................................................... 219
9.9.2 Synchronous regular mode..............................................................................................................................219
9.9.3 Synchronous injection mode ...........................................................................................................................220
9.9.4 Fast alternate mode..........................................................................................................................................221
9.9.5 Slow alternate mode ........................................................................................................................................ 222
9.9.6 Rotation trigger Mode .....................................................................................................................................223
9.9.7 Mixed synchronous regular mode + synchronous injection mode .................................................................. 224
9.9.8 Mixed synchronous regular mode + rotation trigger mode ............................................................................. 224
9.9.9 Mixed synchronous injection mode + alternate mode..................................................................................... 225
Temperature sensor ................................................................................................................................................. 226
9.10.1 Temperature sensor using flow......................................................................................................................227
ADC interrupt ....................................................................................................................................................... 227
ADC registers........................................................................................................................................................228
9.12.1 ADC register overview ...................................................................................................................................228
9.12.2 ADC status register (ADC_STS) ......................................................................................................................229
9.12.3 ADC control register 1 (ADC_CTRL1) ........................................................................................................230
9.12.4 ADC control register 2 (ADC_CTRL2) ........................................................................................................ 233
9.12.5 ADC sampling time register 1 (ADC_SAMPT1)..........................................................................................235
9.12.6 ADC sampling time register 2 (ADC_ SAMPT2).........................................................................................235
9.12.7 ADC injected channel data offset register x (ADC_JOFFSETx) (x=1…4)................................................... 236
9.12.8 ADC watchdog high threshold register (ADC_WDGHIGH) .............................................................................236
9.12.9 ADC watchdog low threshold register (ADC_WDGLOW) ...............................................................................237
9.12.10 ADC regular sequence register 1 (ADC_RSEQ1).......................................................................................237
9.12.11ADC regular sequence register 2 (ADC_RSEQ2) ....................................................................................... 238
9.12.12 ADC regular sequence register 3 (ADC_RSEQ3).......................................................................................238
9.12.13 ADC Injection sequence register (ADC_JSEQ) ............................................................................................... 239
9.12.14 ADC injection data register x (ADC_JDATx) (x= 1…4) ............................................................................240
9.12.15 ADC regulars data register (ADC_DAT) ........................................................................................................ 240
9.12.16 ADC differential mode selection register (ADC_DIFSEL)......................................................................... 240
9.12.17 ADC calibration factor (ADC_CALFACT).................................................................................................241
9.12.18 ADC control register 3 (ADC_CTRL3) ......................................................................................................242
9.12.19 ADC sampling time register 3 (ADC_SAMPT3)........................................................................................243
Digital to analog conversion (DAC)..........................................................................................................................244
Introduction .......................................................................................................................................................... 244
Main features........................................................................................................................................................244
DAC function description and operation description ...........................................................................................246
10.3.1 DAC enable ...................................................................................................................................................246

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10.3.2 DAC output buffer.........................................................................................................................................246
10.3.3 DAC data format ...........................................................................................................................................246
10.3.4 DAC trigger...................................................................................................................................................248
10.3.5 DAC conversion............................................................................................................................................249
10.3.6 DAC output voltage....................................................................................................................................... 249
10.3.7 DMA requests................................................................................................................................................250
10.3.8 The noise ....................................................................................................................................................... 250
10.3.9 Triangular wave generation ........................................................................................................................... 251
DAC dual-channel conversion.............................................................................................................................. 252
10.4.1 Independent trigger without waveform generator..........................................................................................252
10.4.2 Independent triggers producing the same noise.............................................................................................252
10.4.3 Independent triggers that generate different noises .......................................................................................253
10.4.4 Independent triggers that generate the same triangle wave ...........................................................................253
10.4.5 Independent trigger to generate different triangle waves...............................................................................254
10.4.6 Simultaneous software startup....................................................................................................................... 254
10.4.7 Synchronous trigger without waveform generator ........................................................................................255
10.4.8 Synchronous triggers that generate the same noise ....................................................................................... 255
10.4.9 Synchronous triggers that generate different noises ......................................................................................255
10.4.10 Synchronous trigger to generate the same triangle wave.............................................................................256
10.4.11 Synchronous trigger to generate different triangle waves............................................................................256
DAC register.........................................................................................................................................................257
10.5.1 DAC registers overview ................................................................................................................................ 257
10.5.2 DAC control register (DAC_CTRL) ............................................................................................................. 257
10.5.3 DAC software trigger register (DAC_SOTTR)............................................................................................. 260
10.5.4 12 bit right aligned data hold register for DAC1 (DAC_DR12CH1) ............................................................ 260
10.5.5 12 bit left aligned data hold register for DAC1 (DAC_DL12CH1) ..............................................................261
10.5.6 8-bit right-aligned data hold register for DAC1 (DAC_DR8CH1) ............................................................... 261
10.5.7 12 bit right aligned data hold register for DAC2 (DAC_DR12CH2)............................................................ 262
10.5.8 12 bit left aligned data hold register for DAC2 (DAC_DL12CH2) .............................................................. 262
10.5.9 8-bit right-aligned data hold register for DAC2 (DAC_DR8CH2) ............................................................... 262
10.5.10 12 bit right aligned data hold register for dual DAC (DAC_DR12DCH) ................................................... 263
10.5.11 12 bit left aligned data hold register for dual DAC (DAC_DL12DCH)......................................................263
10.5.12 8 bit right aligned data hold register for dual DAC (DAC_DR8DCH) ....................................................... 264
10.5.13 DAC1 data output register (DAC_DATO1) ................................................................................................264
10.5.14 DAC2 data output register (DAC_DATO2) ................................................................................................265
Advanced-control timers (TIM1 and TIM8) ................................................................................................................266
TIM1 and TIM8 introduction ..................................................................................................................................266
Main features of TIM1 and TIM8 ............................................................................................................................ 266
TIM1 and TIM8 function description ....................................................................................................................... 267
11.3.1 Time-base unit ................................................................................................................................................. 267
11.3.2 Counter mode ..................................................................................................................................................268
11.3.3 Repetition counter ............................................................................................................................................273
11.3.4 Clock selection ................................................................................................................................................276

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11.3.5 Capture/compare channels ...............................................................................................................................279
11.3.6 Input capture mode ..........................................................................................................................................282
11.3.7 PWM input mode ............................................................................................................................................. 283
11.3.8 Forced output mode ......................................................................................................................................... 284
11.3.9 Output compare mode ......................................................................................................................................285
11.3.10 PWM mode ................................................................................................................................................... 286
11.3.11 One-pulse mode .............................................................................................................................................289
11.3.12 Clearing the OCxREF signal on an external event ...........................................................................................290
11.3.13 Complementary outputs with dead-time insertion ............................................................................................291
11.3.14 Break function ............................................................................................................................................... 293
11.3.15 Debug mode .................................................................................................................................................. 295
11.3.16 TIMx and external trigger synchronization ......................................................................................................295
11.3.17 Timer synchronization .................................................................................................................................... 298
11.3.18 6-step PWM generation .................................................................................................................................. 298
11.3.19 Encoder interface mode ..................................................................................................................................299
11.3.20 Interfacing with Hall sensor ............................................................................................................................302
TIMx register (x=1, 8) ............................................................................................................................................ 304
11.4.1 Register Overview ........................................................................................................................................... 304
11.4.2 Control register 1 (TIMx_CTRL1) ................................................................................................................... 305
11.4.3 Control register 2 (TIMx_CTRL2) ................................................................................................................... 308
11.4.4 Slave mode control register (TIMx_SMCTRL) .................................................................................................309
11.4.5 DMA/Interrupt enable registers (TIMx_DINTEN) ............................................................................................312
11.4.6 Status registers (TIMx_STS) ............................................................................................................................313
11.4.7 Event generation registers (TIMx_EVTGEN) ...................................................................................................315
11.4.8 Capture/compare mode register 1 (TIMx_CCMOD1) .......................................................................................316
11.4.9 Capture/compare mode register 2 (TIMx_CCMOD2) .......................................................................................320
11.4.10 Capture/compare enable registers (TIMx_CCEN) ...........................................................................................321
11.4.11 Counters (TIMx_CNT) ................................................................................................................................... 324
11.4.12 Prescaler (TIMx_PSC) ................................................................................................................................... 324
11.4.13 Auto-reload register (TIMx_AR) ....................................................................................................................324
11.4.14 Repeat count registers (TIMx_REPCNT) ........................................................................................................325
11.4.15 Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 325
11.4.16 Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 326
11.4.17 Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 326
11.4.18 Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 327
11.4.19 Break and Dead-time registers (TIMx_BKDT) ...............................................................................................327
11.4.20 DMA Control register (TIMx_DCTRL) .......................................................................................................... 329
11.4.21 DMA transfer buffer register (TIMx_DADDR) ..............................................................................................330
11.4.22 Capture/compare mode registers 3(TIMx_CCMOD3) ..................................................................................... 331
11.4.23 Capture/compare register 5 (TIMx_CCDAT5) ................................................................................................ 331
11.4.24 Capture/compare register 6 (TIMx_CCDAT6) ................................................................................................332
General-purpose timers (TIM2, TIM3, TIM4 and TIM5) ..........................................................................................333
General-purpose timers introduction ........................................................................................................................ 333

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Main features of General-purpose timers .................................................................................................................333
General-purpose timers description .........................................................................................................................334
12.3.1 Time-base unit ................................................................................................................................................. 334
12.3.2 Counter mode ..................................................................................................................................................335
12.3.3 Clock selection ................................................................................................................................................340
12.3.4 Capture/compare channels ............................................................................................................................... 344
12.3.5 Input capture mode ..........................................................................................................................................347
12.3.6 PWM input mode ............................................................................................................................................348
12.3.7 Forced output mode ......................................................................................................................................... 349
12.3.8 Output compare mode ......................................................................................................................................349
12.3.9 PWM mode ..................................................................................................................................................... 351
12.3.10 One-pulse mode .............................................................................................................................................354
12.3.11 Clearing the OCxREF signal on an external event ...........................................................................................355
12.3.12 Debug mode .................................................................................................................................................. 356
12.3.13 TIMx and external trigger synchronization .....................................................................................................356
12.3.14 Timer synchronization ....................................................................................................................................356
12.3.15 Encoder interface mode .................................................................................................................................. 361
12.3.16 Interfacing with Hall sensor ...........................................................................................................................363
TIMx register description(x=2, 3 ,4 and 5) ............................................................................................................... 363
12.4.1 Register Overview ........................................................................................................................................... 363
12.4.2 Control register 1 (TIMx_CTRL1) ................................................................................................................... 365
12.4.3 Control register 2 (TIMx_CTRL2) ................................................................................................................... 367
12.4.4 Slave mode control register (TIMx_SMCTRL) .................................................................................................368
12.4.5 DMA/Interrupt enable registers (TIMx_DINTEN) ...........................................................................................371
12.4.6 Status registers (TIMx_STS) ............................................................................................................................372
12.4.7 Event generation registers (TIMx_EVTGEN) ...................................................................................................373
12.4.8 Capture/compare mode register 1 (TIMx_CCMOD1) .......................................................................................374
12.4.9 Capture/compare mode register 2 (TIMx_CCMOD2) .......................................................................................377
12.4.10 Capture/compare enable registers (TIMx_CCEN) ...........................................................................................379
12.4.11 Counters (TIMx_CNT) ..................................................................................................................................380
12.4.12 Prescaler (TIMx_PSC) ................................................................................................................................... 381
12.4.13 Auto-reload register (TIMx_AR) ....................................................................................................................381
12.4.14 Capture/compare register 1 (TIMx_CCDAT1) ................................................................................................ 381
12.4.15 Capture/compare register 2 (TIMx_CCDAT2) ................................................................................................ 382
12.4.16 Capture/compare register 3 (TIMx_CCDAT3) ................................................................................................ 382
12.4.17 Capture/compare register 4 (TIMx_CCDAT4) ................................................................................................ 383
12.4.18 DMA Control register (TIMx_DCTRL) .......................................................................................................... 383
12.4.19 DMA transfer buffer register (TIMx_DADDR)...........................................................................................384
Basic timers (TIM6 and TIM7) ...................................................................................................................................386
Introduction ............................................................................................................................................................ 386
Main features .......................................................................................................................................................... 386
Basic timers description ..........................................................................................................................................387
13.3.1 Time-base unit ................................................................................................................................................. 387

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13.3.2 Counter mode ..................................................................................................................................................388
13.3.3 Clock selection ................................................................................................................................................ 391
13.3.4 Debug mode .................................................................................................................................................... 391
TIMx register description(x = 6 and 7) ....................................................................................................................391
13.4.1 Register overview..........................................................................................................................................392
13.4.2 Control Register 1 (TIMx_CTRL1)............................................................................................................... 392
13.4.3 Control Register 2 (TIMx_CTRL2)............................................................................................................... 393
13.4.4 DMA/Interrupt Enable Registers (TIMx_DINTEN) .....................................................................................394
13.4.5 Status Registers (TIMx_STS)........................................................................................................................395
13.4.6 Event Generation registers (TIMx_EVTGEN).............................................................................................. 395
13.4.7 Counter (TIMx_CNT) ................................................................................................................................... 396
13.4.8 Prescaler (TIMx_PSC) .................................................................................................................................. 396
13.4.9 Automatic reload register (TIMx_AR) ..........................................................................................................396
Real-time clock (RTC)...............................................................................................................................................398
Description ...........................................................................................................................................................398
14.1.1 Specification..................................................................................................................................................398
RTC function description...................................................................................................................................... 399
14.2.1 RTC block diagram........................................................................................................................................ 399
14.2.2 GPIOs of RTC ............................................................................................................................................... 400
14.2.3 RTC register write protection ........................................................................................................................ 400
14.2.4 RTC clock and prescaler................................................................................................................................400
14.2.5 RTC calendar.................................................................................................................................................401
14.2.6 Calendar initialization and configuration ...................................................................................................... 401
14.2.7 Calendar reading............................................................................................................................................401
14.2.8 Calibration clock output ................................................................................................................................402
14.2.9 Programmable alarms....................................................................................................................................403
14.2.10 Alarm configuration.....................................................................................................................................403
14.2.11 Alarm output................................................................................................................................................ 403
14.2.12 Periodic automatic wakeup..........................................................................................................................403
14.2.13 Wakeup timer configuration ........................................................................................................................404
14.2.14 Timestamp function.....................................................................................................................................404
14.2.15 Daylight saving time configuration ............................................................................................................. 404
14.2.16 RTC sub-second register shift......................................................................................................................405
14.2.17 RTC digital clock precision calibration .......................................................................................................405
14.2.18 RTC low power mode.................................................................................................................................. 406
RTC Registers....................................................................................................................................................... 407
14.3.1 RTC Register overview .................................................................................................................................407
14.3.2 RTC Calendar Time Register (RTC_TSH)....................................................................................................408
14.3.3 RTC Calendar Date Register (RTC_DATE)..................................................................................................408
14.3.4 RTC Control Register (RTC_CTRL)............................................................................................................. 409
14.3.5 RTC Initial Status Register (RTC_INITSTS)................................................................................................ 411
14.3.6 RTC Prescaler Register (RTC_PRE) .............................................................................................................413
14.3.7 RTC Wakeup Timer Register (RTC_WKUPT).............................................................................................. 413

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14.3.8 RTC Alarm A Register (RTC_ALARMA)..................................................................................................... 414
14.3.9 RTC Alarm B Register (RTC_ ALARMB).................................................................................................... 415
14.3.10 RTC Write Protection register (RTC_WRP)................................................................................................416
14.3.11 RTC Sub-second Register (RTC_SUBS).....................................................................................................416
14.3.12 RTC Shift Control Register (RTC_ SCTRL)............................................................................................... 417
14.3.13 RTC Timestamp Time Register (RTC_TST) ...............................................................................................417
14.3.14 RTC Timestamp Date Register (RTC_TSD) ............................................................................................... 418
14.3.15 RTC Timestamp Sub-second Register (RTC_TSSS)...................................................................................419
14.3.16 RTC Calibration Register (RTC_CALIB) ...................................................................................................419
14.3.17 RTC Alarm A sub-second register (RTC_ ALRMASS)...............................................................................420
14.3.18 RTC Alarm B sub-second register (RTC_ ALRMBSS)...............................................................................421
14.3.19 RTC Option Register (RTC_ OPT).............................................................................................................. 421
CRC calculation unit .................................................................................................................................................423
Introduction .......................................................................................................................................................... 423
Main features........................................................................................................................................................423
15.2.1 CRC32...........................................................................................................................................................423
15.2.2 CRC16...........................................................................................................................................................423
Function description ............................................................................................................................................. 424
15.3.1 CRC32...........................................................................................................................................................424
15.3.2 CRC16...........................................................................................................................................................424
CRC registers........................................................................................................................................................425
15.4.1 CRC register overview ..................................................................................................................................425
15.4.2 CRC32 data register (CRC_CRC32DAT) .....................................................................................................425
15.4.3 CRC32 independent data register (CRC_CRC32IDAT)................................................................................425
15.4.4 CRC32 control register (CRC_CRC32CTRL) .............................................................................................. 426
15.4.5 CRC16 control register (CRC_CRC16CTRL) .............................................................................................. 426
15.4.6 CRC16 input data register (CRC_CRC16DAT)............................................................................................427
15.4.7 CRC cyclic redundancy check code register (CRC_CRC16D).....................................................................427
15.4.8 LRC result register (CRC_LRC) ................................................................................................................... 428
Independent watchdog (IWDG) ...............................................................................................................................429
Introduction .......................................................................................................................................................... 429
Main features........................................................................................................................................................429
Functional description .......................................................................................................................................... 430
16.3.1 Register access protection .............................................................................................................................430
16.3.2 Debug mode .................................................................................................................................................. 431
User interface........................................................................................................................................................431
16.4.1 Operate flow.................................................................................................................................................. 431
16.4.2 IWDG configuration flow .............................................................................................................................432
IWDG registers..................................................................................................................................................... 433
16.5.1 IWDG register overview ............................................................................................................................... 433
16.5.2 IWDG key register (IWDG_KEY)................................................................................................................ 433
16.5.3 IWDG pre-scaler register (IWDG_PREDIV)................................................................................................ 433

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16.5.4 IWDG reload register (IWDG_RELV).......................................................................................................... 434
16.5.5 IWDG status register (IWDG_STS)..............................................................................................................435
Window watchdog (WWDG).................................................................................................................................... 436
Introduction .......................................................................................................................................................... 436
Main features........................................................................................................................................................436
Function description ............................................................................................................................................. 436
Timing for refresh watchdog and interrupt generation .........................................................................................437
Debug mode..........................................................................................................................................................438
User interface........................................................................................................................................................438
17.6.1 WWDG configuration flow...........................................................................................................................438
WWDG registers ..................................................................................................................................................439
17.7.1 WWDG register overview.............................................................................................................................439
17.7.2 WWDG control register (WWDG_CTRL)....................................................................................................439
17.7.3 WWDG config register (WWDG_CFG) .......................................................................................................439
17.7.4 WWDG status register (WWDG_STS).........................................................................................................440
SDIO Interface（SDIO）.........................................................................................................................................441
Main features of SDIO .........................................................................................................................................441
SDIO bus topology...............................................................................................................................................442
SDIO function description....................................................................................................................................444
18.3.1 SDIO adapter.................................................................................................................................................444
18.3.2 SDIO AHB Interface .....................................................................................................................................455
Card function description .....................................................................................................................................456
18.4.1 Confirmation of working voltage range ........................................................................................................456
18.4.2 Card reset.......................................................................................................................................................456
18.4.3 Card identification mode ...............................................................................................................................457
18.4.4 Card identification process............................................................................................................................ 457
18.4.5 Write data block.............................................................................................................................................458
18.4.6 Read data block ............................................................................................................................................. 459
18.4.7 Data Streaming Operation (Only for Multimedia Card)................................................................................459
18.4.8 Erase..............................................................................................................................................................461
18.4.9 Wide bus selection and de-selection.............................................................................................................. 461
18.4.10 Protection management ...............................................................................................................................461
18.4.11 Card status register ......................................................................................................................................465
18.4.12 SD I/O mode................................................................................................................................................ 472
Commands and responses..................................................................................................................................... 473
18.5.1 Application related commands and general commands.................................................................................473
18.5.2 Commands of Multimedia Card/SD Card module ........................................................................................474
18.5.3 Command type .............................................................................................................................................. 476
18.5.4 Command format...........................................................................................................................................477
18.5.5 Response format............................................................................................................................................ 478
Hardware flow control..........................................................................................................................................481
SDIO register........................................................................................................................................................481

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18.7.1 SDIO register overview.................................................................................................................................482
18.7.2 SDIO power control register (SDIO_PWRCTRL)........................................................................................483
18.7.3 SDIO clock control register (SDIO_CLKCTRL)..........................................................................................483
18.7.4 SDIO command argument register (SDIO_CMDARG)................................................................................ 484
18.7.5 SDIO command register (SDIO_CMDCTRL)..............................................................................................485
18.7.6 SDIO command response register(SDIO_CMDRESP).................................................................................486
18.7.7 SDIO response 1..4 register (SDIO_RESPONSEx)...................................................................................... 486
18.7.8 SDIO data timer register (SDIO_DTIMER).................................................................................................. 487
18.7.9 SDIO data length register (SDIO_DATLEN)................................................................................................488
18.7.10 SDIO data control register (SDIO_DATCTRL) ..........................................................................................488
18.7.11 SDIO data counter register (SDIO_DATCOUNT) ......................................................................................490
18.7.12 SDIO status register (SDIO_STS)...............................................................................................................490
18.7.13 SDIO interrupt clear register (SDIO_INTCLR) .......................................................................................... 491
18.7.14 SDIO interrupt enable register (SDIO_INTEN).......................................................................................... 492
18.7.15 SDIO FIFO counter register (SDIO_FIFOCOUNT) ...................................................................................495
18.7.16 SDIO data FIFO register (SDIO_DATFIFO) ..............................................................................................496
Universal serial bus full-speed device interface (USB_FS_Device) .......................................................................497
Introduction .......................................................................................................................................................... 497
Main features........................................................................................................................................................497
Clock configuration.............................................................................................................................................. 498
Functional description .......................................................................................................................................... 498
19.4.1 Access Packet Buffer Memory ......................................................................................................................498
19.4.2 Buffer description table .................................................................................................................................499
19.4.3 Double-buffered endpoints............................................................................................................................500
19.4.4 USB transfer..................................................................................................................................................503
19.4.5 USB events and interrupts.............................................................................................................................508
19.4.6 Endpoint initialization ...................................................................................................................................510
USB registers........................................................................................................................................................ 510
19.5.1 USB register overview .................................................................................................................................. 511
19.5.2 USB endpoint n register (USB_EPn), n=[0..7].............................................................................................. 512
19.5.3 USB control register (USB_CTRL) ..............................................................................................................514
19.5.4 USB interrupt status register (USB_STS) .....................................................................................................516
19.5.5 USB frame number register (USB_FN) ........................................................................................................519
19.5.6 USB device address register (USB_ADDR) ................................................................................................. 519
19.5.7 USB packet buffer description table address register (USB_BUFTAB) ....................................................... 520
Buffer description table ........................................................................................................................................520
19.6.1 Send buffer address register n (USB_ADDRn_TX)......................................................................................521
19.6.2 Send data byte number register n (USB_CNTn_TX).................................................................................... 521
19.6.3 Receive buffer address register n (USB_ADDRn_RX)................................................................................. 521
19.6.4 Receive data byte number register n (USB_CNTn_RX)............................................................................... 522
Controller area network (CAN)................................................................................................................................524
Introduction to CAN............................................................................................................................................. 524

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Main features of CAN ..........................................................................................................................................524
CAN overall introduction ..................................................................................................................................... 525
20.3.1 CAN module.................................................................................................................................................. 525
20.3.2 CAN working mode ......................................................................................................................................525
20.3.3 Send mailbox.................................................................................................................................................527
20.3.4 Receiving filter..............................................................................................................................................527
20.3.5 Receive FIFO ................................................................................................................................................ 527
20.3.6 CAN Test mode .............................................................................................................................................529
20.3.7 CAN Debugging mode.................................................................................................................................. 531
CAN function description.....................................................................................................................................531
20.4.1 Send processing............................................................................................................................................. 531
20.4.2 Time triggered communication mode............................................................................................................532
20.4.3 Non-automatic retransmission mode............................................................................................................. 532
20.4.4 Receiving management .................................................................................................................................533
20.4.5 Identifier filtering ..........................................................................................................................................535
20.4.6 Message storage.............................................................................................................................................538
20.4.7 Bit time characteristic.................................................................................................................................... 539
CAN interrupt.......................................................................................................................................................542
20.5.1 Error management .........................................................................................................................................543
20.5.2 Bus-Off recovery...........................................................................................................................................543
CAN Configuration Flow .....................................................................................................................................543
CAN Register File ................................................................................................................................................545
20.7.1 Register Description ......................................................................................................................................545
20.7.2 CAN register address overview.....................................................................................................................546
20.7.3 CAN control and status register.....................................................................................................................550
20.7.4 CAN mailbox register....................................................................................................................................561
20.7.5 CAN filter register.........................................................................................................................................566
Serial peripheral interface/Inter-IC Sound (SPI/ I2S) ............................................................................................570
Introduction .......................................................................................................................................................... 570
Main features........................................................................................................................................................570
21.2.1 SPI features....................................................................................................................................................570
21.2.2 I2S features .................................................................................................................................................... 570
SPI function description .......................................................................................................................................571
21.3.1 General description........................................................................................................................................571
21.3.2 SPI work mode ..............................................................................................................................................574
21.3.3 Status flag...................................................................................................................................................... 580
21.3.4 Disabling the SPI...........................................................................................................................................581
21.3.5 SPI communication using DMA....................................................................................................................582
21.3.6 CRC calculation............................................................................................................................................. 583
21.3.7 Error flag ....................................................................................................................................................... 584
21.3.8 SPI interrupt .................................................................................................................................................. 584
I2S function description ........................................................................................................................................ 585
21.4.1 Supported audio protocols............................................................................................................................. 586

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21.4.2 Clock generator ............................................................................................................................................. 592
21.4.3 I2S Transmission and reception sequence...................................................................................................... 594
21.4.4 Status flag...................................................................................................................................................... 596
21.4.5 Error flag ....................................................................................................................................................... 597
21.4.6 I2S interrupt ...................................................................................................................................................597
21.4.7 DMA function................................................................................................................................................ 597
SPI and I2S register...............................................................................................................................................598
21.5.1 SPI register overview .................................................................................................................................... 598
21.5.2 SPI control register 1 (SPI_CTRL1) (not used in I2S mode) ........................................................................598
21.5.3 SPI control register 2 (SPI_CTRL2).............................................................................................................. 601
21.5.4 SPI status register (SPI_STS)........................................................................................................................601
21.5.5 SPI data register (SPI_DAT)..........................................................................................................................603
21.5.6 SPI CRC polynomial register (SPI_CRCPOLY) (not used in I2S mode) ......................................................603
21.5.7 SPI RX CRC register (SPI_CRCRDAT) (not used in I2S mode) ..................................................................603
21.5.8 SPI TX CRC register（SPI_CRCTDAT）...................................................................................................604
21.5.9 SPI_ I2S configuration register（SPI_I2SCFG）.........................................................................................604
21.5.10 SPI_I2S prescaler register (SPI_I2SPREDIV)............................................................................................. 606
I2C interface ............................................................................................................................................................... 607
Introduction .......................................................................................................................................................... 607
Main features........................................................................................................................................................607
Function description ............................................................................................................................................. 607
22.3.1 SDA and SCL line control............................................................................................................................. 607
22.3.2 Software communication process..................................................................................................................608
22.3.3 Error conditions description ..........................................................................................................................618
22.3.4 DMA application ........................................................................................................................................... 619
22.3.5 Packet error check .........................................................................................................................................620
22.3.6 SMBus...........................................................................................................................................................621
Debug mode..........................................................................................................................................................623
Interrupt request.................................................................................................................................................... 623
I2C registers..........................................................................................................................................................624
22.6.1 I2C register overview ....................................................................................................................................624
22.6.2 I2C Control register 1 (I2C_CTRL1) ............................................................................................................ 625
22.6.3 I2C Control register 2 (I2C_CTRL2) ............................................................................................................ 627
22.6.4 I2C Own address register 1 (I2C_OADDR1)................................................................................................628
22.6.5 I2C Own address register 2 (I2C_OADDR2)................................................................................................629
22.6.6 I2C Data register (I2C_DAT) ........................................................................................................................629
22.6.7 I2C Status register 1 (I2C_STS1)..................................................................................................................629
22.6.8 I2C Status register 2 (I2C_STS2)..................................................................................................................633
22.6.9 I2C Clock control register (I2C_CLKCTRL)................................................................................................634
22.6.10 I2C Rise time register (I2C_TMRISE)........................................................................................................635
Universal synchronous asynchronous receiver transmitter (USART) ..................................................................636
Introduction .......................................................................................................................................................... 636

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Main features........................................................................................................................................................636
Functional block diagram ..................................................................................................................................... 637
Function description ............................................................................................................................................. 637
23.4.1 USART frame format ....................................................................................................................................638
23.4.2 Transmitter.....................................................................................................................................................639
23.4.3 Receiver.........................................................................................................................................................641
23.4.4 Generation of fractional baud rate.................................................................................................................644
23.4.5 Receiver’s tolerance clock deviation .............................................................................................................646
23.4.6 Parity control .................................................................................................................................................646
23.4.7 DMA application ........................................................................................................................................... 647
23.4.8 Hardware flow control...................................................................................................................................649
23.4.9 Multiprocessor communication .....................................................................................................................651
23.4.10 Synchronous mode ......................................................................................................................................653
23.4.11 Single-wire half-duplex mode ..................................................................................................................... 655
23.4.12 IrDA SIR ENDEC mode .............................................................................................................................656
23.4.13 LIN mode ....................................................................................................................................................657
23.4.14 Smartcard mode (ISO7816).........................................................................................................................660
Interrupt request.................................................................................................................................................... 662
Mode support........................................................................................................................................................663
USART registers...................................................................................................................................................663
23.7.1 USART register overview..............................................................................................................................663
23.7.2 USART Status register (USART_STS) ......................................................................................................... 664
23.7.3 USART Data register (USART_DAT)........................................................................................................... 666
23.7.4 USART Baud rate register (USART_BRCF) ................................................................................................667
23.7.5 USART control register 1 register (USART_CTRL1)................................................................................... 667
23.7.6 USART control register 2 register (USART_CTRL2)................................................................................... 669
23.7.7 USART control register 3 register (USART_CTRL3)................................................................................... 670
23.7.8 USART guard time and prescaler register (USART_GTP) ...........................................................................672
Quad Serial Peripheral Interface (QSPI) ................................................................................................................674
Introduction .......................................................................................................................................................... 674
QSPI Main features ..............................................................................................................................................674
Function description ............................................................................................................................................. 675
QSPI command sequence .....................................................................................................................................675
Operating procedures............................................................................................................................................676
24.5.1 QSPI indirect mode ....................................................................................................................................... 676
24.5.2 QSPI Indirect send operation......................................................................................................................... 677
24.5.3 QSPI indirect receive operation..................................................................................................................... 679
QSPI register ........................................................................................................................................................ 681
24.6.1 QSPI register overview.................................................................................................................................. 681
24.6.2 QSPI Control 0 Register (QSPI_CTRL0)...................................................................................................... 683
24.6.3 QSPI Control 1 Register (QSPI_CTRL1)......................................................................................................685
24.6.4 QSPI Enable Register (QSPI_EN).................................................................................................................685
24.6.5 QSPI Microwire Control Register (QSPI_MW_CTRL)................................................................................686

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24.6.6 QSPI Slave Enable Register (QSPI_SLAVE_EN) ........................................................................................ 686
24.6.7 QSPI Baud Rate Select Register (QSPI_BAUD) .......................................................................................... 687
24.6.8 QSPI Transmit FIFO Threshold Level Register (QSPI_TXFT) ....................................................................687
24.6.9 QSPI Receive FIFO Threshold Level Register (QSPI_RXFT) .....................................................................688
24.6.10 QSPI Transmit FIFO Level Register (QSPI_TXFN)................................................................................... 688
24.6.11 QSPI Receive FIFO Level Register (QSPI_RXFN)....................................................................................689
24.6.12 QSPI Status Register (QSPI_STS) .............................................................................................................. 689
24.6.13 QSPI Interrupt Mask Register (QSPI_IMASK) ..........................................................................................690
24.6.14 QSPI Interrupt Status Register (QSPI_ISTS) ..............................................................................................691
24.6.15 QSPI Raw Interrupt Status Register (QSPI_RISTS) ...................................................................................692
24.6.16 QSPI Transmit FIFO Overflow Interrupt Clear Register (QSPI_TXFOI_CLR) .........................................693
24.6.17 QSPI Receive FIFO Overflow Interrupt Clear Register (QSPI_RXFOI_CLR) ..........................................693
24.6.18 QSPI Receive FIFO Underflow Interrupt Clear Register (QSPI_RXFUI_CLR) ........................................693
24.6.19 QSPI Multi-Master Interrupt Clear Register (QSPI_MMCI_CLR) ............................................................694
24.6.20 QSPI Interrupt Clear Register (QSPI_ICLR) ..............................................................................................694
24.6.21 QSPI DMA Control Register (QSPI_DMA_CTRL) ...................................................................................695
24.6.22 QSPI DMA Transmit Data Level Register (QSPI_DMATDL_CTRL)........................................................ 695
24.6.23 QSPI DMA Receive Data Level Register (QSPI_DMARDL_CTRL) ........................................................695
24.6.24 QSPI Data Register（QSPI_DATx）.........................................................................................................696
24.6.25 QSPI RX Sample Delay Register (QSPI_RS_DELAY) ..............................................................................696
24.6.26 QSPI Enhanced SPI Mode Control 0 Register（QSPI_ENH_CTRL0）....................................................697
24.6.27 QSPI DDR Transmit Drive Edge Register (QSPI_DDR_TXDE) ...............................................................698
24.6.28 QSPI XIP Mode bits Register (QSPI_XIP_MODE)....................................................................................698
24.6.29 QSPI XIP INCR transfer opcode Register (QSPI_XIP_INCR_TOC).........................................................699
24.6.30 QSPI XIP WRAP transfer opcode Register (QSPI_XIP_WRAP_TOC).....................................................699
24.6.31 QSPI XIP Control Register (QSPI_XIP_CTRL)......................................................................................... 700
24.6.32 QSPI XIP Slave Enable Register (QSPI_XIP_SLAVE_EN)....................................................................... 701
24.6.33 QSPI XIP Receive FIFO Overflow Interrupt Clear Register (QSPI_XIP_RXFOI_CLR)...........................702
24.6.34 QSPI XIP time out for continuous transfers register（QSPI_XIP_TOUT）..............................................702
Ethernet (ETH)..........................................................................................................................................................704
Introduction .......................................................................................................................................................... 704
Main features........................................................................................................................................................704
Function block diagram........................................................................................................................................ 706
Function description ............................................................................................................................................. 706
25.4.1 IEEE 802.3 ethernet frame format.................................................................................................................706
25.4.2 Pin configuration (alternate) method.............................................................................................................707
25.4.3 SMI interface.................................................................................................................................................708
25.4.4 MII interface.................................................................................................................................................. 709
25.4.5 RMII interface ............................................................................................................................................... 711
25.4.6 MAC function description.............................................................................................................................712
25.4.7 Power management (PMT)............................................................................................................................ 721
25.4.8 Ethernet DMA function description...............................................................................................................724
25.4.9 Precision time protocol (PTP) ....................................................................................................................... 740

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25.4.10 Typical ethernet configuration flow example ..............................................................................................743
25.4.11 Ethernet interrupt......................................................................................................................................... 744
ETH register .........................................................................................................................................................744
25.5.1 ETH register overview ..................................................................................................................................745
25.5.2 ETH MAC configuration register (ETH_MACCFG)....................................................................................748
25.5.3 ETH MAC frame filter register (ETH_MACFFLT)......................................................................................750
25.5.4 ETH MAC HASH list high register (ETH_MACHASHHI) .........................................................................752
25.5.5 ETH MAC HASH list low register (ETH_MACHASHLO) .........................................................................752
25.5.6 ETH MAC MII address register (ETH_MACMIIADDR) ............................................................................753
25.5.7 ETH MAC MII data register (ETH_MACMIIDAT) ..................................................................................... 754
25.5.8 ETH MAC flow control register (ETH_MACFLWCTRL) ...........................................................................754
25.5.9 ETH MAC VLAN tag register (ETH_MACVLANTAG) .............................................................................756
25.5.10 ETH MAC remote wakeup frame filter register (ETH_MACRMTWUFRMFLT) ..................................... 756
25.5.11 ETH MAC PMT control and status register (ETH_MACPMTCTRLSTS)................................................. 757
25.5.12 ETH MAC interrupt status register (ETH_MACINTSTS).......................................................................... 758
25.5.13 ETH MAC interrupt mask register (ETH_MACINTMSK).........................................................................759
25.5.14 ETH MAC address 0 high register (ETH_MACADDR0HI)....................................................................... 759
25.5.15 ETH MAC address 0 low register (ETH_MACADDR0LO)....................................................................... 760
25.5.16 ETH MAC address 1 high register (ETH_MACADDR1HI)....................................................................... 760
25.5.17 ETH MAC address 1 low register (ETH_MACADDR1LO)....................................................................... 761
25.5.18 ETH MAC address 2 high register (ETH_MACADDR2HI)....................................................................... 761
25.5.19 ETH MAC address 2 low register (ETH_MACADDR2LO)....................................................................... 762
25.5.20 ETH MAC address 3 high register (ETH_MACADDR3HI)....................................................................... 762
25.5.21 ETH MAC address 3 low register (ETH_MACADDR3LO)....................................................................... 763
25.5.22 ETH MMC control register (ETH_MMCCTRL) ........................................................................................764
25.5.23 ETH MMC receive interrupt status register (ETH_MMCRXINT) ............................................................. 764
25.5.24 ETH MMC transmit interrupt status register (ETH_MMCTXINT)............................................................ 765
25.5.25 ETH MMC receive interrupt mask register (ETH_MMCRXINTMSK) .....................................................766
25.5.26 ETH MMC transmit interrupt mask register (ETH_MMCTXINTMSK)....................................................767
25.5.27 ETH MMC transmitted “good” frame counter register after 1 collision (ETH_MMCTXGFASCCNT) .... 767
25.5.28 ETH MMC transmitted “good” frame counter register after more than 1 collision
(ETH_MMCTXGFAMSCCNT) ..............................................................................................................................768
25.5.29 ETH MMC transmitted “good” frame counter register (ETH_MMCTXGFCNT)...................................... 768
25.5.30 ETH MMC CRC error received frame counter register (ETH_MMCRXFCECNT)...................................769
25.5.31 ETH MMC alignment error received frame counter register (ETH_MMCRXFAECNT)...........................769
25.5.32 ETH MMC receive "good" unicast frame counter register (ETH_MMCRXGUFCNT) ............................. 769
25.5.33 ETH PTP timestamp control register (ETH_PTPTSCTRL)........................................................................ 770
25.5.34 ETH PTP subsecond increment register (ETH_PTPSSINC).......................................................................771
25.5.35 ETH PTP timestamp high register (ETH_PTPSEC)....................................................................................771
25.5.36 ETH PTP timestamp low register (ETH_PTPNS)....................................................................................... 772
25.5.37 ETH PTP timestamp high update register (ETH_PTPSECUP)...................................................................772
25.5.38 ETH PTP timestamp low update register (ETH_PTPNSUP) ......................................................................773
25.5.39 ETH PTP timestamp addend register (ETH_PTPTSADD) ......................................................................... 773

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25.5.40 ETH PTP target time high register (ETH_PTPTTSEC) ..............................................................................774
25.5.41 ETH PTP target time low register (ETH_PTPTTNS)..................................................................................774
25.5.42 ETH DMAbus mode register (ETH_DMABUSMOD) ..............................................................................775
25.5.43 ETH DMA transmit query request register (ETH_DMATXPD) ................................................................. 777
25.5.44 ETH DMA receive query request register (ETH_DMARXPD) ..................................................................777
25.5.45 ETH DMA receive descriptor list address register (ETH_DMARXDLADDR)..........................................778
25.5.46 ETH DMA transmit descriptor list address register (ETH_DMATXDLADDR).........................................778
25.5.47 ETH DMA status register (ETH_DMASTS)...............................................................................................779
25.5.48 ETH DMA operation mode register (ETH_DMAOPMOD)........................................................................783
25.5.49 ETH DMA interrupt enable register (ETH_DMAINTEN).......................................................................... 785
25.5.50 ETH DMA missed frames and buffer overflow counter register (ETH_DMAMFBOCNT) .......................787
25.5.51 ETH DMA current transmit descriptor address register (ETH_DMACHTXDESC)................................... 788
25.5.52 ETH DMA current receive descriptor address register (ETH_DMACHRXDESC) ....................................788
25.5.53 ETH DMA current transmit buffer address register (ETH_DMACHTXBADDR) .....................................789
25.5.54 ETH DMA current receive buffer address register (ETH_DMACHRXBADDR).......................................789
Comparator (COMP) ................................................................................................................................................790
COMP system connection block diagram.............................................................................................................790
Main features........................................................................................................................................................793
COMP configuration process................................................................................................................................ 793
COMP working mode........................................................................................................................................... 794
26.4.1 Window mode................................................................................................................................................ 794
26.4.2 Independent comparator ................................................................................................................................794
Comparator interconnection .................................................................................................................................794
Interrupt................................................................................................................................................................795
COMP register......................................................................................................................................................796
26.7.1 COMP register overview............................................................................................................................... 796
26.7.2 COMP control register (COMPx_CTRL)...................................................................................................... 798
26.7.3 COMP window mode register (COMP_WINMODE)...................................................................................799
26.7.4 COMP lock register (COMP_LOCK) ...........................................................................................................800
26.7.5 COMP interrupt enable register (COMP_INTEN)........................................................................................ 800
26.7.6 COMP interrupt status register (COMP_INTSTS)........................................................................................ 801
26.7.7 COMP filter register (COMPx_FILC)...........................................................................................................801
26.7.8 COMP filter frequency division register (COMPx_FILP) ............................................................................802
26.7.9 COMP reference voltage register (COMP_VREFSCL) ................................................................................802
Operational Amplifier (OPAMP)..............................................................................................................................804
Main features........................................................................................................................................................804
27.1.1 OPAMP function description......................................................................................................................... 804
27.1.2 Internal connection between OPAMP and COMP.........................................................................................806
OPAMP working mode.........................................................................................................................................809
27.2.1 OPAMP independent op amp mode............................................................................................................... 809
27.2.2 OPAMP follow mode.....................................................................................................................................809
27.2.3 OPAMP internal gain (PGA) mode ............................................................................................................... 810

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27.2.4 OPAMP with filter internal gain mode .......................................................................................................... 811
27.2.5 OPAMP calibration........................................................................................................................................812
27.2.6 OPAMP independent write protection...........................................................................................................812
27.2.7 OPAMP TIMER controls the switching mode...............................................................................................812
OPAMP register....................................................................................................................................................812
27.3.1 OPAMP register overview.............................................................................................................................812
27.3.2 OPAMP Control Status Register (OPAMPx_CS).......................................................................................... 813
27.3.3 OPAMP Lock register (OPAMP_LOCK)......................................................................................................815
DVP interface (DVP) .................................................................................................................................................816
Introduction .......................................................................................................................................................... 816
Hardware Interface ...............................................................................................................................................816
28.2.1 Pin multiplexing mode .................................................................................................................................. 816
28.2.2 Interface Timing ............................................................................................................................................817
Operating Instructions ..........................................................................................................................................817
28.3.1 General operation process .............................................................................................................................817
28.3.2 DMA application ........................................................................................................................................... 818
28.3.3 Image size......................................................................................................................................................818
28.3.4 Image area ..................................................................................................................................................... 818
28.3.5 Image scaling................................................................................................................................................. 818
28.3.6 Soft reset........................................................................................................................................................819
28.3.7 Interrupts .......................................................................................................................................................819
28.3.8 Read FIFO data .............................................................................................................................................819
28.3.9 Notes..............................................................................................................................................................819
DVP register .........................................................................................................................................................820
28.4.1 DVP register overview .................................................................................................................................. 820
28.4.2 DVP Control Register（DVP_CTRL）........................................................................................................ 820
28.4.3 DVP Status Register（DVP_STS）.............................................................................................................822
28.4.4 DVP Interrupt Status Register（DVP_INTSTS）........................................................................................ 823
28.4.5 DVP Interrupt Enable Register......................................................................................................................824
28.4.6 DVP interrupt trigger status register（DVP_MINTSTS）...........................................................................825
28.4.7 DVP image start register（DVP_WST）..................................................................................................... 827
28.4.8 DVP image size register（DVP_WSIZE）.................................................................................................. 827
28.4.9 DVP FIFO register（DVP_FIFO）.............................................................................................................. 827
Debug support (DBG)................................................................................................................................................829
Overview ..............................................................................................................................................................829
JTAG/SWD function ............................................................................................................................................ 830
29.2.1 Switch JTAG/SWD interface.........................................................................................................................830
29.2.2 Pin allocation.................................................................................................................................................830
MCU debugging function.....................................................................................................................................831
29.3.1 Low power mode support..............................................................................................................................831
29.3.2 Peripheral debugging support........................................................................................................................ 831
DBG registers.......................................................................................................................................................832