SONIX SN8P1829 User manual

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Version1.0
SN8P1829
USER’S MANUAL
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Version1.0
AMENDMENT HISTORY
Version Date Description
Pre V0.1 Nov. 2003 Preliminary V0.1 first issue
Pre V0.2 Dec. 2003 1. Change Regulator output = 3.8V
2. CPCKS/ PGIACKS clock setting for up-count
3. Add P13M in RAM table
4. PEDGE Register “01”, “10” setting modified. And add P0.1 description
5. Pin assignment : V1/V2/V3 re-arrange.
6. Application circuit : VLCD power came from AVDDR/VDD
Pre V0.3 Jul. 2003 1. Change the minimal different voltage between AVREFH and AVREFL form “1.2V”
to “2.0V”.
2. Modify ADC programming notice.
3. In EOC bit description: Change “reset ADENB bit” to “reset ADS” bit.
4. Modify some electrical characteristics: Varfh, Varfl,add Tast
V1.0 Feb. 2005 1. “B0MOV M, I”, M only supports 0x80~0x87
2. Add external low clock diagram, Figure7-5,7-6
3. Add note for PUSH/POP only one level.
4. External Reset circuit needs 100-ohm resistance. Figure 6-3, 6-4

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page3 Version1.0
Table of Contents
AMENDMENT HISTORY.............................................................................................................. 2
1
1
1PRODUCT OVERVIEW..................................................................................................... 7
FEATURES................................................................................................................................... 7
FEATURES TABLE ...................................................................................................................... 7
SYSTEM BLOCK DIAGRAM ........................................................................................................ 8
PIN ASSIGNMENT ....................................................................................................................... 9
PIN DESCRIPTIONS.................................................................................................................. 10
PIN CIRCUIT DIAGRAMS .......................................................................................................... 11
2
2
2CODE OPTION TABLE ................................................................................................... 12
3
3
3ADDRESS SPACES........................................................................................................ 13
PROGRAM MEMORY (ROM)..................................................................................................... 13
DATA MEMORY (RAM).............................................................................................................. 21
WORKING REGISTERS............................................................................................................. 23
PROGRAM FLAG....................................................................................................................... 26
ACCUMULATOR........................................................................................................................ 27
STACK OPERATIONS................................................................................................................28
PROGRAM COUNTER............................................................................................................... 31
4
4
4ADDRESSING MODE...................................................................................................... 34
OVERVIEW................................................................................................................................. 34

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page4 Version1.0
5
5
5SYSTEM REGISTER....................................................................................................... 36
OVERVIEW................................................................................................................................. 36
SYSTEM REGISTER ARRANGEMENT (BANK 0)..................................................................... 36
6
6
6POWER ON RESET ........................................................................................................ 39
OVERVIEW................................................................................................................................. 39
EXTERNAL RESET DESCRIPTION........................................................................................... 40
LOW VOLTAGE DETECTOR (LVD) DESCRIPTION ................................................................. 41
7
7
7OSCILLATORS................................................................................................................ 42
OVERVIEW................................................................................................................................. 42
SYSTEM MODE DESCRIPTION................................................................................................ 48
SYSTEM MODE CONTROL....................................................................................................... 49
WAKEUP TIME........................................................................................................................... 51
8
8
8TIMERS COUNTERS....................................................................................................... 53
WATCHDOG TIMER (WDT)....................................................................................................... 53
BASIC TIMER 0 (T0) .................................................................................................................. 55
TIMER COUNTER 0 (TC0)......................................................................................................... 56
TIMER COUNTER 1 (TC1)......................................................................................................... 67
PWM FUNCTION DESCRIPTION.............................................................................................. 76
9
9
9INTERRUPT..................................................................................................................... 80
OVERVIEW................................................................................................................................. 80
INTEN INTERRUPT ENABLE REGISTER ................................................................................. 81

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page5 Version1.0
INTRQ INTERRUPT REQUEST REGISTER.............................................................................. 81
INTERRUPT OPERATION DESCRIPTION................................................................................ 82
1
1
10
0
0SERIAL INPUT/OUTPUT TRANSCEIVER (SIO).................................................. 91
OVERVIEW................................................................................................................................. 91
SIOM MODE REGISTER............................................................................................................ 93
SIOB DATA BUFFER ................................................................................................................. 94
SIOR REGISTER DESCRIPTION .............................................................................................. 94
SIO MASTER OPERATING DESCRIPTION .............................................................................. 95
SIO SLAVE OPERATING DESCRIPTION.................................................................................. 99
SIO INTERRUPT OPERATION DESCRIPTION....................................................................... 104
1
1
11
1
1I/O PORT............................................................................................................. 105
OVERVIEW............................................................................................................................... 105
I/O PORT FUNCTION TABLE .................................................................................................. 106
PULL-UP RESISTOR (PNUR) REGISTER................................................................................ 106
I/O PORT MODE ...................................................................................................................... 107
THE PORT2 DISCRIPTION...................................................................................................... 108
I/O PORT DATA REGISTER .................................................................................................... 109
1
1
12
2
2LCD DRIVER....................................................................................................... 110
LCDM1 REGISTER ..................................................................................................................110
LCD TIMING............................................................................................................................. 112
LCD RAM LOCATION .............................................................................................................. 114
1
1
13
3
33-CHANNEL ADC WITH BATTERY MONITOR................................................. 115
OVERVIEW............................................................................................................................... 115
ADM REGISTER....................................................................................................................... 116

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page6 Version1.0
ADR REGISTERS..................................................................................................................... 116
ADB REGISTERS..................................................................................................................... 117
ADC CONVERTING TIME........................................................................................................ 118
1
1
14
4
4CHARGE-PUMP, PGIA AND OPA ..................................................................... 119
OVERVIEW............................................................................................................................... 119
BLOCK DIAGRAM.................................................................................................................... 119
VOLTAGE CHARGE-PUMP REGULATOR (CPR)................................................................... 120
PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) ...................................... 123
OPA – OPERATIONAL AMPLIFIER......................................................................................... 125
1
1
15
5
5APPLICATION CIRCUIT..................................................................................... 126
BLOOD PRESSURE METER APPLICATION CIRCUIT........................................................................... 126
1
1
16
6
6INSTRUCTION SET TABLE............................................................................... 127
1
1
17
7
7ELECTRICAL CHARACTERISTIC..................................................................... 128
ABSOLUTE MAXIMUM RATING.............................................................................................. 128
ELECTRICAL CHARACTERISTIC ........................................................................................... 128
1
1
18
8
8PACKAGE INFORMATION ................................................................................ 130
LQFP80..................................................................................................................................... 130

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page7 Version1.0
1
1
1
PRODUCT OVERVIEW
FEATURES
 Memory configuration
OTP ROM size: 8K * 16 bits
RAM size: 512 * 8 bits (bank 0/1/2)
8-levels stack buffer
LCD RAM size: 4*32 bits
Eight level stack buffer
 I/O pin configuration
Input only: P0, P2
Bi-directional: P1, P5
P2 shared with LCD segment
Wakeup: P0, P1
Pull-up resisters: P0, P1, P2, P5
External interrupt: P0
Port 2 shared with LCD segment
 Six interrupt sources
Four internal interrupts: T0, TC0, TC1, SIO
Two external interrupts: INT0, INT1
 Timer System
T0: 8-bit timer with green mode wakeup function
TC0/TC1: 8-bit timer counters with PWM or buzzer
Real Time Clock (RTC): 0.5/1/2/4 second
On chip watchdog timer
 Powerful instructions
Four clocks per instruction cycle
All instructions are one word length.
Most of instructions are 1 cycle only.
Maximum instruction cycle is “2”.
JMP instruction jumps to all ROM area.
All ROM area look-up table function (MOVC)
Support hardware multiplier (MUL).
 Single power supply: 2.4V ~5.5V
 Built-in Charge-Pump Regulator (CPR)
3.8V output / 5mA driven current
 PGIA: Programmable Gain Instrumentation
Amplifier with fully differential input
Gain 1: 16/32/64/128
Gain 2: 1.3 ~ 2.5
 Two-sets Operational Amplifier
 Three Channel 12-Bit ADC
 Built-in Battery Measurement
 LCD driver:
1/3 duty, 1/3 bias or 1/2 bias
4 common * 32 segment
 SIO function
 Dual clock system offers four operating modes
External high clock: RC type up to 10 MHz
External high clock: Crystal type up to 16 MHz
External Low clock: Crystal 32768Hz, RC mode
Normal mode: Both high and low clock active.
Slow mode: Low clock only.
Sleep mode: Both high and low clock stop.
Green mode: Periodical wakeup by T0 timer.
 Package:
LQFP80
FEATURES TABLE
Timer
CHIP ROM RAM Stack LCD T0 TC0 TC1 I/O ADC PWM
Buzzer SIO Wakeup Pin no. Package
SN8P1829 8K*16 512*8 8 4*32 V V V 20 12-bit 2 1 6 LQFP80
Table 1-1 Selection table of SN8P1829

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page8 Version1.0
SYSTEM BLOCK DIAGRAM
Figure 1-1 Simplified system block diagram
PC
IR OTP
ROM
H-OSC
TIMING GENERATOR
LCD
DRIVER
RAM
SYSTEM REGISTER
ALU
ACC
INTERRUPT CONTROL TIMER & COUNTER
PORT 0
PORT 1 PORT 2 PORT 5
SEG.
COM.
FLAGS
ADC AIN0~AIN2
L-OSC
SIO TX/RX
PWM0
PWM1
PWM0/Buzzer0
PWM1/Buzzer1
Charge
Pump AVDDCP
PGIA PGIAOUT
PGIAIN+/PGIAIN-
AVDDR
PC
IR OTP
ROM
H-OSC
TIMING GENERATOR
LCD
DRIVER
RAM
SYSTEM REGISTER
ALU
ACC
INTERRUPT CONTROLINTERRUPT CONTROL TIMER & COUNTER
PORT 0
PORT 1 PORT 2 PORT 5
SEG.
COM.
FLAGS
ADC AIN0~AIN2
L-OSC
SIO TX/RXSIO TX/RX
PWM0PWM0
PWM1PWM1
PWM0/Buzzer0
PWM1/Buzzer1
Charge
Pump AVDDCP
PGIA PGIAOUT
PGIAIN+/PGIAIN-
AVDDR

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page9 Version1.0
PIN ASSIGNMENT
SN8P1829 (LQFP80)
C+ VDD C- VSS V1 V2 V3 VLCD COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVDDCP 1 O60SEG8
AVDDR 2 59 SEG9
AGND 3 58SEG10
AVREFL4 57SEG11
AIN25 56SEG12
AIN16 55SEG13
AIN07 54SEG14
AVREFH8 53SEG15
PGIABIAS9 52SEG16
PGIAIN+10 51SEG17
PGIAIN-11 50SEG18
PGIAOUT12 49SEG19
OP1IN+13 48SEG20
OP1IN-14 47SEG21
OP1OUT15 46SEG22
OP2IN+16 45SEG23
OP2IN-17 44SEG24/P2.0
OP2OUT18 43SEG25/P2.1
P0.0/INT019 42SEG26/P2.2
P0.1/INT120 41SEG27/P2.3
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1.0 P1.1 P1.2 P1.3
P5.0/SCK
P5.1/SI
P5.2/SO
P5.3/PWM1/BZ1 P5.4/PWM0/BZ0
VDD
LXIN
LXOUT
XIN
XOUT
VPP/RST
GND
SEG31/P2.7 SEG30/P2.6 SEG29/P2.5 SEG28/P2.4

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page10 Version1.0
PIN DESCRIPTIONS
PIN NAME TYPE DESCRIPTION
VDD, VSS P Power supply input pins for digital circuit.
VLCD P Power supply of COM0 ~ COM3, SEG0 ~SEG31.
AVDDR P Regulator power output pin, Voltage=3.8V Maximum output current=5mA.
AGND P Regulator Analog Ground.
AVDDCP P Charge Pump Voltage output. ( connect a 2.2uF or higher capacitor to ground)
RST I System reset input pin. Schmitt trigger structure, active “low”, normal stay to “high”.
XIN, XOUT I, O External oscillator pins. RC mode from XIN.
LXIN, LXOUT I, O Low speed (32768 Hz) oscillator pins. RC mode from LXIN.
P0.0 / INT0 I Port 0.0 and shared with INT0 trigger pin. (Schmitt trigger) / Built-in pull-up resisters.
P0.1 / INT1 I Port 0.1 and shared with INT1 trigger pin. (Schmitt trigger) / Built-in pull-up resisters.
P1.0~P1.3 I/O Port 1.0~P1.3 bi-direction pins / Built-in pull-up resisters.
P5.0 / SCK I/O Port 5.0 bi-direction pin and SIO’s clock input/output / Built-in pull-up resisters.
P5.1 / SI I/O Port 5.1 bi-direction pin and SIO’s data input / Built-in pull-up resisters.
P5.2 / SO I/O Port 5.2 bi-direction pin and SIO’s data output / Built-in pull-up resisters.
P5.3 / BZ1 / PWM1 I/O Port 5.3 bi-direction pin, TC1 ÷ 2 signal output pin or PWM1 output pin.
Built-in pull-up resisters.
P5.4 / BZ0 / PWM0 I/O Port 5.4 bi-direction pin, TC0 ÷ 2 signal output pin or PWM0 output pin.
Built-in pull-up resisters.
P2.0 ~ P2.7 I Port 2.0 ~ Port 2.7 input pins with pull-up register and shared with LCD’s
SEG24~SEG31.
AIN0 ~ AIN3 I Analog signal input pins for ADC converter.
COM0 ~ COM3 O LCD driver common pins.
SEG0 ~ SEG31 O LCD driver segment pins.
AvrefH, AverfL I ADC’s reference high / low voltage input pins.
OP1IN+, OP1IN- I Operational Amplifier 1 Input Channels
OPOUT1 O Operational Amplifier 1 Output Channel
OP2IN+, OP2IN- I Operational Amplifier 2 Input Channels
OPOUT2 O Operational Amplifier 2 Output Channel
PGIAIN+, PGIAIN- I PGIA Input Channels
PGIAOUT O PGIA Output Channel
PGIABIAS I PGIA Bias Voltage input
C+ A Positive capacitor terminal for charge pump regulator
C- A Negative capacitor terminal for charge pump regulator
Table 1-2 SN8P1829 pin description

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page11 Version1.0
PIN CIRCUIT DIAGRAMS
Figure 1-2. Pin Circuit Diagram
Port0 structure
PUR
P0UR
Pin
Int. bus
PUR
P2UR
Pin
Port2 structure
Int. bus
LCD wave form
P2SEG
PUR
P2UR
Pin
Port2 structure
Int. bus
LCD wave form
P2SEG
PUR
PnM, PnUR
Pin
Int. bus
PnM
Latch
Port1, 5 structure
PnM
PUR
PnM, PnUR
Pin
Int. bus
PnM
Latch
Port1, 5 structure
PnM

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page12 Version1.0
2
2
2
CODE OPTION TABLE
Code Option Content Function Description
RC Low cost RC for external high clock oscillator
32K X’tal Low frequency, power saving crystal (e.g. 32.768K) for external high
clock oscillator
12M X’tal High speed crystal /resonator (e.g. 12M) for external high clock oscillator
High_Clk
4M X’tal Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator
Enable External high clock divided by two, FOSC = high clock / 2
High_Clk / 2 Disable FOSC = high clock
Enable Enable Watchdog function
Watch_Dog Disable Disable Watchdog function
Enable Enable ROM code Security function
Security Disable Disable ROM code Security function
8-bit TC0 as 8-bit counter.
6-bit TC0 as 6-bit counter.
5-bit TC0 as 5-bit counter.
TC0_Count
4-bit TC0 as 4-bit counter.
8-bit TC1 as 8-bit counter.
6-bit TC1 as 6-bit counter.
5-bit TC1 as 5-bit counter.
TC1_Count
4-bit TC1 as 4-bit counter.
Enable Enable Noise Filter function to enhance EMI performance
Noise Filter Disable Disable Noise Filter function
Always_ON
Force Watch Dog Timer clock source come from INT 16K RC.
A
lso INT 16K RC never stop both in power down and green mode that
means Watch Dog Timer will always enable both in power down and
green mode.
INT_16K_RC
By_CPUM Enable or Disable internal 16K(@ 3V) RC clock by CPUM register
Enable Enable Low Power function to save Operating current
Low Power Disable Disable Low Power function
Table 2-1. Code Option Table of SN8P1829
Notice:
 In high noisy environment, enable “Noise Filter”, and disable “Low Power” is strongly
recommended.
 The side effect is to increase the lowest valid working voltage level if enable “Noise Filter” or
“Low Power” code option.
 Enable “Low Power” option will reduce operating current except in 32K X’tal or slow mode.

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page13 Version1.0
3
3
3
ADDRESS SPACES
PROGRAM MEMORY (ROM)
OVERVIEW
ROM Maps for SN8P1829 devices provide 8K x 16 OTP memory that programmable by user. The SN8P1829 program
memory is able to fetch instructions through 13-bit wide PC (Program Counter) and can look up ROM data by using
ROM code registers (R, X, Y, Z). In standard configuration, the device’s 8192 * 16-bit program memory has four areas:
 1-word reset vector addresses
 1-word Interrupt vector addresses
 5-words reserved area
 8K words general purpose area
All of the program memory is partitioned into two coding areas, located from 0000H to 0008H and from 0009H to
0FFEH. Former area is assigned for executing reset vector and interrupt vector. The later area is for storing
instruction’s OP-code and look-up table’s data. User’s program is in the last area (0010H~1FFEH).
ROM
0000H Reset vector User reset vector
0001H Jump to user start address
0002H Jump to user start address
0003H General purpose area Jump to user start address
0004H
0005H
0006H
0007H
Reserved
0008H Interrupt vector User interrupt vector
0009H User program
.
.
000FH
0010H
0011H
.
.
1FFEH
General purpose area
End of user program
1FFFH Reserved
Figure 3-1. ROM Address Structure

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page14 Version1.0
USER RESET VECTOR ADDRESS (0000H)
A 1-word vector address area is used to execute system reset. After power-on reset or watchdog timer overflow reset,
chip restarts the program from address 0000h and all system registers will be set as default values. The following
example shows the way to define the reset vector in the program memory.
 Example: After power on reset, external reset active or reset by watchdog timer overflow.
ORG 0 ; 0000H
JMP START ; Jump to user program address.
. ; 0004H ~ 0007H are reserved
ORG 10H
START: ; 0010H, The head of user program.
. ; User program
.
.
.
ENDP ; End of program
INTERRUPT VECTOR ADDRESS (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service is executed, the program
counter (PC) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
 Example 1: This demo program includes interrupt service routine and the user program is behind the
interrupt service routine.
ORG 0 ; 0000H
JMP START ; Jump to user program address.
. ; 0001H ~ 0007H are reserved
ORG 8
; Interrupt service routine
B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag
PUSH ; Push 80H ~ 87H system registers
.
.
.
POP ; Pop 80H ~ 87H system registers
B0XCH A, ACCBUF
RETI ; End of interrupt service routine
START: ; The head of user program.
. ; User program
.
.
.
JMP START ; End of user program
ENDP ; End of program

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page15 Version1.0
 Example 2: The demo program includes interrupt service routine and the address of interrupt service
routine is in a special address of general-purpose area.
ORG 0 ; 0000H
JMP START ; Jump to user program address.
. ; 0001H ~ 0007H are reserved
ORG 08
JMP MY_IRQ ; 0008H, Jump to interrupt service routine address
ORG 10H
START: ; 0010H, The head of user program.
. ; User program
.
.
.
JMP START ; End of user program
MY_IRQ: ; Label of interrupt service routine
B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag
PUSH ; Push 80H ~ 87H system registers
.
.
.
POP ; Pop 80H ~ 87H system registers
B0XCH A, ACCBUF
RETI ; End of interrupt service routine
ENDP ; End of program
 Remark: it is easy to get the rules of SONiX program from demo programs given above. These points are
as following.
1. The address 0000H is a “JMP” instruction to make the program go to general-purpose ROM area. The
0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and
necessary.
2. The interrupt vector located at 0008H. Users can put the whole interrupt service routine from 0008H
(Example1) or to put a “JMP” instruction in 0008H then place the interrupt service routine in other
general-purpose ROM area (Example2) to get modularized coding style.

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page16 Version1.0
CHECKSUM CALCULATION
The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses
(0004H~0007H and last address) when calculate the Checksum value.
 Example:
The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of
user’s code
MOV A, #END_USER_CODE$L
B0MOV END_ADDR1,A ; save low end address to end_addr1
MOV A,#END_USER_CODE$M
B0MOV END_ADDR2,A ; save middle end address to end_addr2
CLR Y ; set Y to 00H
CLR Z ; set Z to 00H
@@:
CALL YZ_CHECK ; call function of check yz value
MOVC ;
B0BSET FC ;clear C flag
ADD DATA1,A ;add A to Data1
MOV A,R
ADC DATA2,A ;add R to Data2
JMP END_CHECK ;check if the YZ address = the end of code
AAA:
INCMS Z ;Z=Z+1
JMP @B ;if Z!= 00H calculate to next address
JMP Y_ADD_1 ;if Z=00H increase Y
END_CHECK:
MOV A,END_ADDR1
CMPRS A,Z ;check if Z = low end address
JMP AAA ;if Not jump to checksum calculate
MOV A,END_ADDR2
CMPRS A,Y ;if Yes, check if Y = middle end address
JMP AAA ;if Not jump to checksum calculate
JMP CHECKSUM_END ;if Yes checksum calculated is done.
YZ_CHECK: ;check if YZ=0004H
MOV A,#04H
CMPRS A,Z ;check if Z=04H
RET ;if Not return to checksum calculate
MOV A,#00H
CMPRS A,Y ;if Yes, check if Y=00H
RET ;if Not return to checksum calculate
INCMS Z ;if Yes, increase 4 to Z
INCMS Z
INCMS Z
INCMS Z
RET ;set YZ=0008H then return
Y_ADD_1:
INCMS Y ;increase Y
NOP
JMP @B ;jump to checksum calculate
CHECKSUM_END:
……….
……….
END_USER_CODE: ; Label of program end

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page17 Version1.0
GENERAL PURPOSE PROGRAM MEMORY AREA
The 8174-word at ROM locations 0010H~1FFEH is used as general-purpose memory. The area stored instruction’s
op-code and look-up table data. The SN8P1829 includes jump table function by using program counter (PC) and
look-up table function by using ROM code registers (R, X, Y, Z).
The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table
function and look-up table function, the program counter can’t leap over the boundary by program counter
automatically. Users need to modify the PCH value to “PCH+1” as the PCL overflow (from 0FFH to 000H).
LOOK-UP TABLE DESCRIPTION
In the ROM’s data look-up function, the X-register points to the highest 8-bit, Y-register to the middle 8-bit and
Z-register to the lowest 8-bit data of ROM address. After MOVC instruction executed, the low-byte data of ROM stores
in ACC and high-byte data stores in R register.
 Example: To look-up the ROM data located “TABLE1”.
B0MOV Y, #TABLE1$M ; To set look-up table1’s middle address
B0MOV Z, #TABLE1$L ; To set look-up table1’s low address.
MOVC ; To look-up data, R = 00H, ACC = 35H
;
; Increment the index address for next address
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Z overflow (FFH 00), Y=Y+1
NOP ; Not overflow
;
@@: MOVC ; To look-up data, R = 51H, ACC = 05H.
. . ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H ; “
DW 2012H ; “
 CAUSION: The Y-register can't increase automatically if Z-register cross boundary from 0xFF to 0x00.
Therefore, user must take care such situation to avoid loop-up table errors. If Z-register
overflows, Y-register must be added by one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
 Note: Because the program counter (PC) is only 13-bit, the X register is useless in the application. Users
can omit “B0MOV X, #TABLE1$H”. SONiX ICE support more larger program memory addressing
capability. So make sure X register is “0” to avoid unpredicted error in loop-up table operation.
 Example: INC_YZ Macro
INC_YZ MACRO
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Y+1
NOP ; Not overflow
@@:
ENDM

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page18 Version1.0
The other coding style of look-up table is to add Y or Z index register by accumulator. Be careful if carry happens.
Refer the following example for detailed information:
 Example: Increase Y and Z register by B0ADD/ADD instruction
B0MOV Y, #TABLE1$M ; To set look-up table’s middle address.
B0MOV Z, #TABLE1$L ; To set look-up table’s low address.
B0MOV A, BUF ; Z = Z + BUF.
B0ADD Z, A
B0BTS1 FC ; Check the carry flag.
JMP GETDATA ; FC = 0
INCMS Y ; FC = 1. Y+1.
NOP
GETDATA: ;
MOVC ; To look-up data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
.
.
. . ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H ; “
DW 2012H ; “

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page19 Version1.0
JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get a new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The way
is easy to make a multi-branch program.
When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump
table leaps over the ROM page boundary or the listing file generated by SONiX assembler. If the jump table leaps over
the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page
(xx00H). Here one page mean 256 words.
 Example : If PC = 0323H (PCH = 03H、PCL = 23H)
ORG 0X0100 ; The jump table is from the head of the ROM boundary
B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
In following example, the jump table starts at 0x00FD. When executing “B0ADD PCL, A”, ACC = 0 or 1, the
jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't
increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program
counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check
whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump
table at the start of ROM boundary (e.g. 0100H).
 Example: Errors occurs if jump table’s range over ROM boundary.
ROM Address
. .
. .
. .
0X00FD B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed.
0X00FE JMP A0POINT ; ACC = 0
0X00FF JMP A1POINT ; ACC = 1
0X0100 JMP A2POINT ; ACC = 2 jump table cross boundary here
0X0101 JMP A3POINT ; ACC = 3
. .
. .
SONiX provides a macro for safe jump table function. This macro checks the ROM boundary and move the jump table
to the right position. The side effect of this macro is maybe wasting some ROM size. Notice the maximum jump table
number for this macro is limited to 254.
@JMP_A MACRO VAL
IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP ($ | 0XFF)
ORG ($ | 0XFF)
ENDIF
ADD PCL, A
ENDM
 Note: “VAL” is the number of the jump table listing number.

SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD Page20 Version1.0
 Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV A, BUF0 ; “BUF0” is from 0 to 4.
@JMP_A 5 ; The number of the jump table listing is five.
JMP A0POINT ; If ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
JMP A4POINT ; ACC = 4, jump to A4POINT
If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h.