Nuvoton ISD3900 User manual

ISD3900
Publication Release Date: Dec 10, 2013
- 1 - Revision 1.5
ISD3900
Multi-Message Record/Playback Devices
with Digital Audio Interface

ISD3900
Publication Release Date: Dec 10, 2013
- 2 - Revision 1.5
TABLE OF CONTENTS
1GENERAL DESCRIPTION .............................................................................................................. 4
2FEATURES ...................................................................................................................................... 4
3BLOCK DIAGRAM ........................................................................................................................... 6
4PINOUT CONFIGURATION ............................................................................................................ 8
5PIN DESCRIPTION.......................................................................................................................... 9
6SPI INTERFACE............................................................................................................................ 12
7ANALOG AND DIGITAL SIGNAL PATH........................................................................................ 15
7.1 ANALOG SIGNAL PATH...........................................................................................................................15
7.1.1 ANAIN & MICIN Analog Input......................................................................................................16
7.1.2 AUX Analog Input..........................................................................................................................17
7.1.3 AUX & AUD Analog Output..........................................................................................................19
7.1.4 BTL Analog Output........................................................................................................................20
7.2 DIGITAL SIGNAL PATH ...........................................................................................................................21
8ISD3900 MEMORY MANAGEMENT............................................................................................. 22
8.1 ISD3900 MEMORY FORMAT...................................................................................................................22
8.2 MESSAGE MANAGEMENT .......................................................................................................................23
8.2.1 Voice Prompts................................................................................................................................24
8.2.2 Voice Macros.................................................................................................................................24
8.2.3 User Data.......................................................................................................................................25
8.2.4 Reserved Sectors............................................................................................................................25
8.2.5 Message Recordings ......................................................................................................................25
8.3 MEMORY AND MESSAGE HEADERS ........................................................................................................26
8.3.1 Memory Header.............................................................................................................................26
8.3.2 Message Header.............................................................................................................................27
8.4 DIGITAL ACCESS OF MEMORY................................................................................................................28
8.5 DEVICE ERASE COMMANDS....................................................................................................................28
8.6 MEMORY CONTENTS PROTECTION .........................................................................................................28
9I2S INTERFACE ............................................................................................................................. 29
10 CLOCK GENERATION............................................................................................................... 30
10.1 EXTERNAL CRYSTAL OSCILLATOR .........................................................................................................31
10.2 I2SCLOCK USAGE ..................................................................................................................................33
10.3 INTERNAL OSCILLATOR..........................................................................................................................33
11 INITIALIZATION & RECORD/PLAY FLOWCHART................................................................... 34
12 DEVICE CONFIGURATION AND STATUS............................................................................... 36
12.1 CLOCK CONFIGURATION.........................................................................................................................36
12.2 DEVICE STATUS REGISTER .....................................................................................................................37
12.3 DEVICE CONFIGURATION REGISTERS .....................................................................................................39
12.4 DEVICE IDENTIFICATION REGISTERS. .....................................................................................................59
13 SPI COMMANDS........................................................................................................................ 60
13.1 AUDIO PLAY AND RECORD COMMANDS.................................................................................................62

ISD3900
Publication Release Date: Dec 10, 2013
- 3 - Revision 1.5
13.1.1 Play Voice Prompt.........................................................................................................................62
13.1.2 Play Voice Prompt @Rn, n = 0 ~ 7 ...............................................................................................63
13.1.3 Execute Voice Macro.....................................................................................................................63
13.1.4 Record Message.............................................................................................................................64
13.1.5 Record Message at Address...........................................................................................................64
13.1.6 Play Message at Address ...............................................................................................................65
13.1.7 Play Silence....................................................................................................................................66
13.1.8 Stop Command...............................................................................................................................66
13.1.9 Erase Message at Address .............................................................................................................67
13.1.10 SPI Write PCM Data .................................................................................................................67
13.1.11 SPI Read PCM Data..................................................................................................................69
13.1.12 SPI Send Compressed Data to Decode ......................................................................................70
13.1.13 SPI Receive Encoded Data ........................................................................................................71
13.2 DEVICE STATUS COMMANDS..................................................................................................................72
13.2.1 Read Status ....................................................................................................................................72
13.2.2 Read Interrupt................................................................................................................................73
13.2.3 Read Recorded Message Address Details......................................................................................73
13.2.4 Read Message Length ....................................................................................................................74
13.2.5 Read I3900 ID................................................................................................................................74
13.3 DIGITAL MEMORY COMMANDS..............................................................................................................75
13.3.1 Digital Read...................................................................................................................................75
13.3.2 Digital Write ..................................................................................................................................75
13.3.3 Erase Memory................................................................................................................................76
13.3.4 Chip Erase .....................................................................................................................................77
13.4 DEVICE CONFIGURATION COMMANDS....................................................................................................77
13.4.1 PWR_UP –Power up.....................................................................................................................77
13.4.2 PWR_DN –Power Down...............................................................................................................78
13.4.3 SET_CLK_CFG –Set Clock Configuration Register.....................................................................78
13.4.4 RD_CLK_CFG –Read Clock Configuration Register...................................................................79
13.4.5 WR_CFG_REG –Write Configuration Register ...........................................................................79
13.4.6 RD_CFG_REG –Read Configuration Register.............................................................................79
14 ELECTRICAL CHARACTERISTICS .......................................................................................... 80
14.1 ABSOLUTE MAXIMUM RATINGS.............................................................................................................80
14.2 OPERATING CONDITIONS........................................................................................................................80
14.3 DC PARAMETERS ...................................................................................................................................80
14.4 AC PARAMETERS ...................................................................................................................................82
14.4.1 Internal Oscillator .........................................................................................................................82
14.4.2 Inputs .............................................................................................................................................82
14.4.3 Outputs...........................................................................................................................................83
14.4.4 ADC and DAC Frequency Responses............................................................................................85
14.4.5 SPI Timing .....................................................................................................................................90
14.4.6 I2S Timing ......................................................................................................................................91
15 APPLICATION DIAGRAM.......................................................................................................... 93
16 PACKAGE SPECIFICATION...................................................................................................... 94
16.1 48 LEAD LQFP(7X7X1.4MM FOOTPRINT 2.0MM)....................................................................................94
17 ORDERING INFORMATION...................................................................................................... 95
18 REVISION HISTORY.................................................................................................................. 96

ISD3900
Publication Release Date: Dec 10, 2013
- 4 - Revision 1.5
1 GENERAL DESCRIPTION
The ISD3900 is a multi-message ChipCorder®featuring digital compression, comprehensive memory
management, and integrated analog/digital audio signal paths. The message management feature is
designed to make message recording simple and address-free as well as make code development
easier for playback-only applications. The ISD3900 utilizes winbond’s 25X and 25Q series flash
memory to provide non-volatile audio record/playback for a two-chip solution. Unlike other ChipCorder
series, the ISD3900 provides an I2S digital audio interface, faster digital recording, higher sampling
frequency, and a signal path with SNR equivalent to 12bit resolution.
The ISD3900 can take digital audio data via I2S or SPI interface. When I2S input is selected, it will
replace the analog audio inputs and will support sample rates of 32, 44.1 or 48 kHz depending upon
clock configuration. When SPI interface is chosen, the sample rate of the audio data sent must be one
of the ISD3900 supported sample rates.
The ISD3900 has built-in analog audio inputs, analog audio line driver, and speaker driver output. The
two analog audio inputs to the device are: (1) AUXIN has a fixed gain configured by SPI command,
and (2) ANAIN/ANAOUT has a fixed gain amplifier with the gain set by two external resistors.
ANAIN/ANAOUT can also be used as a microphone differential input (ANAIN/ANAOUT becomes
MIC+/MIC-) in conjunction with an automatic gain control (AGC) circuit configured by SPI command.
Analog outputs are available in three forms: (1) AUXOUT is a single-ended voltage output; (2)
AUDOUT can be configured as either a single-ended voltage output or a single-ended current output;
(3) BTL (bridge-tied-load) is a differential voltage output.
2 FEATURES
External Memory: support winbond’s 25X and 25Q SpiFlash.
oThe addressing ability of ISD3900 is up to 128Mbit
1
, which is 64-minute recording time based
on 8kHz/4bit ADPCM.
Fast Digital Programming
oProgramming rate can go up to 1Mbits/second mainly limited by the flash memory write rate.
Message Management
oPerform address-free recording: The ISD3900 allocates memory for new recording requests
and upon completion, returns a start address to the host via SPI interface
oStore pre-recorded audio (Voice Prompts) using high quality digital compression
oUse a simple index based command for playback
oExecute pre-programmed macro scripts (Voice Macros) designed to control the configuration
of the device and play back Voice Prompts sequences and message recordings.
Sample Rate
oSeven record and playback sampling frequencies are available for a given master sample
rate. For example, the record and playback sampling frequencies of 4, 5.3, 6.4, 8, 12.8, 16
and 32kHz are available when the device is clocked at a 32kHz master sample rate.
oFor I2S operation, 32, 44.1 and 48kHz master sample rates are available with record and
playback sampling frequencies scaling accordingly.
Compression Algorithms
oFor recording
ADPCM: 2, 3, 4 or 5 bits per sample
1
For details please refer to Section 8.

ISD3900
Publication Release Date: Dec 10, 2013
- 5 - Revision 1.5
µ-Law: 6, 7 or 8 bits per sample
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample. Each sampled value is stored as a code, offering no
compression but preserving maximum resolution
oFor Pre-Recorded Voice Prompts
µ-Law: 6, 7 or 8 bits per sample
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample
Enhanced ADPCM: 2, 3, 4 or 5 bits per sample
Variable-bit-rate optimized compression. This allows best possible compression given a
metric of SNR and background noise levels.
Oscillator
oInternal oscillator with internal reference: 2.048 MHz with ±10% deviation
oInternal oscillator with external resistor: 2.048 MHz with ±5% deviation when Rosc is
78.7Kohm
oExternal crystal or clock input
oI2S bit clock input
oCrystals and resonators support standard audio sampling rates of 2.048, 4.096, 8.192, 12.288
and11.2896MHz
Inputs
oAUXIN: Analog input with 2-bit gain control configured by SPI command
oANAIN/ANAOUT:
Analog input with the gain set by two external resistors from ANAOUT to ANAIN, or
Microphone differential input (ANAIN/ANAOUT becomes MIC+/MIC-)
oDigital AGC:
Automatic gain control of digitized data from the analog input
Outputs
oPWM: Class D speaker driver to direct drive an 8Ω speaker or buzzer
oAUDOUT: configurable as a current or voltage single-ended line driver
oAUXOUT: a single-ended voltage output
oBTL: a differential voltage output
I/Os
oSPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data
oI2S interface: I2S_CLK, I2S_WS, I2S_SDI, I2S_SDO for digital audio data
o8 GPIO pins (4 of the 8 GPIO pins share with I2S).
Three 8-bit Volume Control set by SPI command for flexible mixing
oVOLA: volume control for the digital audio data from I2S or analog inputs
oVOLB: volume control for the digital audio data from decompression block or SPI
oVOLC: master volume control for PWM, AUDOUT, AUXOUT and I2S outputs
Operating Voltage: 2.7-3.6V
Standby Current: 1uA typical
Package: Green 48L-LQFP
Temperature Options:
oIndustrial: -40C to 85C

ISD3900
Publication Release Date: Dec 10, 2013
- 6 - Revision 1.5
3 BLOCK DIAGRAM
AUDOUT
AUXIN
ANAIN
+Digital Signal Path:
Digital Filters
Resampling
Digital Mixing
Volume Control
DAC
ADC +
AUXOUT
PWM
Control
Compression
De-Compression
Flash Memory
Controller
I2S
Interface
SPI
Interface
Memory Management
and Command
Interpreter
SCK
SDI
WS
SCLK
SSB
MISO
MOSI
INTB
RDY/BSYB
AUDOUT
AUXOUT
SPK+
SPK-
SUM1 SUM2
ADC_MUX
SDO
SUM2_MUX
AUD_MUX AUX_MUX
GPIO
Controller
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4/
GPIO5/
GPIO6/
GPIO7/
A
G
C
ANAIN
ANAOUT
Av = 0, 3, 6, 9dB
AUXIN
SPK+_MUX SPK-_MUX
CLK
CSB
DI
DO
Figure 3-1 ISD3900 Block Diagram, ANAIN Selected

ISD3900
Publication Release Date: Dec 10, 2013
- 7 - Revision 1.5
AUDOUT
AUXIN
MICIN
Digital Signal Path:
Digital Filters
Resampling
Digital Mixing
Volume Control
DAC
ADC +
AUXOUT
PWM
Control
Compression
De-Compression
Flash Memory
Controller
I2S
Interface
SPI
Interface
Memory Management
and Command
Interpreter
SCK
SDI
WS
SCLK
SSB
MISO
MOSI
INTB
RDY/BSYB
AUDOUT
AUXOUT
SPK+
SPK-
SUM2
SDO
SUM2_MUX
AUD_MUX AUX_MUX
GPIO
Controller
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4/
GPIO5/
GPIO6/
GPIO7/
A
G
C
MIC+
MIC-
Av = 0, 3, 6, 9dB
AUXIN
SPK+_MUX SPK-_MUX
CLK
CSB
DI
DO
Figure 3-2 ISD3900 Block Diagram, MICIN Selected

ISD3900
Publication Release Date: Dec 10, 2013
- 8 - Revision 1.5
4 PINOUT CONFIGURATION
ISD3900
NC
2
3
4
5
6
7
8
9
10
1
2
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
33
32
31
30
29
44 43 42 41 40 39 38 3736
35
34
47 46 4548
VSSD
NC
VCCD
VREG
I2S_SDO/GPIO4
I2S_WS/GPIO5
I2S_SCK/GPIO6
I2S_SDI/GPIO7
DI
CSB
NC
VCCD_PWM
NC NC
SPK-
VSSD_PWM
SPK+
VCCD_PWM
MOSI
SSB
SCLK
MISO
NC
INTB
DO
CLK
RDY/BSYB
RESET
XTALOUT
XTALIN
GPIO3
NC
GPIO2
GPIO1
NC
NC NC NC AUDOUT AUXOUT VCCA VSSA ANAOUT/MIC- ANAIN/MIC+ AUXIN NC GPIO0
Figure 4-1 ISD3900 48-Lead LQFP Pin Configuration.

ISD3900
Publication Release Date: Dec 10, 2013
- 9 - Revision 1.5
5 PIN DESCRIPTION
Pin
Number
Pin Name
I/O
Function
1
NC
This pin should be left unconnected.
2
CSB
O
Chip Select Bar of the external serial flash interface.
3
DI
I
Serial data input to external serial flash interface. Connects to data
output (DO) of external flash memory.
4
I2S_SDI/
GPIO7
I
Serial Data Input of the I2S interface (If I2S is not used, this pin should
be grounded).
Or, can be configured as a GPIO pin.
5
I2S_SCK/
GPIO6
I/O
Clock input in slave mode or clock output in master mode. This pin can
be configured as an external clock buffer if I2S is not used (If I2S is not
used, this pin should be grounded).
Or, can be configured as a GPIO pin.
6
I2S_WS/
GPIO5
I/O
Word Select (WS) input in slave mode or WS output in master mode (If
I2S is not used, this pin should be grounded).
Or, can be configured as a GPIO pin.
7
I2S_SDO/
GPIO4
O
Serial Data Output of the I2S Interface (If I2S is not used, this pin
should be left unconnected).
Or, can be configured as a GPIO pin.
8
NC
This pin should be left unconnected.
9
NC
This pin should be left unconnected.
10
VSSD
I
Digital Ground.
11
VCCD
I
Digital power supply.
12
VREG
O
A 1.8V regulator to supply the internal logic. A 0.1uF capacitor should
be connected to this pin for supply decoupling and stability.
13
MISO
O
Master-In-Slave-Out. Serial output from the ISD3900 to the host. This
pin is in tri-state when SSB=1.
14
SCLK
I
Serial Clock input to the ISD3900 from the host.
15
SSB
I
Slave Select input to the ISD3900 from the host. When SSB is low
device is selected and responds to commands on the SPI interface.
16
MOSI
I
Master-Out-Slave-In. Serial input to the ISD3900 from the host.
17
VCCD_PWM
I
Digital Power for the PWM Driver.

ISD3900
Publication Release Date: Dec 10, 2013
- 10 - Revision 1.5
Pin
Number
Pin Name
I/O
Function
18
SPK+
O
PWM driver positive output. This SPK+ output, together with SPK- pin,
provide a differential output to drive 8Ωspeaker or buzzer. During
power down this pin is in tri-state.
Or, can be configured as BTL which, together with SPK- pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
19
VSSD_PWM
I
Digital Ground for the PWM Driver.
20
SPK-
O
PWM driver negative output. This SPK- output, together with SPK+
pin, provides a differential output to drive 8Ωspeaker or buzzer.
During power down this pin is tri-state.
Or, can be configured as BTL which, together with SPK+ pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
21
VCCD_PWM
I
Digital Power for the PWM Driver.
22
NC
This pin should be left unconnected.
23
NC
This pin should be left unconnected.
24
NC
This pin should be left unconnected.
25
INTB
O
Active low interrupt request pin. This pin is an open-drain output.
26
RDY/BSYB
O
An output pin to report the status of data transfer on the SPI interface.
“High” indicates that ISD3900 is ready to accept new SPI commands
or data.
27
RESET
I
Applying power to this pin will reset the chip. (A high pulse of 50ms or
more will reset the chip.)
28
DO
O
Serial data output of the external serial flash interface. Connects to
data input (DI) of external serial flash.
29
CLK
O
Serial data CLK of the external serial flash interface.
30
GPIO3
I/O
GPIO
31
GPIO2
I/O
GPIO
32
GPIO1
I/O
GPIO
33
NC
This pin should be left unconnected.
34
NC
This pin should be left unconnected.
35
XTALOUT
O
Crystal interface output pin.