Nuvoton ISD91200 Series Product manual

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 1 - Revision 2.4
ISD ARM®Cortex®-M0 SoC
ISD91200 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD ARM® Cortex®-M0
microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 2 - Revision 2.4
Table of Contents-
TABLE OF CONTENTS-.............................................................................................................2
1GENERAL DESCRIPTION............................................................................................... 11
2FEATURES...................................................................................................................... 12
3PART INFORMATION AND PIN CONFIGURATION......................................................... 16
3.1 Pin Configuration ................................................................................................... 16
3.2 Pin Description....................................................................................................... 17
4BLOCK DIAGRAM ........................................................................................................... 22
5FUNCTIONAL DESCRIPTION.......................................................................................... 23
5.1 ARM®Cortex™-M0 core........................................................................................ 23
5.2 System Manager.................................................................................................... 25
5.2.1 Overview................................................................................................................... 25
5.2.2 System Reset............................................................................................................ 25
5.2.3 System Power Distribution......................................................................................... 26
5.2.4 System Memory Map................................................................................................. 27
5.2.5 System Manager Control Registers............................................................................ 29
5.2.6 System Timer (SysTick)............................................................................................. 53
5.2.7 Nested Vectored Interrupt Controller (NVIC)............................................................... 57
5.2.8 System Control Registers ........................................................................................ 103
5.3 Clock Controller and Power Management Unit (PMU) .......................................... 111
5.3.1 Clock Generator...................................................................................................... 111
5.3.2 System Clock & SysTick Clock................................................................................. 112
5.3.3 Peripheral Clocks .................................................................................................... 113
5.3.4 Power Management ................................................................................................ 113
5.3.5 Register Map........................................................................................................... 115
5.3.6 Register Description ................................................................................................ 116
5.4 General Purpose I/O............................................................................................ 133
5.4.1 Overview and Features............................................................................................ 133
5.4.2 GPIO I/O Modes...................................................................................................... 133
5.4.3 GPIO Control Register Map ..................................................................................... 135
5.4.4 Register Description ................................................................................................ 136
5.5 Brownout Detection and Temperature Alarm........................................................ 146
5.5.1 Brownout Register Map........................................................................................... 146
5.5.2 Brownout Register Description................................................................................. 147
5.6 I2C Serial Interface Controller (Master/Slave)....................................................... 150
5.6.1 Introduction............................................................................................................. 150
5.6.2 Modes of Operation................................................................................................. 154
5.6.3 Data Transfer Flow in Five Operating Modes............................................................ 155
5.6.4 I2C Protocol Registers............................................................................................. 161
5.6.5 Register Mapping.................................................................................................... 164
5.6.6 Register Description................................................................................................ 165
5.7 PWM Generator and Capture Timer..................................................................... 172
5.7.1 Introduction............................................................................................................. 172
5.7.2 Features.................................................................................................................. 172
5.7.3 PWM Generator Architecture ................................................................................... 174

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 3 - Revision 2.4
5.7.4 PWM-Timer Operation............................................................................................. 174
5.7.5 PWM Double Buffering, Auto-reload and One-shot Operation................................... 176
5.7.6 Modulate Duty Cycle................................................................................................ 176
5.7.7 Dead-Zone Generator.............................................................................................. 177
5.7.8 Capture Timer Operation......................................................................................... 178
5.7.9 PWM-Timer Interrupt Architecture............................................................................ 179
5.7.10 PWM-Timer Initialization Procedure ....................................................................... 179
5.7.11 PWM-Timer Stop Procedure.................................................................................. 179
5.7.12 Capture Start Procedure........................................................................................ 180
5.7.13 Register Map......................................................................................................... 181
5.7.14 Register Description .............................................................................................. 183
5.8Real Time Clock (RTC) Overview........................................................................ 200
5.8.1 RTC Features.......................................................................................................... 200
5.8.2 RTC Block Diagram................................................................................................. 201
5.8.3 RTC Function Description........................................................................................ 201
5.8.4 Register Map........................................................................................................... 204
5.8.5 Register Description ................................................................................................ 205
5.9 Serial 0 Peripheral Interface (SPI0) Controller...................................................... 218
5.9.1 Overview................................................................................................................. 218
5.9.2 Features.................................................................................................................. 218
5.9.3 SPI0 Block Diagram................................................................................................. 218
5.9.4 SPI0 Function Descriptions...................................................................................... 219
5.9.5SPI Timing Diagram................................................................................................. 229
5.9.6 SPI Configuration Examples .................................................................................... 232
5.9.7 Register Map........................................................................................................... 234
5.9.8 Register Description ................................................................................................ 235
5.10 Serial 1 Peripheral Interface (SPI1) Controller...................................................... 250
5.10.1 Overview............................................................................................................... 250
5.10.2 Features................................................................................................................ 250
5.10.3 SPI1 Block Diagram............................................................................................... 250
5.10.4 SPI1 Function Descriptions.................................................................................... 251
5.10.5 SPI Timing Diagram............................................................................................... 257
5.10.6 SPI Configuration Examples .................................................................................. 260
5.10.7 Register Map......................................................................................................... 262
5.10.8 Register Description .............................................................................................. 263
5.11 Timer Controller................................................................................................... 274
5.11.1 General Timer Controller........................................................................................ 274
5.11.2 Features................................................................................................................ 274
5.11.3 Timer Controller Block Diagram.............................................................................. 274
5.11.4 Register Map......................................................................................................... 275
5.11.5 Register Description .............................................................................................. 276
5.12 Watchdog Timer .................................................................................................. 281
5.12.1 Register Map......................................................................................................... 283
5.12.2 Register Description .............................................................................................. 284
5.13 UART Interface Controller.................................................................................... 286
5.13.1 Overview............................................................................................................... 286
5.13.2 Features of UART controller................................................................................... 288

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 4 - Revision 2.4
5.13.3 Block Diagram....................................................................................................... 289
5.13.4 IrDA Mode............................................................................................................. 291
5.13.5 LIN (Local Interconnection Network) mode............................................................. 293
5.13.6 Register Map......................................................................................................... 294
5.13.7 Register Description .............................................................................................. 295
5.14 I2S Audio PCM Controller.................................................................................... 314
5.14.1 Overview............................................................................................................... 314
5.14.2 Features................................................................................................................ 314
5.14.3 I2S Block Diagram................................................................................................. 315
5.14.4 I2S Operation........................................................................................................ 316
5.14.5 FIFO operation...................................................................................................... 317
5.14.6 Register Map......................................................................................................... 318
5.14.7 Register Description .............................................................................................. 319
5.15 PDMA Controller.................................................................................................. 330
5.15.1 Overview............................................................................................................... 330
5.15.2 Features................................................................................................................ 330
5.15.3 Block Diagram....................................................................................................... 330
5.15.4 Function Description.............................................................................................. 331
5.15.5 Register Map......................................................................................................... 332
5.15.6 Register Description .............................................................................................. 333
5.16 Volume Control.................................................................................................... 352
5.16.1 Overview and feature............................................................................................. 352
5.16.2 Volume Control Register Map ................................................................................ 352
5.16.3 Volume Control register Description ....................................................................... 353
6FLASH MEMORY CONTROLLER (FMC)....................................................................... 356
6.1 Overview ............................................................................................................. 356
6.2 Features .............................................................................................................. 356
6.3 Flash Memory Controller Block Diagram .............................................................. 357
6.4 Flash Memory Organization ................................................................................. 358
6.5 Boot Selection...................................................................................................... 358
6.6 Data Flash (DATAF)............................................................................................. 359
6.7 User Configuration (CONFIG).............................................................................. 360
6.8 In-System Programming (ISP).............................................................................. 362
6.8.1 ISP Procedure......................................................................................................... 362
6.9 Register Map ....................................................................................................... 365
6.10 Register Description............................................................................................. 366
7ANALOG SIGNAL PATH BLOCKS................................................................................. 373
7.1 Sigma- Delta Analog-to-Digital Converter (SDADC).............................................. 373
7.1.1 Functional Description............................................................................................. 373
7.1.2 Features.................................................................................................................. 373
7.1.3 Block Diagram......................................................................................................... 373
7.1.4 Operation................................................................................................................ 374
7.1.5 ADC Register Map................................................................................................... 379
7.1.6 ADC Register Description........................................................................................ 380
7.2 Bridge Sense....................................................................................................... 390

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 5 - Revision 2.4
7.2.1 Functional Description............................................................................................. 390
7.2.2 Features.................................................................................................................. 390
7.2.3 Block Diagram......................................................................................................... 390
7.2.4 Operation................................................................................................................ 391
7.2.5 Register Map........................................................................................................... 392
7.2.6 Register Description ................................................................................................ 393
7.3 Audio Class D Speaker Driver (DPWM)................................................................ 398
7.3.1 Functional Description............................................................................................. 398
7.3.2 Features.................................................................................................................. 398
7.3.3 Block Diagram......................................................................................................... 398
7.3.4 Operation................................................................................................................ 398
7.3.5 DPWM Register Map............................................................................................... 401
7.3.6 DPWM Register Description..................................................................................... 402
7.4 Analog Functional Blocks..................................................................................... 408
7.4.1 Overview................................................................................................................. 408
7.4.2 Features.................................................................................................................. 408
7.4.3 Register Map........................................................................................................... 408
7.4.4 VMID Reference Voltage Generation ....................................................................... 409
7.4.5 LDO Power Domain Control..................................................................................... 410
7.4.6 Microphone Bias (Replaced by Bridge Sense ADC).................................................. 412
7.4.7 Oscillator Frequency Measurement and Control ....................................................... 413
7.5 Automatic Level Control (ALC)............................................................................. 419
7.5.1 Overview and Features............................................................................................ 419
7.5.2 Register Map........................................................................................................... 423
7.5.3 Register Description ................................................................................................ 424
7.6 Capacitive Sensing Scan (CSCAN) and Operational Amplifiers............................ 430
7.6.1 Overview and Features............................................................................................ 430
7.6.2 Features.................................................................................................................. 430
7.6.3 Operation................................................................................................................ 430
7.6.4 Operational Amplifier............................................................................................... 430
7.6.5 Comparator............................................................................................................. 433
7.6.6 Register Map........................................................................................................... 433
7.6.7 Register Description ................................................................................................ 434
7.7 Biquad Filter (BIQ)............................................................................................... 442
7.7.1 Overview and Features............................................................................................ 442
7.7.2 Register Map........................................................................................................... 443
7.7.3 Register Description ................................................................................................ 445
7.8 Successive Approximation Analog-to-Digital Convertor (SARADC)....................... 450
7.8.1 Overview and Features............................................................................................ 450
7.8.2 Block Diagram......................................................................................................... 451
7.8.3 Function description ................................................................................................ 451
7.8.4 Register Map........................................................................................................... 457
7.8.5 Register description................................................................................................. 458
8APPLICATION DIAGRAM.............................................................................................. 468
9PACKAGE DIMENSIONS............................................................................................... 469
9.1 64L LQFP (7x7x1.4mm footprint 2.0mm).............................................................. 469
9.2 QFN 32L 4X4 mm2, Thickness: 0.8mm (Max), Pitch: 0.40mm.............................. 470

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 6 - Revision 2.4
10 ORDERING INFORMATION.......................................................................................... 471
11 REVISION HISTORY ..................................................................................................... 472
IMPORTANT NOTICE ............................................................................................................ 473

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 7 - Revision 2.4
Figure of Contents-
Figure 4-1 ISD91200 Block Diagram ..........................................................................................22
Figure 5-1 Functional Block Diagram..........................................................................................23
Figure 5-2 ISD91200 Power Distribution Diagram.......................................................................26
Figure 5-3 Clock generator block diagram ................................................................................111
Figure 5-4 System Clock Block Diagram...................................................................................112
Figure 5-5 SysTick Clock Control Block Diagram......................................................................112
Figure 5-6 Output Mode: Push-Pull Output...............................................................................133
Figure 5-7 Open-Drain Output..................................................................................................134
Figure 5-8 Quasi-bidirectional GPIO Mode ...............................................................................134
Figure 5-9 I2C Bus Timing........................................................................................................151
Figure 5-10 I2C Protocol ..........................................................................................................152
Figure 5-11 Master Transmits Data to Slave.............................................................................152
Figure 5-12 Master Reads Data from Slave..............................................................................152
Figure 5-13 START and STOP condition..................................................................................153
Figure 5-14 Bit Transfer on the I2C bus....................................................................................153
Figure 5-15 Acknowledge on the I2C bus.................................................................................154
Figure 5-16 Legend for the following four figures......................................................................155
Figure 5-17 Master Transmitter Mode.......................................................................................156
Figure 5-18 Master Receiver Mode ..........................................................................................157
Figure 5-19 Slave Transmitter Mode.........................................................................................158
Figure 5-20 Slave Receiver Mode ............................................................................................159
Figure 5-21 GC Mode...............................................................................................................160
Figure 5-22 I2C Data Shift Direction.........................................................................................162
Figure 5-23 I2C Time-out Count Block Diagram........................................................................163
Figure 5-24 PWM Generator Clock Source Control...................................................................174
Figure 5-25 PWM Generator Architecture Diagram...................................................................174
Figure 5-26 PWM Generation Timing .......................................................................................175
Figure 5-27 PWM-Timer Operation Timing...............................................................................175
Figure 5-28 PWM Double Buffering..........................................................................................176
Figure 5-29 PWM Controller Duty Cycle Modulation (PERIOD = 150).......................................176
Figure 5-30 Paired-PWM Output with Dead Zone Generation Operation...................................177
Figure 5-31 Capture Operation Timing .....................................................................................178
Figure 5-32 PWM-Timer Interrupt Architecture Diagram ...........................................................179
Figure 5-33 RTC Block Diagram...............................................................................................201
Figure 5-34 SPI0 Block Diagram ..............................................................................................218
Figure 5-35 SPI Master Mode Application Block Diagram.........................................................219

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 8 - Revision 2.4
Figure 5-36 SPI Slave Mode Application Block Diagram...........................................................219
Figure 5-37 Word Sleep Suspend Mode...................................................................................221
Figure 5-38 Byte Re-Ordering Transfer.....................................................................................221
Figure 5-39 Byte Order in Memory ...........................................................................................222
Figure 5-40 Byte Order in Memory ...........................................................................................223
Figure 5-41 2-Bit Mode System Architecture.............................................................................225
Figure 5-42 2-Bit Mode (Slave Mode).......................................................................................225
Figure 5-43 Bit Sequence of Dual Output Mode........................................................................226
Figure 5-44 Bit Sequence of Dual Input Mode ..........................................................................226
Figure 5-45 Quad Mode System Architecture...........................................................................227
Figure 5-46 Bit Sequence of Quad Output Mode ......................................................................227
Figure 5-47 FIFO Mode Block Diagram ....................................................................................228
Figure 5-48 SPI Timing in Master Mode....................................................................................230
Figure 5-49 SPI Timing in Master Mode (Alternate Phase of SPICLK) .....................................230
Figure 5-50 SPI Timing in Slave Mode.....................................................................................231
Figure 5-51 SPI Timing in Slave Mode (Alternate Phase of SPICLK) .......................................231
Figure 5-52 SPI1 Block Diagram ..............................................................................................250
Figure 5-53 SPI1 Master Mode Application Block Diagram.......................................................251
Figure 5-54 SPI1 Slave Mode Application Block Diagram.........................................................252
Figure 5-55 Two Transactions in One Transfer (Burst Mode)....................................................253
Figure 5-56 Word Sleep Suspend Mode...................................................................................253
Figure 5-57 Byte Re-Ordering Transfer.....................................................................................254
Figure 5-58 Byte Order in Memory ...........................................................................................254
Figure 5-59 Byte Order in Memory ...........................................................................................255
Figure 5-60 Byte Suspend Mode..............................................................................................255
Figure 5-61 Two Bits Transfer Mode.........................................................................................256
Figure 5-62 Variable Serial Clock Frequency............................................................................257
Figure 5-63 SPI Timing in Master Mode....................................................................................257
Figure 5-64 SPI Timing in Master Mode (Alternate Phase of SPICLK) .....................................258
Figure 5-65 SPI Timing in Slave Mode.....................................................................................258
Figure 5-66 SPI Timing in Slave Mode (Alternate Phase of SPICLK) .......................................259
Figure 5-67 Timer Controller Block Diagram.............................................................................274
Figure 5-68 Clock Source of Timer Controller...........................................................................275
Figure 5-69 Watchdog Timer Clock Control..............................................................................281
Figure 5-70 Watchdog Timer Block Diagram ............................................................................282
Figure 5-71 UART Clock Control Diagram................................................................................289
Figure 5-72 UART Block Diagram ............................................................................................289
Figure 5-73 Auto Flow Control Block Diagram ..........................................................................290

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 9 - Revision 2.4
Figure 5-74 IrDA Block Diagram...............................................................................................291
Figure 5-75 IrDA Tx/Rx Timing Diagram...................................................................................292
Figure 5-76 Structure of LIN Frame..........................................................................................293
Figure 5-77 I2S Clock Control Diagram ....................................................................................315
Figure 5-78 I2S Controller Block Diagram.................................................................................315
Figure 5-79 I2S Bus Timing Diagram (Format =0).....................................................................316
Figure 5-80 MSB Justified Timing Diagram (Format=1) ............................................................316
Figure 5-81 FIFO contents for various I2S modes.....................................................................317
Figure 5-82 PDMA Controller Block Diagram............................................................................330
Figure 6-1 Flash Memory Control Block Diagram......................................................................357
Figure 6-2 Flash Memory Organization.....................................................................................358
Figure 6-3 Flash Memory Structure..........................................................................................359
Figure 6-4 ISP Operation Timing..............................................................................................362
Figure 6-5 Boot Sequence and ISP Procedure.........................................................................363
Figure 7-1 ADC Signal Path Block Diagram..............................................................................373
Figure 7-2 SDADC Controller Interrupt.....................................................................................378
Figure 3. Block diagram of Bridge Sense..................................................................................390
Figure 4. Block diagram of instrumentation amplifier (IA). .........................................................391
Figure 7-5 DPWM Block Diagram.............................................................................................398
Figure 7-6 VMID Reference Generation....................................................................................409
Figure 7-7 LDO Power Domain ................................................................................................410
Figure 7-8 Oscillator Frequency Measurement Block Diagram..................................................413
Figure 7-10: ALC Response Graph..........................................................................................419
Figure 7-11: ALC Normal Mode Operation...............................................................................420
Figure 7-12: ALC Hold Time....................................................................................................420
Figure 7-13: ALC Limiter Mode Operations..............................................................................421
Figure 7-14: ALC Operation with Noise Gate disabled.............................................................422
Figure 7-15: ALC Operation with Noise Gate Enabled .............................................................422
Figure 7-16 Operational Amplifier 0 Switch Control...................................................................431
Figure 7-17 Operational Amplifier 1 Switch Control...................................................................432
Figure 7-18 Operational Amplifier bias Switch Control..............................................................432
Figure 7-19 Comparator Switch Control....................................................................................433
Figure 7-20 SARADC Block Diagram .......................................................................................451
Figure 7-21 SARADC Clock Generator.....................................................................................452
Figure 7-22 Single Mode Conversion Timing Diagram..............................................................453
Figure 7-23 Single-Cycle Scan on Enabled Channels Timing Diagram .....................................454
Figure 7-24 Continuous Scan on Enabled Channels Timing Diagram .......................................455
Figure 7-25 A/D Conversion Result Monitor Logics Diagram.....................................................456

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 10 - Revision 2.4
Figure 7-26 A/D Controller Interrupt..........................................................................................456
Figure 7-27 Conversion Result Mapping Diagram of Single-end Input.......................................459