Nuvoton ISD91200 Series Product manual

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 1 - Revision 2.4
ISD ARM®Cortex®-M0 SoC
ISD91200 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD ARM® Cortex®-M0
microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 2 - Revision 2.4
Table of Contents-
TABLE OF CONTENTS-.............................................................................................................2
1GENERAL DESCRIPTION............................................................................................... 11
2FEATURES...................................................................................................................... 12
3PART INFORMATION AND PIN CONFIGURATION......................................................... 16
3.1 Pin Configuration ................................................................................................... 16
3.2 Pin Description....................................................................................................... 17
4BLOCK DIAGRAM ........................................................................................................... 22
5FUNCTIONAL DESCRIPTION.......................................................................................... 23
5.1 ARM®Cortex™-M0 core........................................................................................ 23
5.2 System Manager.................................................................................................... 25
5.2.1 Overview................................................................................................................... 25
5.2.2 System Reset............................................................................................................ 25
5.2.3 System Power Distribution......................................................................................... 26
5.2.4 System Memory Map................................................................................................. 27
5.2.5 System Manager Control Registers............................................................................ 29
5.2.6 System Timer (SysTick)............................................................................................. 53
5.2.7 Nested Vectored Interrupt Controller (NVIC)............................................................... 57
5.2.8 System Control Registers ........................................................................................ 103
5.3 Clock Controller and Power Management Unit (PMU) .......................................... 111
5.3.1 Clock Generator...................................................................................................... 111
5.3.2 System Clock & SysTick Clock................................................................................. 112
5.3.3 Peripheral Clocks .................................................................................................... 113
5.3.4 Power Management ................................................................................................ 113
5.3.5 Register Map........................................................................................................... 115
5.3.6 Register Description ................................................................................................ 116
5.4 General Purpose I/O............................................................................................ 133
5.4.1 Overview and Features............................................................................................ 133
5.4.2 GPIO I/O Modes...................................................................................................... 133
5.4.3 GPIO Control Register Map ..................................................................................... 135
5.4.4 Register Description ................................................................................................ 136
5.5 Brownout Detection and Temperature Alarm........................................................ 146
5.5.1 Brownout Register Map........................................................................................... 146
5.5.2 Brownout Register Description................................................................................. 147
5.6 I2C Serial Interface Controller (Master/Slave)....................................................... 150
5.6.1 Introduction............................................................................................................. 150
5.6.2 Modes of Operation................................................................................................. 154
5.6.3 Data Transfer Flow in Five Operating Modes............................................................ 155
5.6.4 I2C Protocol Registers............................................................................................. 161
5.6.5 Register Mapping.................................................................................................... 164
5.6.6 Register Description................................................................................................ 165
5.7 PWM Generator and Capture Timer..................................................................... 172
5.7.1 Introduction............................................................................................................. 172
5.7.2 Features.................................................................................................................. 172
5.7.3 PWM Generator Architecture ................................................................................... 174

ISD91200 Series Technical Reference Manual
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- 3 - Revision 2.4
5.7.4 PWM-Timer Operation............................................................................................. 174
5.7.5 PWM Double Buffering, Auto-reload and One-shot Operation................................... 176
5.7.6 Modulate Duty Cycle................................................................................................ 176
5.7.7 Dead-Zone Generator.............................................................................................. 177
5.7.8 Capture Timer Operation......................................................................................... 178
5.7.9 PWM-Timer Interrupt Architecture............................................................................ 179
5.7.10 PWM-Timer Initialization Procedure ....................................................................... 179
5.7.11 PWM-Timer Stop Procedure.................................................................................. 179
5.7.12 Capture Start Procedure........................................................................................ 180
5.7.13 Register Map......................................................................................................... 181
5.7.14 Register Description .............................................................................................. 183
5.8Real Time Clock (RTC) Overview........................................................................ 200
5.8.1 RTC Features.......................................................................................................... 200
5.8.2 RTC Block Diagram................................................................................................. 201
5.8.3 RTC Function Description........................................................................................ 201
5.8.4 Register Map........................................................................................................... 204
5.8.5 Register Description ................................................................................................ 205
5.9 Serial 0 Peripheral Interface (SPI0) Controller...................................................... 218
5.9.1 Overview................................................................................................................. 218
5.9.2 Features.................................................................................................................. 218
5.9.3 SPI0 Block Diagram................................................................................................. 218
5.9.4 SPI0 Function Descriptions...................................................................................... 219
5.9.5SPI Timing Diagram................................................................................................. 229
5.9.6 SPI Configuration Examples .................................................................................... 232
5.9.7 Register Map........................................................................................................... 234
5.9.8 Register Description ................................................................................................ 235
5.10 Serial 1 Peripheral Interface (SPI1) Controller...................................................... 250
5.10.1 Overview............................................................................................................... 250
5.10.2 Features................................................................................................................ 250
5.10.3 SPI1 Block Diagram............................................................................................... 250
5.10.4 SPI1 Function Descriptions.................................................................................... 251
5.10.5 SPI Timing Diagram............................................................................................... 257
5.10.6 SPI Configuration Examples .................................................................................. 260
5.10.7 Register Map......................................................................................................... 262
5.10.8 Register Description .............................................................................................. 263
5.11 Timer Controller................................................................................................... 274
5.11.1 General Timer Controller........................................................................................ 274
5.11.2 Features................................................................................................................ 274
5.11.3 Timer Controller Block Diagram.............................................................................. 274
5.11.4 Register Map......................................................................................................... 275
5.11.5 Register Description .............................................................................................. 276
5.12 Watchdog Timer .................................................................................................. 281
5.12.1 Register Map......................................................................................................... 283
5.12.2 Register Description .............................................................................................. 284
5.13 UART Interface Controller.................................................................................... 286
5.13.1 Overview............................................................................................................... 286
5.13.2 Features of UART controller................................................................................... 288

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5.13.3 Block Diagram....................................................................................................... 289
5.13.4 IrDA Mode............................................................................................................. 291
5.13.5 LIN (Local Interconnection Network) mode............................................................. 293
5.13.6 Register Map......................................................................................................... 294
5.13.7 Register Description .............................................................................................. 295
5.14 I2S Audio PCM Controller.................................................................................... 314
5.14.1 Overview............................................................................................................... 314
5.14.2 Features................................................................................................................ 314
5.14.3 I2S Block Diagram................................................................................................. 315
5.14.4 I2S Operation........................................................................................................ 316
5.14.5 FIFO operation...................................................................................................... 317
5.14.6 Register Map......................................................................................................... 318
5.14.7 Register Description .............................................................................................. 319
5.15 PDMA Controller.................................................................................................. 330
5.15.1 Overview............................................................................................................... 330
5.15.2 Features................................................................................................................ 330
5.15.3 Block Diagram....................................................................................................... 330
5.15.4 Function Description.............................................................................................. 331
5.15.5 Register Map......................................................................................................... 332
5.15.6 Register Description .............................................................................................. 333
5.16 Volume Control.................................................................................................... 352
5.16.1 Overview and feature............................................................................................. 352
5.16.2 Volume Control Register Map ................................................................................ 352
5.16.3 Volume Control register Description ....................................................................... 353
6FLASH MEMORY CONTROLLER (FMC)....................................................................... 356
6.1 Overview ............................................................................................................. 356
6.2 Features .............................................................................................................. 356
6.3 Flash Memory Controller Block Diagram .............................................................. 357
6.4 Flash Memory Organization ................................................................................. 358
6.5 Boot Selection...................................................................................................... 358
6.6 Data Flash (DATAF)............................................................................................. 359
6.7 User Configuration (CONFIG).............................................................................. 360
6.8 In-System Programming (ISP).............................................................................. 362
6.8.1 ISP Procedure......................................................................................................... 362
6.9 Register Map ....................................................................................................... 365
6.10 Register Description............................................................................................. 366
7ANALOG SIGNAL PATH BLOCKS................................................................................. 373
7.1 Sigma- Delta Analog-to-Digital Converter (SDADC).............................................. 373
7.1.1 Functional Description............................................................................................. 373
7.1.2 Features.................................................................................................................. 373
7.1.3 Block Diagram......................................................................................................... 373
7.1.4 Operation................................................................................................................ 374
7.1.5 ADC Register Map................................................................................................... 379
7.1.6 ADC Register Description........................................................................................ 380
7.2 Bridge Sense....................................................................................................... 390

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7.2.1 Functional Description............................................................................................. 390
7.2.2 Features.................................................................................................................. 390
7.2.3 Block Diagram......................................................................................................... 390
7.2.4 Operation................................................................................................................ 391
7.2.5 Register Map........................................................................................................... 392
7.2.6 Register Description ................................................................................................ 393
7.3 Audio Class D Speaker Driver (DPWM)................................................................ 398
7.3.1 Functional Description............................................................................................. 398
7.3.2 Features.................................................................................................................. 398
7.3.3 Block Diagram......................................................................................................... 398
7.3.4 Operation................................................................................................................ 398
7.3.5 DPWM Register Map............................................................................................... 401
7.3.6 DPWM Register Description..................................................................................... 402
7.4 Analog Functional Blocks..................................................................................... 408
7.4.1 Overview................................................................................................................. 408
7.4.2 Features.................................................................................................................. 408
7.4.3 Register Map........................................................................................................... 408
7.4.4 VMID Reference Voltage Generation ....................................................................... 409
7.4.5 LDO Power Domain Control..................................................................................... 410
7.4.6 Microphone Bias (Replaced by Bridge Sense ADC).................................................. 412
7.4.7 Oscillator Frequency Measurement and Control ....................................................... 413
7.5 Automatic Level Control (ALC)............................................................................. 419
7.5.1 Overview and Features............................................................................................ 419
7.5.2 Register Map........................................................................................................... 423
7.5.3 Register Description ................................................................................................ 424
7.6 Capacitive Sensing Scan (CSCAN) and Operational Amplifiers............................ 430
7.6.1 Overview and Features............................................................................................ 430
7.6.2 Features.................................................................................................................. 430
7.6.3 Operation................................................................................................................ 430
7.6.4 Operational Amplifier............................................................................................... 430
7.6.5 Comparator............................................................................................................. 433
7.6.6 Register Map........................................................................................................... 433
7.6.7 Register Description ................................................................................................ 434
7.7 Biquad Filter (BIQ)............................................................................................... 442
7.7.1 Overview and Features............................................................................................ 442
7.7.2 Register Map........................................................................................................... 443
7.7.3 Register Description ................................................................................................ 445
7.8 Successive Approximation Analog-to-Digital Convertor (SARADC)....................... 450
7.8.1 Overview and Features............................................................................................ 450
7.8.2 Block Diagram......................................................................................................... 451
7.8.3 Function description ................................................................................................ 451
7.8.4 Register Map........................................................................................................... 457
7.8.5 Register description................................................................................................. 458
8APPLICATION DIAGRAM.............................................................................................. 468
9PACKAGE DIMENSIONS............................................................................................... 469
9.1 64L LQFP (7x7x1.4mm footprint 2.0mm).............................................................. 469
9.2 QFN 32L 4X4 mm2, Thickness: 0.8mm (Max), Pitch: 0.40mm.............................. 470

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- 6 - Revision 2.4
10 ORDERING INFORMATION.......................................................................................... 471
11 REVISION HISTORY ..................................................................................................... 472
IMPORTANT NOTICE ............................................................................................................ 473

ISD91200 Series Technical Reference Manual
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- 7 - Revision 2.4
Figure of Contents-
Figure 4-1 ISD91200 Block Diagram ..........................................................................................22
Figure 5-1 Functional Block Diagram..........................................................................................23
Figure 5-2 ISD91200 Power Distribution Diagram.......................................................................26
Figure 5-3 Clock generator block diagram ................................................................................111
Figure 5-4 System Clock Block Diagram...................................................................................112
Figure 5-5 SysTick Clock Control Block Diagram......................................................................112
Figure 5-6 Output Mode: Push-Pull Output...............................................................................133
Figure 5-7 Open-Drain Output..................................................................................................134
Figure 5-8 Quasi-bidirectional GPIO Mode ...............................................................................134
Figure 5-9 I2C Bus Timing........................................................................................................151
Figure 5-10 I2C Protocol ..........................................................................................................152
Figure 5-11 Master Transmits Data to Slave.............................................................................152
Figure 5-12 Master Reads Data from Slave..............................................................................152
Figure 5-13 START and STOP condition..................................................................................153
Figure 5-14 Bit Transfer on the I2C bus....................................................................................153
Figure 5-15 Acknowledge on the I2C bus.................................................................................154
Figure 5-16 Legend for the following four figures......................................................................155
Figure 5-17 Master Transmitter Mode.......................................................................................156
Figure 5-18 Master Receiver Mode ..........................................................................................157
Figure 5-19 Slave Transmitter Mode.........................................................................................158
Figure 5-20 Slave Receiver Mode ............................................................................................159
Figure 5-21 GC Mode...............................................................................................................160
Figure 5-22 I2C Data Shift Direction.........................................................................................162
Figure 5-23 I2C Time-out Count Block Diagram........................................................................163
Figure 5-24 PWM Generator Clock Source Control...................................................................174
Figure 5-25 PWM Generator Architecture Diagram...................................................................174
Figure 5-26 PWM Generation Timing .......................................................................................175
Figure 5-27 PWM-Timer Operation Timing...............................................................................175
Figure 5-28 PWM Double Buffering..........................................................................................176
Figure 5-29 PWM Controller Duty Cycle Modulation (PERIOD = 150).......................................176
Figure 5-30 Paired-PWM Output with Dead Zone Generation Operation...................................177
Figure 5-31 Capture Operation Timing .....................................................................................178
Figure 5-32 PWM-Timer Interrupt Architecture Diagram ...........................................................179
Figure 5-33 RTC Block Diagram...............................................................................................201
Figure 5-34 SPI0 Block Diagram ..............................................................................................218
Figure 5-35 SPI Master Mode Application Block Diagram.........................................................219

ISD91200 Series Technical Reference Manual
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Figure 5-36 SPI Slave Mode Application Block Diagram...........................................................219
Figure 5-37 Word Sleep Suspend Mode...................................................................................221
Figure 5-38 Byte Re-Ordering Transfer.....................................................................................221
Figure 5-39 Byte Order in Memory ...........................................................................................222
Figure 5-40 Byte Order in Memory ...........................................................................................223
Figure 5-41 2-Bit Mode System Architecture.............................................................................225
Figure 5-42 2-Bit Mode (Slave Mode).......................................................................................225
Figure 5-43 Bit Sequence of Dual Output Mode........................................................................226
Figure 5-44 Bit Sequence of Dual Input Mode ..........................................................................226
Figure 5-45 Quad Mode System Architecture...........................................................................227
Figure 5-46 Bit Sequence of Quad Output Mode ......................................................................227
Figure 5-47 FIFO Mode Block Diagram ....................................................................................228
Figure 5-48 SPI Timing in Master Mode....................................................................................230
Figure 5-49 SPI Timing in Master Mode (Alternate Phase of SPICLK) .....................................230
Figure 5-50 SPI Timing in Slave Mode.....................................................................................231
Figure 5-51 SPI Timing in Slave Mode (Alternate Phase of SPICLK) .......................................231
Figure 5-52 SPI1 Block Diagram ..............................................................................................250
Figure 5-53 SPI1 Master Mode Application Block Diagram.......................................................251
Figure 5-54 SPI1 Slave Mode Application Block Diagram.........................................................252
Figure 5-55 Two Transactions in One Transfer (Burst Mode)....................................................253
Figure 5-56 Word Sleep Suspend Mode...................................................................................253
Figure 5-57 Byte Re-Ordering Transfer.....................................................................................254
Figure 5-58 Byte Order in Memory ...........................................................................................254
Figure 5-59 Byte Order in Memory ...........................................................................................255
Figure 5-60 Byte Suspend Mode..............................................................................................255
Figure 5-61 Two Bits Transfer Mode.........................................................................................256
Figure 5-62 Variable Serial Clock Frequency............................................................................257
Figure 5-63 SPI Timing in Master Mode....................................................................................257
Figure 5-64 SPI Timing in Master Mode (Alternate Phase of SPICLK) .....................................258
Figure 5-65 SPI Timing in Slave Mode.....................................................................................258
Figure 5-66 SPI Timing in Slave Mode (Alternate Phase of SPICLK) .......................................259
Figure 5-67 Timer Controller Block Diagram.............................................................................274
Figure 5-68 Clock Source of Timer Controller...........................................................................275
Figure 5-69 Watchdog Timer Clock Control..............................................................................281
Figure 5-70 Watchdog Timer Block Diagram ............................................................................282
Figure 5-71 UART Clock Control Diagram................................................................................289
Figure 5-72 UART Block Diagram ............................................................................................289
Figure 5-73 Auto Flow Control Block Diagram ..........................................................................290

ISD91200 Series Technical Reference Manual
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Figure 5-74 IrDA Block Diagram...............................................................................................291
Figure 5-75 IrDA Tx/Rx Timing Diagram...................................................................................292
Figure 5-76 Structure of LIN Frame..........................................................................................293
Figure 5-77 I2S Clock Control Diagram ....................................................................................315
Figure 5-78 I2S Controller Block Diagram.................................................................................315
Figure 5-79 I2S Bus Timing Diagram (Format =0).....................................................................316
Figure 5-80 MSB Justified Timing Diagram (Format=1) ............................................................316
Figure 5-81 FIFO contents for various I2S modes.....................................................................317
Figure 5-82 PDMA Controller Block Diagram............................................................................330
Figure 6-1 Flash Memory Control Block Diagram......................................................................357
Figure 6-2 Flash Memory Organization.....................................................................................358
Figure 6-3 Flash Memory Structure..........................................................................................359
Figure 6-4 ISP Operation Timing..............................................................................................362
Figure 6-5 Boot Sequence and ISP Procedure.........................................................................363
Figure 7-1 ADC Signal Path Block Diagram..............................................................................373
Figure 7-2 SDADC Controller Interrupt.....................................................................................378
Figure 3. Block diagram of Bridge Sense..................................................................................390
Figure 4. Block diagram of instrumentation amplifier (IA). .........................................................391
Figure 7-5 DPWM Block Diagram.............................................................................................398
Figure 7-6 VMID Reference Generation....................................................................................409
Figure 7-7 LDO Power Domain ................................................................................................410
Figure 7-8 Oscillator Frequency Measurement Block Diagram..................................................413
Figure 7-10: ALC Response Graph..........................................................................................419
Figure 7-11: ALC Normal Mode Operation...............................................................................420
Figure 7-12: ALC Hold Time....................................................................................................420
Figure 7-13: ALC Limiter Mode Operations..............................................................................421
Figure 7-14: ALC Operation with Noise Gate disabled.............................................................422
Figure 7-15: ALC Operation with Noise Gate Enabled .............................................................422
Figure 7-16 Operational Amplifier 0 Switch Control...................................................................431
Figure 7-17 Operational Amplifier 1 Switch Control...................................................................432
Figure 7-18 Operational Amplifier bias Switch Control..............................................................432
Figure 7-19 Comparator Switch Control....................................................................................433
Figure 7-20 SARADC Block Diagram .......................................................................................451
Figure 7-21 SARADC Clock Generator.....................................................................................452
Figure 7-22 Single Mode Conversion Timing Diagram..............................................................453
Figure 7-23 Single-Cycle Scan on Enabled Channels Timing Diagram .....................................454
Figure 7-24 Continuous Scan on Enabled Channels Timing Diagram .......................................455
Figure 7-25 A/D Conversion Result Monitor Logics Diagram.....................................................456

ISD91200 Series Technical Reference Manual
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Figure 7-26 A/D Controller Interrupt..........................................................................................456
Figure 7-27 Conversion Result Mapping Diagram of Single-end Input.......................................459

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 11 - Revision 2.4
1 GENERAL DESCRIPTION
The ISD91200 series is a system-on-chip product optimized for low power, audio record and playback
with an embedded ARM® Cortex™-M0 32-bit microcontroller core.
The ISD91200 device embeds a Cortex™-M0 core running up to 50 MHz with 64K/128Kbyte of non-
volatile flash memory and 12K-byte of embedded SRAM. It also comes equipped with a variety of
peripheral devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC), Peripheral Direct
Memory Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I2C, I2S), PWM modulators,
GPIO, LDO, SDADC, SARADC, DPWM, Low Voltage Detector and Brown-out detector.
The ISD91200 comes equipped with a rich set of power saving modes including a Deep Power Down
(DPD) mode drawing less than 1µA. A micro-power 10KHz oscillator can periodically wake up the
device from deep power down to check for other events. A Standby Power Down (SPD) mode can
maintain a real time clock function at less than 5 µA.
For audio functionality the ISD91200 includes a Sigma-Delta ADC with 91dB SNR performance
coupled with a Programmable Gain Amplifier (PGA with 0-6/12dB gain) and volume control (36dB to -
108dB) in digital domain to enable direct connection of a microphone. Audio output is provided by a
Differential Class D amplifier (DPWM) that can deliver 0.5W of power to an 8Ωspeaker.
The ISD91200 provides 16 analog enabled general purpose IO pins (GPIO). These pins can be
configured to connect to an analog comparator, can be configured as analog current sources or can
be routed to the SDADC for analog conversion. They can also be used as a relaxation oscillator to
perform capacitive touch sensing.

ISD91200 Series Technical Reference Manual
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2 FEATURES
•Core
–ARM® Cortex™-M0 core running up to 50 MHz for normal speed.
–One 24-bit System tick timer for operating system support.
–Supports a variety of low power sleep and power down modes.
–Single-cycle 32-bit hardware multiplier.
–NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of priority.
–Serial Wire Debug (SWD) supports with 2 watchpoints/4 breakpoints.
•Power Management
–Wide operating voltage range from 1.8V to 5.5V.
–Power management Unit (PMU) providing four levels of power controls.
–Deep Power Down (DPD) mode with sub micro-amp leakage (<2µA).
–Wakeup from Deep Power Down via dedicated WAKEUP pin or timed operation from internal
low power 10KHz oscillator.
–Standby current in SPD mode with limited RAM (256byte SBRAM) retention and RTC
operation <5µA.
–Standby current in STOP mode with full SRAM retention <10 µA.
–Wakeup from Standby can be from any GPIO interrupt, RTC or BOD.
–Sleep mode with minimal dynamic power consumption.
–3V LDO for operation of external 3V devices such as serial flash.
•Flash EPROM Memory
–64K/128K bytes Flash EPROM for program code and data storage.
–Mini-cache to maintain near zero-wait state memory access.
–Support In-system program (ISP) and In-circuit program (ICP) application code update
–512 byte page erase for flash.
–Configurable boundary to delineate code and data flash.
–Support 2 wire In-circuit Programming (ICP) update from SWD ICE interface
•SRAM Memory
–12K bytes embedded SRAM.
•Clock Control
–High speed and low speed oscillators providing flexible selection for different applications. No
external components necessary.
–Built-in trimmable oscillator with range of 16-50MHz. Factory trimmed HIRC within 1% to
settings of 49.152MHz and 32.768MHz. User trimmable with in-built frequency measurement
block (OSCFM) using reference clock of 32kHz crystal or external reference source.
–Ultra-low power (<1uA) 10KHz oscillator for watchdog and wakeup from power-down or sleep
operation.
–External 32kHz crystal input for RTC function and low power system operation.
–External 12 MHz crystal input for precise timing operation.
•GPIO
–Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
–Schmitt trigger input selectable.
–I/O pin can be configured as interrupt source with edge/level setting.
–Supports Driver and Sink IO mode.
–Capacitive Touch: 16
–Maximal 32 GPIO

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•Audio Analog to Digital converter
–Sigma Delta ADC with configurable decimation filter and 16 bit output.
–90dB Signal-to-Noise (SNR) performance.
–Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
–Boost gain stage of 26dB, giving maximum total gain of 61dB.
–Input selectable from dedicated MIC pins or analog enabled GPIO.
–Programmable biquad filter to support multiple sample rates from 8-32kHz.
–DMA support for minimal CPU intervention.
•Differential Audio PWM Output (DPWM)
–Direct connection of speaker
–0.5W drive capability into 8Ωload.
–Configurable up-sampling to support sample rates from 8-48kHz.
–Programmable volume control from -108dB to +36dB in 0.5 dB step
–Programmable biquad filter to support multiple sample rates from 8-48kHz
–DMA support for minimal CPU intervention.
•Timers
–Two timers with 8-bit pre-scaler and 24-bit resolution.
–Counter auto reload.
•Watch Dog Timer
–Default ON/OFF by configuration setting
–Multiple clock sources
–8 selectable time out period from micro seconds to seconds (depending on clock source)
–WDT can wake up power down/sleep.
–Interrupt or reset selectable on watchdog time-out.
•RTC
–Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)
–Alarm registers (second, minute, hour, day, month, year)
–Selectable 12-hour or 24-hour mode
–Automatic leap year recognition
–Time tick and alarm interrupts.
–Device wake up function.
–Supports software compensation of crystal frequency by compensation register (FCR)
•PWM/Capture
–Four 16-bit PWM generators provide four single ended PWM outputs or two complementary
paired PWM outputs.
–The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-scaler
and Dead-Zone generator for complementary paired PWM.
–PWM interrupt synchronous to PWM period.
–16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
–Support Capture interrupt
•UART
–Up to two uart controller
–UART ports with flow control (TX, RX, CTS and RTS)
–8-byte FIFO.
–Support IrDA (SIR) and LIN function
–Programmable baud-rate generator up to 1/16 of system clock.
•SPI
–Up to two SPI controller
–SPI Clock up to 25 MHz.
–SPI data rate in Quad mode up to 100 Mbps
–Support MICROWIRE/SPI master/slave mode (SSP)

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–Full duplex synchronous serial data transfer
–Variable length of transfer data from 1 to 4 bytes
–MSB or LSB first data transfer
–2 slave/device select lines when used in master mode.
–DMA support.( 64bit (16x4) data FIFO)
–Quad/Dual SPI support.
•I2C
–Master/Slave up to 1Mbit/s
–Bidirectional data transfer between masters and slaves
–Multi-master bus (no central master).
–Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
–Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
–Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer.
–Programmable clock allowing versatile rate control.
–Supports multiple address recognition (four slave address with mask option)
–Supports wake-up by address recognition (for 1st slave address only)
•I2S
–Interface with external audio CODEC.
–Operate as either master or slave.
–Capable of handling 8, 16, 24 and 32 bit word sizes
–Mono and stereo audio data supported
–I2S and MSB justified data format supported
–Two 8 word FIFO data buffers are provided, one for transmit and one for receive
–Generates interrupt requests when buffer levels cross a programmable boundary
–Supports DMA requests, for transmit and receive
•SARADC
–12-bit SAR ADC with 700K SPS
–Up to 12-ch single-end input
–Single scan/single cycle scan/continuous scan
–Each channel with individual result register
–Scan on enabled channels
–Threshold voltage detection
–Conversion start by software programming or external input
–Supports PDMA mode
•Low Voltage Reset
–Threshold voltage typical level: 1.6V
•Brown-out detector
–Supports 16-level brown-out setting.
–Supports time-multiplex operation to minimize power consumption.
–Supports Brownout Interrupt and Reset option
•Built in Low Dropout Voltage Regulator (LDO)
–Capable of delivering 30mA load current.
–Configurable 8 output voltage selections from 1.5V – 3.3V.
–LDO output powers IO ring for GPIOA<7:0> and can supply power to external SPI Flash.
–Can be bypassed and voltage domain supplied directly from system power.
•Additional Features

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–Digital Microphone interface.
•Standby current in STOP mode with SRAM retention <=10µA at 25°C.
•Operating Temperature: -40C~85C
•Package:
–All Green package (RoHS)
LQFP 64-pin

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 16 - Revision 2.4
3 PART INFORMATION AND PIN CONFIGURATION
3.1 Pin Configuration
I91200
GPIOA<1>
GPIOA<0>
GPIOA<2>
GPIOA<3>
NC
SPKP
VCCSPK
NC
GPIOA<5>
GPIOA<7>
VSS
NC
VSSSPK
VSSSPK
NC
SPKM
NC
GPIOB<2>
VDDL/VREG
VCC
NC
GPIOB<12>
GPIOB<13>
GPIOB<5>
VMID
NC
GPIOA<10>
GPIOB<15>
GPIOB<14>
MICN
MICP
VSS
GPIOB<4>
GPIOA<4>
MICBIAS
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
17 18 19 20 21 22 23 24 25 26 27 28
64 63 62 61 60 59 58 57 56 55 54 53
GPIOB<3>
GPIOB<1>
GPIOB<0>
VCCA
VCCLDO
VLDOx
GPIOA<6>
VSS_SARADC
GPIOB<11>
GPIOB<10>
VCCSPK
GPIOA<8>
GPIOA<9>
GPIOB<8>
GPIOB<9> GPIOB<7>
GPIOB<6>
GPIOA<11>
RESETB
ICE_CLK
ICE_DAT
NC
NC
NC
NC
29 30 31 32
36
35
34
33
52 51 50 49
13
14
15
16
XI12MGPIOA<12>
XO12M/GPIOA<13>
XI32K/GPIOA<14>
XO32K/GPIOA<15>
A
Fig 3-1 I912XX LQFP 64 pin

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 17 - Revision 2.4
3.2 Pin Description
The ISD91200 is a low pin count device where many pins are configurable to alternative functions. All
General Purpose Input/Output (GPIO) pins can be configured to alternate functions as described in the
table below.
Pin No.
Pin Name Pin Type Alt CFG Description
LQFP
64
1 NC
2 NC
3 NC
4 VCCA P Analog power supply.
5 VCCLDO
P
Power supply for LDO, should be connected to VCCD.
6 VLDOx P LDO regulator output. if used, a 1μF decoupling capacitor must be
placed. If not used then tie to VCCD.
7
PA.0
I/O
0 General purpose input/output pin; Port A, bit 0
SPI0_MISO1
O
1 2nd Master In, Slave Out for SPI0 interface
SPI0_SSB1 O 2 Slave Select Bar 1 for SPI0 interface
I2S0_FS I/O 3 Frame Sync Clock for I2S interface
8 PA.1 I/O 0 General purpose input/output pin; Port A, bit 1
SPI0_MOSI0
O
1
1
st
Master Out, Slave In for SPI0 interface
I2S0_BCLK
I/O
3
Bit Clock for I2S interface
9
PA.2
I/O
0 General purpose input/output pin; Port A, bit 2
SPI0_SCLK0
I/O
1 Serial Clock for SPI 0interface
DMIC_DAT I 2 DMIC data
I2S0_SDI I 3 Serial Data Input for I2S interface
10
PA.3
I/O
0
General purpose input/output pin; Port A, bit 3
SPI0_SSB0
O
1
Slave Select Bar 0 for SPI0 interface
SARADC_TRIG
I
2 SARADC Trigger
I2S0_SDO
O
3 Serial Data Output for I2S interface
11
PA.4
I/O
0 General purpose input/output pin; Port A, bit 4
SPI0_MISO0 O 1 Master In, Slave Out channel 0 for SPI interface
UART0_TX O 2 Transmit channel of UART 0
SPI1_MOSI
O
3
Master Out, Slave In for SPI1interface
12
PA.5
I/O
0
General purpose input/output pin; Port A, bit 5
SPI0_MOSI1
O
1
2
nd
Master Out, Slave In for SPI0 interface
UART0_RX
I
2 Receive channel of UART 0
SP1_SCLK
I/O
3 Serial Clock for SPI1 interface
13 PA.6 I/O 0 General purpose input/output pin; Port A, bit 6
UART0_TX O 1 Transmit channel of UART 0
I2C0_SDA
I/O
2
Serial Data, I2C interface

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 18 - Revision 2.4
Pin No.
Pin Name Pin Type Alt CFG Description
LQFP
64
SPI1_SSB
O
3
Slave Select Bar for SPI1 interface
14
PA.7
I/O
0 General purpose input/output pin; Port A, bit 7
UART0_RX
I
1 Receive channel of UART 0
I2C0_SCL I/O 2 Serial Clock, I2C interface
SPI1_MISO I 3 Master In, Slave Out for SPI1 interface
15 VSSD P Digital Ground.
16 NC
17 NC
18 NC
19 VCCSPK P Power Supply for PWM Speaker Driver
20 SPKP O Positive Speaker Driver Output
21 VSSSPK P Ground for PWM Speaker Driver
22 VSSSPK P Ground for PWM Speaker Driver
23 SPKN O Positive Speaker Driver Output
24 VCCSPK P Power Supply for PWM Speaker Driver
25 NC
26
PA.8
I/O
0 General purpose input/output pin; Port A, bit 8
I2C0_SDA
I/O
1 Serial Data, I2C interface
UART1_TX O 2 Transmit channel of UART 1
UART0_RTS O 3 UART 0 Request to Send Output.
27
PA.9
I/O
0
General purpose input/output pin; Port A, bit 9
I2C0_SCL
I/O
1
Serial Clock, I2C interface
UART1_RX
I
2 Receive channel of UART 1
UART0_CTS
I
3 UART 0 Clear to Send Input.
28
I2C0_SCL
I/O
3 Serial Clock, I2C interface
PA.12 I/O 0 General purpose input/output pin; Port A, bit 12
PWM0CH2
O
1
PWM0CH2 Output.
XI12M
I
2
12MHz Crystal Oscillator Input. Max Voltage 1.8V
29
PA.13
I/O
0
General purpose input/output pin; Port A, bit 13
PWM0CH3
O
1 PWM0CH3 Output.
XO12M
O
2 12MHz Crystal Oscillator Output
I2C0_SCL I/O 3 Serial Clock, I2C interface
30
PA.14 I/O 0 General purpose input/output pin; Port A, bit 14
UART1_TX O 1 Transmit channel of UART 1
DMIC_CLK
IO
2
DMIC clock
XI32K
I
3
32.768kHz Crystal Oscillator Input. Max Voltage 1.8V

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 19 - Revision 2.4
Pin No.
Pin Name Pin Type Alt CFG Description
LQFP
64
31
PA.15
I/O
0
General purpose input/output pin; Port A, bit 15
UART1_RX
I
1 Receive channel of UART 1
MCLK
O
2 Master clock output for synchronizing external device
XO32K O 3 32.768kHz Crystal Oscillator Output
32 NC
33 NC
34 ICE_DAT I/O Serial Wire Debug port clock pin. Has internal weak pull-up.
35 ICE_CLK O Serial Wire Debug port data pin. Has internal weak pull-up.
36 RESETN I
External reset input. Pull this pin low to reset device to initial state. Has
internal weak pull-up.
37
PA.10
I/O
0
General purpose input/output pin; Port A, bit 10
PWM0CH0
O
1 PWM0CH0 Output.
TM0
I
2 External input to Timer 0
DPWM_P O 3 Audio PWM positive
38
PA.11 I/O 0 General purpose input/output pin; Port A, bit 11
PWM0CH1
O
1
PWM0CH1 Output.
TM1
I
2
External input to Timer 1
DPWM_N
O
3
Audio PWM negative
39 VREG P
Logic regulator output decoupling pin. A 1μF capacitor returning to
VSSD must be placed on this pin.
40 NC
41 VCCD P
Main Digital Supply for Chip. Supplies all IO except analog, Speaker
Driver
42
PB.0 I/O 0
General purpose input/output pin, analog capable; Port B, bit 0.
Triggers external interrupt 0 (EINT0/IRQ2)
SPI1_MOSI
O
1 Master Out, Slave In for SPI1interface
CS0
AI
Touch scan channel 0
A0P
AI
Operational Amplifier 0 positive input
43
PB.1 I/O 0
General purpose input/output pin, analog capable; Port B, bit 1.
Triggers external interrupt 1 (EINT1/IRQ3)
SP1_SCLK
I/O
1
Serial Clock for SPI1 interface
CS1
AI
Touch scan channel 1
A0N
AI
Operational Amplifier 0 negative input
44
PB.2 I/O 0 General purpose input/output pin, analog capable; Port B, bit 2
SPI1_SSB O 1 Slave Select Bar for SPI1 interface
CS2
AI
Touch scan channel 1
A0E
AO
Operational Amplifier 0 output
SAR11
AI
SARADC channel 11
45 PB.3
I/O
0 General purpose input/output pin, analog capable; Port B, bit 3
SPI1_MISO
I
1 Master In, Slave Out for SPI1 interface
CS3 AI Touch scan channel 3

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 20 - Revision 2.4
Pin No.
Pin Name Pin Type Alt CFG Description
LQFP
64
A1P
AI
Operational Amplifier 1 positive input
46
PB.4
I/O
0 General purpose input/output pin, analog capable; Port B, bit 4
I2S0_FS
I/O
1 Frame Sync Clock for I2S interface
CS4 AI Touch scan channel 4
A1N AO Operational Amplifier 1 negative input
47
PB.5
I/O
0
General purpose input/output pin, analog capable; Port B, bit 5
I2S0_BCLK
I/O
1
Bit Clock for I2S interface
CS5
AI
Touch scan channel 5
A1E
AO
Operational Amplifier 1 output
SAR10
AI
SARADC channel 10
48
PB.6 I/O 0 General purpose input/output pin, analog capable; Port B, bit 6
I2S0_SDI I 1 Serial Data Input for I2S interface
CS6
AI
Touch scan channel 6
CNP
AI
Comparator 1 positive input and comparator 2 negtive input
SAR8
AI
SARADC channel 8
49
PB.7
I/O
0 General purpose input/output pin, analog capable; Port B, bit 7
I2S0_SDO O 1 Serial Data Output for I2S interface
CS7 AI Touch scan channel 7
C1N AI Comparator 1 negtive input
SAR9
AI
SARADC channel 9
50
PB.8
I/O
0
General purpose input/output pin, analog capable; Port B, bit 8.
I2C0_SDA
I/O
1 Serial Data, I2C interface
I2S0_FS I/O 2 Frame Sync Clock for I2S interface
UART1_RTS O 3 UART 1 Request to Send Output.
CS8 AI Touch scan channel 8
C2P AI Comparator 2 positive input
SAR0
AI
SARADC channel 0
51
PB.9
I/O
0 General purpose input/output pin, analog capable; Port B, bit 9.
I2C0_SCL
I/O
1 Serial Clock, I2C interface
I2S0_BCLK I/O 2 Bit Clock for I2S interface
UART1_CTS I 3 UART 1 Clear to Send Input.
CS9 AI Touch scan channel 9
SAR1
AI
SARADC channel 1
52
PB.10
I/O
0
General purpose input/output pin, analog capable; Port B, bit 10
CMP1
O
1 Compare 1 Output
I2S0_SDI
I
2 Serial Data Input for I2S interface
UART1_TX O 3 Transmit channel of UART 1
CS10 AI Touch scan channel 10
SAR2
AI
SARADC channel 2
53
PB.11
I/O
0
General purpose input/output pin, analog capable; Port B, bit 11