Nuvoton ISD94124BYI Product manual

ISD94100 Series Technical Reference Manual
Sep 9, 2019 Page 1of 928 Rev1.09
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
ISD ARM®Cortex®-M4F SoC
ISD94100 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of microcontroller based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
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TABLE OF CONTENTS
1GENERAL DESCRIPTION ............................................................ 18
2FEATURES .............................................................................. 19
2.1 ISD94100 Series Features ................................................................ 19
3ABBREVIATIONS....................................................................... 26
3.1 Abbreviations................................................................................ 26
4PARTS INFORMATION LIST AND PIN CONFIGURATION..................... 28
4.1 Parts Information............................................................................ 28
4.2 Ordering Information ....................................................................... 29
4.3 Pin Configuration............................................................................ 31
4.3.1 QFN48 (6x6 mm) Pin Diagram ...................................................................31
4.3.2 LQFP64 (7x7 mm) Pin Diagram..................................................................32
4.3.3 LQFP64 (10x10 mm) Pin Diagram...............................................................33
4.4 Pin Description .............................................................................. 34
4.5 GPIO Alternate Function Summary...................................................... 43
5BLOCK DIAGRAM...................................................................... 45
5.1 ISD94100 Series Block Diagram......................................................... 45
6FUNCTIONAL DESCRIPTION........................................................ 46
6.1 ARM®Cortex®-M4 Core.................................................................... 46
6.2 System Manager............................................................................ 49
6.2.1 Overview .............................................................................................49
6.2.2 System Reset........................................................................................49
6.2.3 System Power Distribution ........................................................................53
6.2.4 Power Modes........................................................................................54
6.2.5 Power Modes Settings and Wake-up Sources.................................................56
6.2.6 Brown-out Detector and Low Voltage Reset Controller Configuration .....................61
6.2.7 System Memory Map...............................................................................62
6.2.8 SRAM Memory Organization .....................................................................63
6.2.9 HIRC Auto Trim .....................................................................................64
6.2.10 Register Map......................................................................................66
6.2.11 Register Description.............................................................................67
6.2.12 System Timer (SysTick).........................................................................98
6.2.13 Nested Vectored Interrupt Controller (NVIC) ..............................................102

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6.2.14 System Control Register......................................................................131
6.3 Clock Controller ............................................................................140
6.3.1 Overview ...........................................................................................140
6.3.2 Clock Generator...................................................................................142
6.3.3 System Clock and SysTick Clock ..............................................................143
6.3.4 Peripheral Clock ..................................................................................145
6.3.5 Power-down Mode Clock........................................................................145
6.3.6 Clock Output.......................................................................................145
6.3.7 Clock Setting Limitation..........................................................................146
6.3.8 Register Map ......................................................................................147
6.3.9 Register Description..............................................................................149
6.4 Flash Memory Controller (FMC).........................................................191
6.4.1 Overview ...........................................................................................191
6.4.2 Features............................................................................................191
6.4.3 Block Diagram.....................................................................................192
6.4.4 Functional Description ...........................................................................194
6.4.5 Register Map ......................................................................................215
6.4.6 Register Description..............................................................................217
6.5 General Purpose I/O (GPIO).............................................................240
6.5.1 Overview ...........................................................................................240
6.5.2 Features............................................................................................240
6.5.3 Block Diagram.....................................................................................240
6.5.4 Basic Configuration...............................................................................241
6.5.5 Functional Description ...........................................................................242
6.5.6 Register Map ......................................................................................246
6.5.7 Register Description..............................................................................248
6.6 PDMA Controller (PDMA) ................................................................264
6.6.1 Overview ...........................................................................................264
6.6.2 Features............................................................................................264
6.6.3 Block Diagram.....................................................................................264
6.6.4 Basic Configuration...............................................................................265
6.6.5 Functional Description ...........................................................................265
6.6.6 Register Map ......................................................................................273
6.6.7 Register Description..............................................................................278
6.7 Timer Controller (TMR) ...................................................................338

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6.7.1 Overview ...........................................................................................338
6.7.2 Features............................................................................................338
6.7.3 Block Diagram.....................................................................................340
6.7.4 Basic Configuration...............................................................................344
6.7.5 Timer Functional Description ...................................................................345
6.7.6 PWM Functional Description....................................................................350
6.7.7 Register Map ......................................................................................363
6.7.8 Register Description..............................................................................368
6.8 PWM Generator and Capture Timer (PWM) ..........................................402
6.8.1 Overview ...........................................................................................402
6.8.2 Features............................................................................................402
6.8.3 Block Diagram.....................................................................................404
6.8.4 Basic Configuration...............................................................................407
6.8.5 Functional Description ...........................................................................408
6.8.6 Register Map ......................................................................................439
6.8.7 Register Description..............................................................................443
6.9 Watchdog Timer (WDT)...................................................................525
6.9.1 Overview ...........................................................................................525
6.9.2 Features............................................................................................525
6.9.3 Block Diagram.....................................................................................525
6.9.4 Basic Configuration...............................................................................525
6.9.5 Functional Description ...........................................................................526
6.9.6 Register Map ......................................................................................529
6.9.7 Register Description..............................................................................530
6.10 Window Watchdog Timer (WWDT) .....................................................533
6.10.1 Overview ........................................................................................533
6.10.2 Features .........................................................................................533
6.10.3 Block Diagram ..................................................................................533
6.10.4 Basic Configuration............................................................................534
6.10.5 Functional Description.........................................................................534
6.10.6 Register Map....................................................................................538
6.10.7 Register Description...........................................................................539
6.11 Real Time Clock (RTC) ...................................................................544
6.11.1 Overview ........................................................................................544
6.11.2 Features .........................................................................................544

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6.11.3 Block Diagram ..................................................................................545
6.11.4 Basic Configuration............................................................................545
6.11.5 Functional Description.........................................................................545
6.11.6 Register Map....................................................................................549
6.11.7 Register Description...........................................................................550
6.12 UART Interface Controller (UART)......................................................566
6.12.1 Overview ........................................................................................566
6.12.2 Features .........................................................................................566
6.12.3 Block Diagram ..................................................................................567
6.12.4 Basic Configuration............................................................................570
6.12.5 Functional Description.........................................................................571
6.12.6 Register Map....................................................................................588
6.12.7 Register Description...........................................................................589
6.13 I2C Serial Interface Controller (I2C) .....................................................617
6.13.1 Overview ........................................................................................617
6.13.2 Features .........................................................................................617
6.13.3 Block Diagram ..................................................................................617
6.13.4 Basic Configuration............................................................................618
6.13.5 Functional Description.........................................................................619
6.13.6 Register Map....................................................................................650
6.13.7 Register Description...........................................................................652
6.14 Serial Peripheral Interface (SPI).........................................................674
6.14.1 Overview ........................................................................................674
6.14.2 Features .........................................................................................674
6.14.3 Block Diagram ..................................................................................676
6.14.4 Basic Configuration............................................................................678
6.14.5 Functional Description.........................................................................680
6.14.6 Timing Diagram ................................................................................704
6.14.7 Programming Examples ......................................................................706
6.14.8 Register Map....................................................................................708
6.14.9 Register Description...........................................................................710
6.15 CRC Controller (CRC) ....................................................................746
6.15.1 Overview ........................................................................................746
6.15.2 Features .........................................................................................746
6.15.3 Block Diagram ..................................................................................747

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6.15.4 Basic Configuration............................................................................747
6.15.5 Functional Description.........................................................................747
6.15.6 Register Map....................................................................................749
6.15.7 Register Description...........................................................................750
6.16 Enhanced 12-bit Analog-to-Digital Converter (EADC)...............................755
6.16.1 Overview ........................................................................................755
6.16.2 Features .........................................................................................755
6.16.3 Block Diagram..................................................................................756
6.16.4 Basic Configuration............................................................................756
6.16.5 Functional Description.........................................................................757
6.16.6 Register Map....................................................................................771
6.16.7 Register Description...........................................................................774
6.17 I2S Controller (I2S) .........................................................................801
6.17.1 Overview ........................................................................................801
6.17.2 Features .........................................................................................801
6.17.3 Block Diagram ..................................................................................802
6.17.4 Basic Configuration............................................................................802
6.17.5 Functional Description.........................................................................803
6.17.6 Register Map....................................................................................814
6.17.7 Register Description...........................................................................815
6.18 USB 1.1 Device Controller (USBD).....................................................833
6.18.1 Overview ........................................................................................833
6.18.2 Features .........................................................................................833
6.18.3 Block Diagram ..................................................................................834
6.18.4 Basic Configuration............................................................................834
6.18.5 Functional Description.........................................................................835
6.18.6 Register Map....................................................................................839
6.18.7 Register Description...........................................................................842
6.19 Digital Microphone Inputs (DMIC).......................................................866
6.19.1 Overview ........................................................................................866
6.19.2 Features .........................................................................................866
6.19.3 Block Diagram..................................................................................866
6.19.4 Basic Configuration............................................................................866
6.19.5 Functional Description.........................................................................867
6.19.6 Register Map....................................................................................871

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6.19.7 Register Description...........................................................................872
6.20 Voice Active Detection (VAD)............................................................879
6.20.1 Overview ........................................................................................879
6.20.2 Features .........................................................................................879
6.20.3 Block Diagram ..................................................................................879
6.20.4 Basic Configuration............................................................................879
6.20.5 Functional Description.........................................................................879
6.20.6 Register Map....................................................................................885
6.20.7 Register Description...........................................................................886
6.21 Audio DPWM Modulator (DPWM).......................................................897
6.21.1 Overview ........................................................................................897
6.21.2 Features .........................................................................................897
6.21.3 Block Diagram ..................................................................................897
6.21.4 Basic Configuration............................................................................897
6.21.5 Functional Description.........................................................................898
6.21.6 Register Map....................................................................................905
6.21.7 Register Description...........................................................................910
7ELECTRICAL CHARACTERISTICS................................................922
8APPLICATION CIRCUIT..............................................................923
9PACKAGE DIMENSIONS ............................................................924
9.1 QFN 48L (6x6x0.8 mm3 Pitch 0.4 mm) .................................................924
9.2 LQFP 64L (7x7x1.4 mm footprint 2.0 mm).............................................925
9.3 LQFP 64L (10x10x1.4 mm footprint 2.0 mm) .........................................926
10 REVISION HISTORY..................................................................927

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List of Figure
Figure 4.2-1 Ordering Information Scheme ................................................................................... 29
Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram.................................................................................. 31
Figure 4.3-2 LQFP64 (7x7 mm) Pin Diagram ................................................................................ 32
Figure 4.3-3 LQFP64 (10x10 mm) Pin Diagram ............................................................................ 33
Figure 5.1-1 ISD94100 Series Block Diagram............................................................................... 45
Figure 6.1-1 Cortex®-M4 Block Diagram........................................................................................ 46
Figure 6.2-1 System Reset Sources.............................................................................................. 50
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 51
Figure 6.2-3 Brown-out Detector (BOD) Waveform....................................................................... 52
Figure 6.2-4 ISD94100 Series Power Distribution Diagram .......................................................... 54
Figure 6.2-5 ISD94100 Series Power Mode State Machine.......................................................... 57
Figure 6.2-6 SRAM Block Diagram................................................................................................ 63
Figure 6.2-7 SRAM Memory Organization..................................................................................... 64
Figure 6.3-1 Clock Generator Global View Diagram.................................................................... 141
Figure 6.3-2 Clock Generator Block Diagram.............................................................................. 142
Figure 6.3-3 System Clock Block Diagram .................................................................................. 143
Figure 6.3-4 HXT Stop Protect Procedure................................................................................... 144
Figure 6.3-5 SysTick Clock Control Block Diagram..................................................................... 144
Figure 6.3-6 Clock Output Block Diagram ................................................................................... 145
Figure 6.4-1 Flash Memory Controller Block Diagram................................................................. 192
Figure 6.4-2 Memory Organization .............................................................................................. 194
Figure 6.4-3 Data Flash Shared with 512 KB APRM example .................................................... 194
Figure 6.4-4 Boot from LDROM with IAP support........................................................................ 196
Figure 6.4-5 Boot from APROM with IAP support........................................................................ 197
Figure 6.4-6 Boot from LDROM without IAP support................................................................... 198
Figure 6.4-7 Boot from APROM without IAP support................................................................... 198
Figure 6.4-8 ISP Procedure Example .......................................................................................... 201
Figure 6.4-9 flash 32-bit write procedure ..................................................................................... 203
Figure 6.4-10 Flash 64-bit write procedure.................................................................................. 204
Figure 6.4-11 Timeline comparison for write operations.............................................................. 205
Figure 6.4-12 Firmware in SRAM for Multi-word Programming................................................... 205
Figure 6.4-13 Multi-word programming flow chart ....................................................................... 207
Figure 6.4-14 Fast Flash Programming Verification Flow............................................................ 208
Figure 6.4-15 Verification Flow .................................................................................................... 209
Figure 6.4-16 Flash CRC32 Checksum Calculation.................................................................... 209

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Figure 6.4-17 Flash access cycle auto-tuning flow...................................................................... 213
Figure 6.5-1 GPIO Controller Block Diagram............................................................................... 241
Figure 6.5-2 Push-Pull Output...................................................................................................... 242
Figure 6.5-3 Open-Drain Output .................................................................................................. 243
Figure 6.5-4 Quasi-Bidirectional I/O Mode................................................................................... 243
Figure 6.5-5 GPIO Rising Edge Trigger Interrupt ........................................................................ 244
Figure 6.5-6 GPIO Falling Edge Trigger Interrupt........................................................................ 245
Figure 6.6-1 PDMA Controller Block Diagram ............................................................................. 264
Figure 6.6-2 Descriptor Table Entry Structure ............................................................................. 265
Figure 6.6-3 Basic Mode Finite State Machine............................................................................ 267
Figure 6.6-4 Descriptor Table Link List Structure ........................................................................ 268
Figure 6.6-5 Scatter-Gather Mode Finite State Machine............................................................. 268
Figure 6.6-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode ............ 270
Figure 6.6-7 Example of PDMA Channel 0 Time-out Counter Operation.................................... 271
Figure 6.6-8 Stride Function Block Transfer................................................................................ 271
Figure 6.7-1 Timer Controller Block Diagram .............................................................................. 340
Figure 6.7-2 Clock Source of Timer Controller ............................................................................ 341
Figure 6.7-3 PWM Generator Overview Block Diagram.............................................................. 342
Figure 6.7-4 PWM System Clock Source Control........................................................................ 342
Figure 6.7-5 PWM Counter Clock Source Control....................................................................... 343
Figure 6.7-6 PWM Independent Mode Architecture Diagram...................................................... 343
Figure 6.7-7 PWM Complementary Mode Architecture Diagram ................................................ 344
Figure 6.7-8 Continuous Counting Mode..................................................................................... 347
Figure 6.7-9 External Capture Mode............................................................................................ 348
Figure 6.7-10 External Reset Counter Mode ......................................................................... 348
Figure 6.7-11 Internal Timer Trigger............................................................................................ 349
Figure 6.7-12 Inter-Timer Trigger Capture Timing....................................................................... 350
Figure 6.7-13 PWM Prescale Waveform in Up Count Type ........................................................ 351
Figure 6.7-14 PWM Up Count Type............................................................................................. 351
Figure 6.7-15 PWM Down Count Type........................................................................................ 352
Figure 6.7-16 PWM Up-Down Count Type .................................................................................. 352
Figure 6.7-17 PWM Comparator Events in Up-Down Count Type.............................................. 353
Figure 6.7-18 Period Loading Mode with Up Count Type............................................................ 354
Figure 6.7-19 Immediately Loading Mode with Up Count Type................................................... 355
Figure 6.7-20 PWM Pulse Generation in Up-Down Count Type ................................................. 355
Figure 6.7-21 PWM Pulse Generation in Up Count Type............................................................ 356
Figure 6.7-22 PWM Pulse Generation in Down Count Type ....................................................... 356

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Figure 6.7-23 PWM 0% to 100% Duty Cycle in Up Count Type and Up-Down Count Type....... 357
Figure 6.7-24 PWM Independent Mode Output Waveform ......................................................... 358
Figure 6.7-25 PWM Complementary Mode Output Waveform.................................................... 358
Figure 6.7-26 PWMx_CH0 Output Control in Independent Mode ............................................... 358
Figure 6.7-27 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode.............. 359
Figure 6.7-28 Dead-Time Insertion.............................................................................................. 359
Figure 6.7-29 PWM Output Mask Control Waveform .................................................................. 360
Figure 6.7-30 PWMx_CH0 and PWMx_CH1 Polarity Control with Dead-Time Insertion............ 361
Figure 6.7-31 PWM Interrupt Architecture Diagram..................................................................... 362
Figure 6.7-32 PWM Trigger ADC Block Diagram ........................................................................ 362
Figure 6.8-1 PWM Generator Overview Block Diagram.............................................................. 404
Figure 6.8-2 PWM System Clock Source Control........................................................................ 404
Figure 6.8-3 PWM Clock Source Control..................................................................................... 405
Figure 6.8-4 PWM Independent Mode Architecture Diagram...................................................... 406
Figure 6.8-5 PWM Complementary Mode Architecture Diagram ................................................ 407
Figure 6.8-6 PWM0_CH0 Prescaler Waveform in Up Counter Type........................................... 408
Figure 6.8-7 PWM0 Counter Waveform when set clear counter ................................................. 409
Figure 6.8-8 PWM Up Counter Type............................................................................................ 409
Figure 6.8-9 PWM Down Counter Type....................................................................................... 410
Figure 6.8-10 PWM Up-Down Counter Type............................................................................... 411
Figure 6.8-11 PWM Compared point Events in Up-Down Counter Type .................................... 412
Figure 6.8-12 PWM Double Buffering Illustration......................................................................... 413
Figure 6.8-13 Period Loading in Up-Count Mode........................................................................ 414
Figure 6.8-14 Immediately Loading in Up-Count Mode............................................................... 415
Figure 6.8-15 Window Loading in Up-Count Mode...................................................................... 416
Figure 6.8-16 Center Loading in Up-Down-Count Mode ............................................................. 417
Figure 6.8-17 PWM One-shot Mode Output Waveform............................................................... 418
Figure 6.8-18 PWM Pulse Generation......................................................................................... 419
Figure 6.8-19 PWM 0% to 100% Pulse Generation..................................................................... 419
Figure 6.8-20 PWM Independent Mode Waveform ..................................................................... 421
Figure 6.8-21 PWM Complementary Mode Waveform................................................................ 421
Figure 6.8-22 PWM Group Function Waveform........................................................................... 422
Figure 6.8-23 PWM SYNC_IN Noise Filter Block Diagram ......................................................... 423
Figure 6.8-24 PWM Counter Synchronous Function Block Diagram........................................... 424
Figure 6.8-25 PWM Synchronous Function with Synchronize source from SYNC_IN Signal..... 425
Figure 6.8-26 PWM0_CH0 Output Control in Independent Mode............................................... 425
Figure 6.8-27 PWM0_CH0 and PWM0_CH1 Output Control in Complementary Mode.............. 426

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Figure 6.8-28 Dead-Time Insertion.............................................................................................. 427
Figure 6.8-29 Illustration of Mask Control Waveform................................................................... 427
Figure 6.8-30 Brake Noise Filter Block Diagram.......................................................................... 428
Figure 6.8-31 Brake Block Diagram for PWM0_CH0 and PWM0_CH1 Pair............................... 429
Figure 6.8-32 Edge Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair ........................ 430
Figure 6.8-33 Level Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair........................ 430
Figure 6.8-34 Brake Source Block Diagram ................................................................................ 431
Figure 6.8-35 Brake System Fail Block Diagram......................................................................... 431
Figure 6.8-36 Initial State and Polarity Control with Rising Edge Dead-Time Insertion .............. 432
Figure 6.8-37 PWM0_CH0 and PWM0_CH1 Pair Interrupt Architecture Diagram...................... 433
Figure 6.8-38 PWM0_CH0 and PWM0_CH1 Pair Trigger EADC Block Diagram....................... 434
Figure 6.8-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform...................... 434
Figure 6.8-40 PWM0_CH0 Capture Block Diagram .................................................................... 435
Figure 6.8-41 Capture Operation Waveform................................................................................ 436
Figure 6.8-42 Capture PDMA Operation Waveform of Channel 0............................................... 438
Figure 6.9-1 Watchdog Timer Block Diagram.............................................................................. 525
Figure 6.9-2 Watchdog Timer Clock Control................................................................................ 526
Figure 6.9-3 Watchdog Timer Time-out Interval and Reset Period Timing ................................. 527
Figure 6.10-1 WWDT Block Diagram........................................................................................... 533
Figure 6.10-2 WWDT Clock Control............................................................................................. 534
Figure 6.10-3 WWDT Reset and Reload Behavior...................................................................... 535
Figure 6.10-4 WWDT Reload Counter When CNTDAT > CMPDAT ........................................... 536
Figure 6.10-5 WWDT Reload Counter When WWDT_CNT < WINCMP..................................... 537
Figure 6.10-6 WWDT Interrupt and Reset Signals ...................................................................... 537
Figure 6.11-1 RTC Block Diagram............................................................................................... 545
Figure 6.12-1 UART Clock Control Diagram................................................................................ 567
Figure 6.12-2 UART Block Diagram............................................................................................. 568
Figure 6.12-3 Auto-Baud Rate Measurement.............................................................................. 574
Figure 6.12-4 Transmit Delay Time Operation............................................................................. 575
Figure 6.12-5 UART nCTS Wake-up Case1................................................................................ 576
Figure 6.12-6 UART nCTS Wake-up Case2................................................................................ 576
Figure 6.12-7 UART Data Wake-up............................................................................................. 577
Figure 6.12-8 UART RX FIFO reached threshold wake-up......................................................... 577
Figure 6.12-9 UART RS-485 AAD Mode Address Match Wake-up............................................. 578
Figure 6.12-10 UART RX FIFO threshold time-out wake-up....................................................... 578
Figure 6.12-11 Auto-Flow Control Block Diagram ....................................................................... 582
Figure 6.12-12 UART nCTS Auto-Flow Control Enabled ............................................................ 583

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Figure 6.12-13 UART nRTS Auto-Flow Control Enabled ............................................................ 583
Figure 6.12-14 UART nRTS Auto-Flow with Software Control.................................................... 584
Figure 6.12-15 RS-485 nRTS Driving Level in Auto Direction Mode........................................... 586
Figure 6.12-16 RS-485 nRTS Driving Level with Software Control............................................. 586
Figure 6.12-17 Structure of RS-485 Frame ................................................................................. 587
Figure 6.13-1 I2C Controller Block Diagram................................................................................. 618
Figure 6.13-2 I2C Bus Timing...................................................................................................... 620
Figure 6.13-3 I2C Protocol............................................................................................................ 620
Figure 6.13-4 Bit Transfer on the I2C Bus.................................................................................... 621
Figure 6.13-5 Acknowledge on the I2C Bus................................................................................. 621
Figure 6.13-6 Bit Transfer on the I2C Bus.................................................................................... 622
Figure 6.13-7 Acknowledge on the I2C Bus................................................................................. 623
Figure 6.13-8 Master Transmits Data to Slave by 7-bit ............................................................... 623
Figure 6.13-9 Master Reads Data from Slave by 7-bit................................................................. 623
Figure 6.13-10 Master Transmits Data to Slave by 10-bit ........................................................... 624
Figure 6.13-11 Master Reads Data from Slave by 10-bit ............................................................ 624
Figure 6.13-12 Control I2C Bus according to the current I2C Status............................................ 625
Figure 6.13-13 Master Transmitter Mode Control Flow............................................................... 627
Figure 6.13-14 Master Receiver Mode Control Flow................................................................... 629
Figure 6.13-15 Slave Mode Control Flow .................................................................................... 631
Figure 6.13-16 GC Mode ............................................................................................................. 634
Figure 6.13-17 Arbitration Lost..................................................................................................... 636
Figure 6.13-18 Bus Management Packet Protocol Diagram Element Key.................................. 638
Figure 6.13-19 7-Bit Addressable Device to Host Communication.............................................. 639
Figure 6.13-20 7-Bit Addressable Device Responds to an ARA ................................................ 639
Figure 6.13-21 Bus Management ALERT function...................................................................... 640
Figure 6.13-22 Bus Management Time Out Timing..................................................................... 641
Figure 6.13-23 Bus Clock Low Time Out Timing......................................................................... 641
Figure 6.13-24 Setup Time Wrong Adjustment............................................................................ 643
Figure 6.13-25 Hold Time Wrong Adjustment.............................................................................. 643
Figure 6.13-26 I2C Data Shifting Direction................................................................................... 644
Figure 6.13-27 I2C Time-out Count Block Diagram ..................................................................... 646
Figure 6.13-28 I2C Wake-Up Related Signals Waveform............................................................ 647
Figure 6.13-29 EEPROM Random Read..................................................................................... 648
Figure 6.13-30 Protocol of EEPROM Random Read................................................................... 649
Figure 6.14-1 SPI Block Diagram (SPI0) ..................................................................................... 676
Figure 6.14-2 SPI Block Diagram (SPI1/2) .................................................................................. 676

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Table 6.14-3 SPI/I2S Interface Controller Pin Description (SPI1~SPI2) ..................................... 680
Figure 6.14-4 SPI Peripheral Clock.............................................................................................. 680
Figure 6.14-5 SPI0 Full-Duplex Master Mode Application Block Diagram .................................. 681
Figure 6.14-6 SPI0 Full-Duplex Slave Mode Application Block Diagram .................................... 681
Figure 6.14-7 SPI1 ~ SPI2 Full-Duplex Master Mode Application Block Diagram ...................... 682
Figure 6.14-8 SPI1 ~ SPI2 Full-Duplex Slave Mode Application Block Diagram ........................ 682
Figure 6.14-9 32-Bit in One Transaction...................................................................................... 683
Figure 6.14-10 Automatic Slave Selection (SSACTPOL = 0, SUSPITV > 0x2)........................... 684
Figure 6.14-11 Automatic Slave Selection (SSACTPOL = 0, SUSPITV < 0x3)........................... 685
Figure 6.14-12 Byte Reorder Function......................................................................................... 686
Figure 6.14-13 Timing Waveform for Byte Suspend.................................................................... 686
Figure 6.14-14 SPI Half-Duplex Master Mode Application Block Diagram.................................. 687
Figure 6.14-15 SPI Half-Duplex Slave Mode Application Block Diagram.................................... 687
Figure 6.14-16 Two-Bit Transfer Mode System Architecture....................................................... 689
Figure 6.14-17 Two-Bit Transfer Mode Timing (Master Mode).................................................... 689
Figure 6.14-18 Bit Sequence of Dual Output Mode..................................................................... 690
Figure 6.14-19 Bit Sequence of Dual Input Mode........................................................................ 690
Figure 6.14-20 Bit Sequence of Quad Output Mode.................................................................... 691
Figure 6.14-21 Bit Sequence of Quad Input Mode ...................................................................... 692
Figure 6.14-22 FIFO Threshold Comparator ............................................................................... 693
Figure 6.14-23 Transmit FIFO Buffer Example............................................................................ 694
Figure 6.14-24 Receive FIFO Buffer Example............................................................................. 695
Figure 6.14-25 TX Underflow Event and Slave Under Run Event............................................... 696
Figure 6.14-26 Two-Bit Transfer Mode FIFO Buffer Example (SPI0 Only) ................................. 696
Figure 6.14-27 TX Underflow Event (SPI0 Slave 3-Wire Mode Enabled) ................................... 696
Figure 6.14-28 Slave Mode Bit Count Error................................................................................. 697
Figure 6.14-29 Slave Time-out Event (for SPI0).......................................................................... 697
Figure 6.14-30 I2S Data Format Timing Diagram......................................................................... 700
Figure 6.14-31 MSB Justified Data Format Timing Diagram....................................................... 701
Figure 6.14-32 PCM Mode A Timing Diagram............................................................................. 701
Figure 6.14-33 PCM Mode B Timing Diagram............................................................................. 701
Figure 6.14-34 FIFO Contents for Various I2S Modes................................................................. 704
Figure 6.14-35 SPI Timing in Master Mode ................................................................................. 704
Figure 6.14-36 SPI Timing in Master Mode (Alternate Phase of SPIx_CLK) .............................. 705
Figure 6.14-37 SPI Timing in Slave Mode ................................................................................... 705
Figure 6.14-38 SPI Timing in Slave Mode (Alternate Phase of SPIx_CLK) ................................ 705
Figure 6.15-1 CRC Generator Block Diagram............................................................................. 747

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Figure 6.15-2 CHECKSUM Bit Order Reverse Functional Block................................................. 748
Figure 6.15-3 Write Data Bit Order Reverse Functional Block .................................................... 748
Figure 6.16-1 ADC Converter Block Diagram.............................................................................. 756
Figure 6.16-2 Sample Module 0~3 Block Diagram...................................................................... 758
Figure 6.16-3 Sample Module 4~12 Block Diagram................................................................... 759
Figure 6.16-4 EADC Clock Control.............................................................................................. 760
Figure 6.16-5 Example ADC Conversion Timing Diagram, n=0~12............................................ 760
Figure 6.16-6 Sample module Conversion Priority Arbitrator Diagram........................................ 761
Figure 6.16-7 Specific Sample Module ADC EOC Signal for ADINT0~3 Interrupt...................... 763
Figure 6.16-8 PWM-triggered ADC Start Conversion.................................................................. 764
Figure 6.16-9 External triggered ADC Start Conversion.............................................................. 764
Figure 6.16-10 Conversion Start Delay Timing Diagram............................................................. 765
Figure 6.16-11 EADC0_ST De-bounce Timing Diagram............................................................. 766
Figure 6.16-12 ADC Extend Sampling Timing Diagram .............................................................. 767
Figure 6.16-13 ADC Conversion Result Monitor Logics Diagram ............................................... 767
Figure 6.16-14 ADC Controller Interrupts .................................................................................... 768
Figure 6.16-15 ADC start up sequence with calibration............................................................... 769
Figure 6.16-16 Model of the sampling network............................................................................ 770
Figure 6.17-1 I2S Controller Block Diagram................................................................................. 802
Figure 6.17-2 I2S Clock Control Diagram..................................................................................... 803
Figure 6.17-3 Master mode Interface Block Diagram.................................................................. 803
Figure 6.17-4 Slave mode Interface Block Diagram.................................................................... 804
Figure 6.17-5 I2S Channel Width and Data Width (CHWIDTH≦DATWIDTH).............................. 804
Figure 6.17-6 I2S Channel Width and Data Width (CHWIDTH > DATWIDTH)............................ 804
Figure 6.17-7 I2S Data Format Timing Diagram (FORMAT = 0x0 ; CHWIDTH≦DATWIDTH) .... 805
Figure 6.17-8 MSB Justified Data Format (FORMAT = 0x1 ; CHWIDTH > DATWIDTH)............ 805
Figure 6.17-9 LSB Justified Data Format (FORMAT = 0x2 ; CHWIDTH > DATWIDTH)............. 805
Figure 6.17-10 Standard PCM Audio Timing Diagram (FORMAT = 0x4 ; CHWIDTH≦DATWIDTH)
.............................................................................................................................................. 806
Figure 6.17-11 PCM with MSB Justified Data Format (FORMAT = 0x5 ; CHWIDTH > DATWIDTH)
.............................................................................................................................................. 806
Figure 6.17-12 PCM with LSB Justified Data Format (FORMAT = 0x6 ; CHWIDTH > DATWIDTH)
.............................................................................................................................................. 806
Figure 6.17-13 TDM 6-channel audio format with 24-bit data in 32-bit channel block (PCM standard
data format; FORMAT=0x4) ................................................................................................. 807
Figure 6.17-14 TDM 6-channel audio format with 24-bit data in 32-bit channel block (PCM with MSB
justified; FORMAT=0x5)........................................................................................................ 807

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Figure 6.17-15 TDM 6-channel audio format with 24-bit data in 32-bit channel block (PCM with LSB
justified; FORMAT=0x6)........................................................................................................ 807
Figure 6.17-16 I2S Interrupts........................................................................................................ 809
Figure 6.17-17 FIFO Contents for Various 2-channel Audio Modes............................................ 810
Figure 6.17-18 FIFO Contents for Various 4-channel Audio Modes............................................ 811
Figure 6.17-19 FIFO Contents for Various 6-channel Audio Modes (Part-1) .............................. 812
Figure 6.17-20 FIFO Contents for Various 6-channel Audio Modes (Part-2) .............................. 813
Figure 6.18-1 USB Block Diagram............................................................................................... 834
Figure 6.18-2 NEVWK Interrupt Operation Flow.......................................................................... 836
Figure 6.18-3 Endpoint SRAM Structure ..................................................................................... 837
Figure 6.18-4 Setup Transaction Followed by Data IN Transaction............................................ 837
Figure 6.18-5 Data Out Transfer.................................................................................................. 838
Figure 6.19-1 DMIC Block Diagram............................................................................................. 866
Figure 6.19-2 DMIC Clock Control Diagram ................................................................................ 867
Figure 6.19-3 Typical connection to two digital microphones sharing a common data line......... 869
Figure 6.19-4 Digital Microphone Interface Timing Diagram ....................................................... 869
Figure 6.19-5 DMIC FIFO Contents for Various Settings ............................................................ 870
Figure 6.20-1 VAD Block Diagram............................................................................................... 879
Figure 6.20-2 VAD Clock Control Diagram.................................................................................. 880
Figure 6.20-3 VAD Data Diagram................................................................................................ 881
Figure 6.20-4 VAD Decision Tree................................................................................................ 882
Figure 6.21-1 DPWM Block Diagram........................................................................................... 897
Figure 6.21-2 DPWM Clock Control Diagram.............................................................................. 899
Figure 6.21-3 Splitter Frequency Response and Channel Distribution........................................ 902
Figure 6.21-4 Audio DPWM FIFO Contents for Various Data Width........................................... 903

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List of Tables
Table 3.1-1 List of Abbreviations.................................................................................................... 27
Table 4.1-1 Devices Features and Peripheral Counts................................................................... 28
Table 4.2-1 Devices Features Summary ....................................................................................... 30
Table 4.4-1 Pin Description............................................................................................................ 42
Table 4.5-1 GPIO Alternate Function Summary............................................................................ 44
Table 6.2.2-1 Reset Value of Registers......................................................................................... 51
Table 6.2.2-2 Reset Flag Table...................................................................................................... 53
Table 6.2.5-1 Power Mode Table................................................................................................... 56
Table 6.2.5-2 Power Mode Difference Table................................................................................. 57
Table 6.2.5-3 Power Mode Difference Table................................................................................. 57
Table 6.2.5-4 Clocks in Power Modes ........................................................................................... 58
Table 6.2.5-5 Re-Entering Power-down Mode Condition .............................................................. 60
Table 6.2.6-1 Brown-out Detector and Low Voltage Reset Controller Effect Table ...................... 61
Table 6.2.7-1 Address Space Assignments for On-Chip Controllers............................................. 63
Table 6.2.13-1 Exception Model .................................................................................................. 103
Table 6.2.13-2 Interrupt Number Table........................................................................................ 104
Table 6.2.14-1 Priority Grouping.................................................................................................. 135
Table 6.3.9-1 The symbol definition of PLL Output Frequency formula ...................................... 167
Table 6.4.4-1 Flash Memory Address Map.................................................................................. 195
Table 6.4.4-2 Boot Configuration................................................................................................. 196
Table 6.4.4-3 ISP Command List................................................................................................. 201
Table 6.4.4-4 FMC control registers for Flash Read/Write .......................................................... 202
Table 6.4.4-5 Flash Access Optimized Cycle under auto-tuning function................................... 212
Table 6.4.4-6 The lock effect table with two protections.............................................................. 214
Table 6.5.5-1 De-Bounce Function Setting Table........................................................................ 245
Table 6.6.5-1 Channel Priority Table ........................................................................................... 266
Table 6.7.6-1 PWM Pulse Generation Event Priority in Up Count Type...................................... 356
Table 6.7.6-2 PWM Pulse Generation Event Priority in Down Count Type................................. 357
Table 6.7.6-3 PWM Pulse Generation Event Priority in Up-Down Count Type........................... 357
Table 6.8.3-1 PWM System Clock Source Control Registers Setting Table ............................... 405
Table 6.8.5-1 PWM Pulse Generation Event Priority for Up-Counter.......................................... 419
Table 6.8.5-2 PWM Pulse Generation Event Priority for Down-Counter..................................... 420
Table 6.8.5-3 PWM Pulse Generation Event Priority for Up-Down-Counter ............................... 420
Table 6.9.5-1 Watchdog Timer Time-out Interval Period Selection............................................. 527
Table 6.10.5-1 WWDT Prescaler Value Selection....................................................................... 535

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Table 6.10.5-2 CMPDAT Setting Limitation................................................................................. 537
Table 6.11.5-1 RTC Read/Write Enable ...................................................................................... 546
Table 6.11.5-2 12/24 hour Time Scale Selection......................................................................... 547
Table 6.11.5-3 Registers value after power-on............................................................................ 548
Table 6.12.2-1 UART Feature...................................................................................................... 567
Table 6.12.3-1 UART Interrupt..................................................................................................... 570
Table 6.12.4-1 UART Interface Controller Pin ............................................................................. 571
Table 6.12.5-1 UART controller Baud Rate Equation Table........................................................ 571
Table 6.12.5-2 UART controller Baud Rate Parameter Setting Example Table.......................... 572
Table 6.12.5-3 UART controller Baud Rate Register Setting Example Table ............................. 572
Table 6.12.5-4 Baud Rate Compensation Example Table 1 ....................................................... 573
Table 6.12.5-5 Baud Rate Compensation Example Table 2 ....................................................... 573
Table 6.12.5-6 UART controller Interrupt Source and Flag List................................................... 580
Table 6.12.5-7 UART Line Control of Word and Stop Length Setting ......................................... 581
Table 6.12.5-8 UART Line Control of Parity Bit Setting............................................................... 581
Table 6.13.5-1 Reserved SMBus Address................................................................................... 637
Table 6.13.5-2 Relationship between I2C Baud Rate and PCLK................................................. 642
Table 6.13.5-3 I2C Status Code Description................................................................................ 645
Table 6.14.2-1 SPI feature difference (SPI0~SPI2)..................................................................... 675
Table 6.16.5-1 The relation between resolution and conversion cycles...................................... 762
Table 6.16.5-2 EADC Power Saving Mode.................................................................................. 769
Table 6.16.5-3 EADC minimum sampling time............................................................................ 770
Table 6.19.5-1 Example for DMIC bus clock and OSR configuring............................................. 868
Table 6.20.5-1 Short Term Power Attack Time Selection............................................................ 883
Table 6.20.5-2 Long Term Power Attack Time Selection ............................................................ 883
Table 6.20.5-3 Power Threshold Reference................................................................................ 884

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1 GENERAL DESCRIPTION
The ISD94100 series 32-bit microcontrollers are an embedded ARM®Cortex®-M4F core with DSP
extensions and a Floating Point Unit which run up to 200 MHz. It provides up to 512 KB of flash
memory and up to 192 KB of SRAM. It is ideal for consumer product applications which need
communication interfaces and high computing power.
The ISD94100 is also equipped with a variety of peripheral devices, such as Multi-Function Timers,
Watchdog Timers, RTC, PDMA, UART, SPI, I2C, PWM, GPIO, 12-bit ADC, USB1.1 Device, Low
voltage reset and Brown-out Detector. In addition, it supports plenty of audio peripherals such as
I2S, DMIC and audio DPWM modulator.
The ISD94100 series is suitable for a wide range of applications such as:
Audio Processing Platform
Consumer Products
Industrial Automation
Home Automation
Security Alarm System
System Supervisors

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2 FEATURES
2.1 ISD94100 Series Features
Core
– ARM®Cortex®-M4F core running up to 200 MHz
– Supports DSP extension with hardware divider
– Supports IEEE 754 compliant Floating-point Unit (FPU)
– Supports Memory Protection Unit (MPU)
– One 24-bit system timer
– Supports Low Power Sleepmode by WFI and WFE instructions
– Single-cycle 32-bit hardware multiplier
– Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
(NVIC)
– Supports programmable mask-able interrupts
– Supports Embedded Trace Macrocell
Built-in LDO for wide operating voltage range
Flash Memory
– Up to 512KB on-chip Application ROM (APROM)
– Configurable program code/data allocation
– 4 KB Flash for loader (LDROM)
– Supports 2-wire ICP update through SWD/ICE interface
– Supports In-system program (ISP), In application program (IAP) update
– Supports 4 KB page erase for all embedded flash
– Supports 4 KB two-way cache to reduce power consumption and improve
performance.
– Enhanced performance up to 3.4 Core Mark/MHz when running code in Flash with
cache
– Supports 2-wire ICP flash updating through SWD interface
– Supports 32-bit/64-bit and multi-word flash programming function.
– Supports fast flash programming verification by CRC function.
SRAM
– Up to 192 KB embedded SRAM
– 32 KB SRAM in bank 0 that supports hardware parity check and retention mode
– Supports byte-, half-word- and word-access
– Supports exception (NMI) generated once a parity check error occurs
– Supports PDMA mode
Clock Control
– Built-in 48.0 MHz or 49.152 MHz selectable internal high speed RC oscillator (HIRC) for
system operation
– Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-
up operation
– 4~24.576 MHz external high speed crystal oscillator (HXT) for precise timing operation
– 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power

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system operation
– Supports one PLL up to 500 MHz for high performance system operation, sourced from
HIRC or HXT
– Supports clock failure detection for high/low speed external crystal oscillator
– Supports exception (NMI) generation once a clock failure detected
– Supports clock output
GPIO
– Supports four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable
– I/O pin configured as interrupt source with edge/level trigger setting
– Supports high slew driver and high sink current I/O (up to 20mA at 3.3V)
– Supports software selectable slew rate control
– Supports 5V tolerance function on subset of GPIO except analog I/O
PDMA (Peripheral DMA)
– Supports 16 independent configurable channels for automatic data transfer between
memories and peripherals
– Supports stride function.
– Channel 0, 1 supports time-out function for each channel.
– Supports Basic and Scatter-Gather Transfer modes
– Each channel supports circular buffer management using Scatter-Gather Transfer mode
– Supports two types of priorities modes: Fixed-priority and Round-robin modes
– Supports byte-, half-word- and word-access
– Supports single and burst transfer type
– Supports source and destination address can be increment or fixed.
– DMA transfer count up to 65536.
Multi-Function Timer (MFT, Timer + PWM)
– TIMER mode
Supports 4 sets of 32-bit timers with 24-bit up-timer and 8-bit prescale counter,
24-bit up counter value is readable.
Independent clock source for each timer
Provides One-shot, Periodic, Toggle and Continuous Counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Supports external capture pin event for interval measurement.
Supports external capture pin event to reset 24-bit up counter.
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to
trigger PWM, EADC and DMA.
Supports Inter-Timer trigger mode
– PWM mode
Supports four 16-bit PWM counters with 10-bit dead time generator
Supports 12-bit pre-scale for PWM.