Nuvoton ISD94124BYI Product manual

ISD94100 Series Technical Reference Manual
Sep 9, 2019 Page 1of 928 Rev1.09
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
ISD ARM®Cortex®-M4F SoC
ISD94100 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of microcontroller based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
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TABLE OF CONTENTS
1GENERAL DESCRIPTION ............................................................ 18
2FEATURES .............................................................................. 19
2.1 ISD94100 Series Features ................................................................ 19
3ABBREVIATIONS....................................................................... 26
3.1 Abbreviations................................................................................ 26
4PARTS INFORMATION LIST AND PIN CONFIGURATION..................... 28
4.1 Parts Information............................................................................ 28
4.2 Ordering Information ....................................................................... 29
4.3 Pin Configuration............................................................................ 31
4.3.1 QFN48 (6x6 mm) Pin Diagram ...................................................................31
4.3.2 LQFP64 (7x7 mm) Pin Diagram..................................................................32
4.3.3 LQFP64 (10x10 mm) Pin Diagram...............................................................33
4.4 Pin Description .............................................................................. 34
4.5 GPIO Alternate Function Summary...................................................... 43
5BLOCK DIAGRAM...................................................................... 45
5.1 ISD94100 Series Block Diagram......................................................... 45
6FUNCTIONAL DESCRIPTION........................................................ 46
6.1 ARM®Cortex®-M4 Core.................................................................... 46
6.2 System Manager............................................................................ 49
6.2.1 Overview .............................................................................................49
6.2.2 System Reset........................................................................................49
6.2.3 System Power Distribution ........................................................................53
6.2.4 Power Modes........................................................................................54
6.2.5 Power Modes Settings and Wake-up Sources.................................................56
6.2.6 Brown-out Detector and Low Voltage Reset Controller Configuration .....................61
6.2.7 System Memory Map...............................................................................62
6.2.8 SRAM Memory Organization .....................................................................63
6.2.9 HIRC Auto Trim .....................................................................................64
6.2.10 Register Map......................................................................................66
6.2.11 Register Description.............................................................................67
6.2.12 System Timer (SysTick).........................................................................98
6.2.13 Nested Vectored Interrupt Controller (NVIC) ..............................................102

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6.2.14 System Control Register......................................................................131
6.3 Clock Controller ............................................................................140
6.3.1 Overview ...........................................................................................140
6.3.2 Clock Generator...................................................................................142
6.3.3 System Clock and SysTick Clock ..............................................................143
6.3.4 Peripheral Clock ..................................................................................145
6.3.5 Power-down Mode Clock........................................................................145
6.3.6 Clock Output.......................................................................................145
6.3.7 Clock Setting Limitation..........................................................................146
6.3.8 Register Map ......................................................................................147
6.3.9 Register Description..............................................................................149
6.4 Flash Memory Controller (FMC).........................................................191
6.4.1 Overview ...........................................................................................191
6.4.2 Features............................................................................................191
6.4.3 Block Diagram.....................................................................................192
6.4.4 Functional Description ...........................................................................194
6.4.5 Register Map ......................................................................................215
6.4.6 Register Description..............................................................................217
6.5 General Purpose I/O (GPIO).............................................................240
6.5.1 Overview ...........................................................................................240
6.5.2 Features............................................................................................240
6.5.3 Block Diagram.....................................................................................240
6.5.4 Basic Configuration...............................................................................241
6.5.5 Functional Description ...........................................................................242
6.5.6 Register Map ......................................................................................246
6.5.7 Register Description..............................................................................248
6.6 PDMA Controller (PDMA) ................................................................264
6.6.1 Overview ...........................................................................................264
6.6.2 Features............................................................................................264
6.6.3 Block Diagram.....................................................................................264
6.6.4 Basic Configuration...............................................................................265
6.6.5 Functional Description ...........................................................................265
6.6.6 Register Map ......................................................................................273
6.6.7 Register Description..............................................................................278
6.7 Timer Controller (TMR) ...................................................................338

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6.7.1 Overview ...........................................................................................338
6.7.2 Features............................................................................................338
6.7.3 Block Diagram.....................................................................................340
6.7.4 Basic Configuration...............................................................................344
6.7.5 Timer Functional Description ...................................................................345
6.7.6 PWM Functional Description....................................................................350
6.7.7 Register Map ......................................................................................363
6.7.8 Register Description..............................................................................368
6.8 PWM Generator and Capture Timer (PWM) ..........................................402
6.8.1 Overview ...........................................................................................402
6.8.2 Features............................................................................................402
6.8.3 Block Diagram.....................................................................................404
6.8.4 Basic Configuration...............................................................................407
6.8.5 Functional Description ...........................................................................408
6.8.6 Register Map ......................................................................................439
6.8.7 Register Description..............................................................................443
6.9 Watchdog Timer (WDT)...................................................................525
6.9.1 Overview ...........................................................................................525
6.9.2 Features............................................................................................525
6.9.3 Block Diagram.....................................................................................525
6.9.4 Basic Configuration...............................................................................525
6.9.5 Functional Description ...........................................................................526
6.9.6 Register Map ......................................................................................529
6.9.7 Register Description..............................................................................530
6.10 Window Watchdog Timer (WWDT) .....................................................533
6.10.1 Overview ........................................................................................533
6.10.2 Features .........................................................................................533
6.10.3 Block Diagram ..................................................................................533
6.10.4 Basic Configuration............................................................................534
6.10.5 Functional Description.........................................................................534
6.10.6 Register Map....................................................................................538
6.10.7 Register Description...........................................................................539
6.11 Real Time Clock (RTC) ...................................................................544
6.11.1 Overview ........................................................................................544
6.11.2 Features .........................................................................................544

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6.11.3 Block Diagram ..................................................................................545
6.11.4 Basic Configuration............................................................................545
6.11.5 Functional Description.........................................................................545
6.11.6 Register Map....................................................................................549
6.11.7 Register Description...........................................................................550
6.12 UART Interface Controller (UART)......................................................566
6.12.1 Overview ........................................................................................566
6.12.2 Features .........................................................................................566
6.12.3 Block Diagram ..................................................................................567
6.12.4 Basic Configuration............................................................................570
6.12.5 Functional Description.........................................................................571
6.12.6 Register Map....................................................................................588
6.12.7 Register Description...........................................................................589
6.13 I2C Serial Interface Controller (I2C) .....................................................617
6.13.1 Overview ........................................................................................617
6.13.2 Features .........................................................................................617
6.13.3 Block Diagram ..................................................................................617
6.13.4 Basic Configuration............................................................................618
6.13.5 Functional Description.........................................................................619
6.13.6 Register Map....................................................................................650
6.13.7 Register Description...........................................................................652
6.14 Serial Peripheral Interface (SPI).........................................................674
6.14.1 Overview ........................................................................................674
6.14.2 Features .........................................................................................674
6.14.3 Block Diagram ..................................................................................676
6.14.4 Basic Configuration............................................................................678
6.14.5 Functional Description.........................................................................680
6.14.6 Timing Diagram ................................................................................704
6.14.7 Programming Examples ......................................................................706
6.14.8 Register Map....................................................................................708
6.14.9 Register Description...........................................................................710
6.15 CRC Controller (CRC) ....................................................................746
6.15.1 Overview ........................................................................................746
6.15.2 Features .........................................................................................746
6.15.3 Block Diagram ..................................................................................747

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6.15.4 Basic Configuration............................................................................747
6.15.5 Functional Description.........................................................................747
6.15.6 Register Map....................................................................................749
6.15.7 Register Description...........................................................................750
6.16 Enhanced 12-bit Analog-to-Digital Converter (EADC)...............................755
6.16.1 Overview ........................................................................................755
6.16.2 Features .........................................................................................755
6.16.3 Block Diagram..................................................................................756
6.16.4 Basic Configuration............................................................................756
6.16.5 Functional Description.........................................................................757
6.16.6 Register Map....................................................................................771
6.16.7 Register Description...........................................................................774
6.17 I2S Controller (I2S) .........................................................................801
6.17.1 Overview ........................................................................................801
6.17.2 Features .........................................................................................801
6.17.3 Block Diagram ..................................................................................802
6.17.4 Basic Configuration............................................................................802
6.17.5 Functional Description.........................................................................803
6.17.6 Register Map....................................................................................814
6.17.7 Register Description...........................................................................815
6.18 USB 1.1 Device Controller (USBD).....................................................833
6.18.1 Overview ........................................................................................833
6.18.2 Features .........................................................................................833
6.18.3 Block Diagram ..................................................................................834
6.18.4 Basic Configuration............................................................................834
6.18.5 Functional Description.........................................................................835
6.18.6 Register Map....................................................................................839
6.18.7 Register Description...........................................................................842
6.19 Digital Microphone Inputs (DMIC).......................................................866
6.19.1 Overview ........................................................................................866
6.19.2 Features .........................................................................................866
6.19.3 Block Diagram..................................................................................866
6.19.4 Basic Configuration............................................................................866
6.19.5 Functional Description.........................................................................867
6.19.6 Register Map....................................................................................871

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6.19.7 Register Description...........................................................................872
6.20 Voice Active Detection (VAD)............................................................879
6.20.1 Overview ........................................................................................879
6.20.2 Features .........................................................................................879
6.20.3 Block Diagram ..................................................................................879
6.20.4 Basic Configuration............................................................................879
6.20.5 Functional Description.........................................................................879
6.20.6 Register Map....................................................................................885
6.20.7 Register Description...........................................................................886
6.21 Audio DPWM Modulator (DPWM).......................................................897
6.21.1 Overview ........................................................................................897
6.21.2 Features .........................................................................................897
6.21.3 Block Diagram ..................................................................................897
6.21.4 Basic Configuration............................................................................897
6.21.5 Functional Description.........................................................................898
6.21.6 Register Map....................................................................................905
6.21.7 Register Description...........................................................................910
7ELECTRICAL CHARACTERISTICS................................................922
8APPLICATION CIRCUIT..............................................................923
9PACKAGE DIMENSIONS ............................................................924
9.1 QFN 48L (6x6x0.8 mm3 Pitch 0.4 mm) .................................................924
9.2 LQFP 64L (7x7x1.4 mm footprint 2.0 mm).............................................925
9.3 LQFP 64L (10x10x1.4 mm footprint 2.0 mm) .........................................926
10 REVISION HISTORY..................................................................927

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List of Figure
Figure 4.2-1 Ordering Information Scheme ................................................................................... 29
Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram.................................................................................. 31
Figure 4.3-2 LQFP64 (7x7 mm) Pin Diagram ................................................................................ 32
Figure 4.3-3 LQFP64 (10x10 mm) Pin Diagram ............................................................................ 33
Figure 5.1-1 ISD94100 Series Block Diagram............................................................................... 45
Figure 6.1-1 Cortex®-M4 Block Diagram........................................................................................ 46
Figure 6.2-1 System Reset Sources.............................................................................................. 50
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 51
Figure 6.2-3 Brown-out Detector (BOD) Waveform....................................................................... 52
Figure 6.2-4 ISD94100 Series Power Distribution Diagram .......................................................... 54
Figure 6.2-5 ISD94100 Series Power Mode State Machine.......................................................... 57
Figure 6.2-6 SRAM Block Diagram................................................................................................ 63
Figure 6.2-7 SRAM Memory Organization..................................................................................... 64
Figure 6.3-1 Clock Generator Global View Diagram.................................................................... 141
Figure 6.3-2 Clock Generator Block Diagram.............................................................................. 142
Figure 6.3-3 System Clock Block Diagram .................................................................................. 143
Figure 6.3-4 HXT Stop Protect Procedure................................................................................... 144
Figure 6.3-5 SysTick Clock Control Block Diagram..................................................................... 144
Figure 6.3-6 Clock Output Block Diagram ................................................................................... 145
Figure 6.4-1 Flash Memory Controller Block Diagram................................................................. 192
Figure 6.4-2 Memory Organization .............................................................................................. 194
Figure 6.4-3 Data Flash Shared with 512 KB APRM example .................................................... 194
Figure 6.4-4 Boot from LDROM with IAP support........................................................................ 196
Figure 6.4-5 Boot from APROM with IAP support........................................................................ 197
Figure 6.4-6 Boot from LDROM without IAP support................................................................... 198
Figure 6.4-7 Boot from APROM without IAP support................................................................... 198
Figure 6.4-8 ISP Procedure Example .......................................................................................... 201
Figure 6.4-9 flash 32-bit write procedure ..................................................................................... 203
Figure 6.4-10 Flash 64-bit write procedure.................................................................................. 204
Figure 6.4-11 Timeline comparison for write operations.............................................................. 205
Figure 6.4-12 Firmware in SRAM for Multi-word Programming................................................... 205
Figure 6.4-13 Multi-word programming flow chart ....................................................................... 207
Figure 6.4-14 Fast Flash Programming Verification Flow............................................................ 208
Figure 6.4-15 Verification Flow .................................................................................................... 209
Figure 6.4-16 Flash CRC32 Checksum Calculation.................................................................... 209

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Figure 6.4-17 Flash access cycle auto-tuning flow...................................................................... 213
Figure 6.5-1 GPIO Controller Block Diagram............................................................................... 241
Figure 6.5-2 Push-Pull Output...................................................................................................... 242
Figure 6.5-3 Open-Drain Output .................................................................................................. 243
Figure 6.5-4 Quasi-Bidirectional I/O Mode................................................................................... 243
Figure 6.5-5 GPIO Rising Edge Trigger Interrupt ........................................................................ 244
Figure 6.5-6 GPIO Falling Edge Trigger Interrupt........................................................................ 245
Figure 6.6-1 PDMA Controller Block Diagram ............................................................................. 264
Figure 6.6-2 Descriptor Table Entry Structure ............................................................................. 265
Figure 6.6-3 Basic Mode Finite State Machine............................................................................ 267
Figure 6.6-4 Descriptor Table Link List Structure ........................................................................ 268
Figure 6.6-5 Scatter-Gather Mode Finite State Machine............................................................. 268
Figure 6.6-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode ............ 270
Figure 6.6-7 Example of PDMA Channel 0 Time-out Counter Operation.................................... 271
Figure 6.6-8 Stride Function Block Transfer................................................................................ 271
Figure 6.7-1 Timer Controller Block Diagram .............................................................................. 340
Figure 6.7-2 Clock Source of Timer Controller ............................................................................ 341
Figure 6.7-3 PWM Generator Overview Block Diagram.............................................................. 342
Figure 6.7-4 PWM System Clock Source Control........................................................................ 342
Figure 6.7-5 PWM Counter Clock Source Control....................................................................... 343
Figure 6.7-6 PWM Independent Mode Architecture Diagram...................................................... 343
Figure 6.7-7 PWM Complementary Mode Architecture Diagram ................................................ 344
Figure 6.7-8 Continuous Counting Mode..................................................................................... 347
Figure 6.7-9 External Capture Mode............................................................................................ 348
Figure 6.7-10 External Reset Counter Mode ......................................................................... 348
Figure 6.7-11 Internal Timer Trigger............................................................................................ 349
Figure 6.7-12 Inter-Timer Trigger Capture Timing....................................................................... 350
Figure 6.7-13 PWM Prescale Waveform in Up Count Type ........................................................ 351
Figure 6.7-14 PWM Up Count Type............................................................................................. 351
Figure 6.7-15 PWM Down Count Type........................................................................................ 352
Figure 6.7-16 PWM Up-Down Count Type .................................................................................. 352
Figure 6.7-17 PWM Comparator Events in Up-Down Count Type.............................................. 353
Figure 6.7-18 Period Loading Mode with Up Count Type............................................................ 354
Figure 6.7-19 Immediately Loading Mode with Up Count Type................................................... 355
Figure 6.7-20 PWM Pulse Generation in Up-Down Count Type ................................................. 355
Figure 6.7-21 PWM Pulse Generation in Up Count Type............................................................ 356
Figure 6.7-22 PWM Pulse Generation in Down Count Type ....................................................... 356

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Figure 6.7-23 PWM 0% to 100% Duty Cycle in Up Count Type and Up-Down Count Type....... 357
Figure 6.7-24 PWM Independent Mode Output Waveform ......................................................... 358
Figure 6.7-25 PWM Complementary Mode Output Waveform.................................................... 358
Figure 6.7-26 PWMx_CH0 Output Control in Independent Mode ............................................... 358
Figure 6.7-27 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode.............. 359
Figure 6.7-28 Dead-Time Insertion.............................................................................................. 359
Figure 6.7-29 PWM Output Mask Control Waveform .................................................................. 360
Figure 6.7-30 PWMx_CH0 and PWMx_CH1 Polarity Control with Dead-Time Insertion............ 361
Figure 6.7-31 PWM Interrupt Architecture Diagram..................................................................... 362
Figure 6.7-32 PWM Trigger ADC Block Diagram ........................................................................ 362
Figure 6.8-1 PWM Generator Overview Block Diagram.............................................................. 404
Figure 6.8-2 PWM System Clock Source Control........................................................................ 404
Figure 6.8-3 PWM Clock Source Control..................................................................................... 405
Figure 6.8-4 PWM Independent Mode Architecture Diagram...................................................... 406
Figure 6.8-5 PWM Complementary Mode Architecture Diagram ................................................ 407
Figure 6.8-6 PWM0_CH0 Prescaler Waveform in Up Counter Type........................................... 408
Figure 6.8-7 PWM0 Counter Waveform when set clear counter ................................................. 409
Figure 6.8-8 PWM Up Counter Type............................................................................................ 409
Figure 6.8-9 PWM Down Counter Type....................................................................................... 410
Figure 6.8-10 PWM Up-Down Counter Type............................................................................... 411
Figure 6.8-11 PWM Compared point Events in Up-Down Counter Type .................................... 412
Figure 6.8-12 PWM Double Buffering Illustration......................................................................... 413
Figure 6.8-13 Period Loading in Up-Count Mode........................................................................ 414
Figure 6.8-14 Immediately Loading in Up-Count Mode............................................................... 415
Figure 6.8-15 Window Loading in Up-Count Mode...................................................................... 416
Figure 6.8-16 Center Loading in Up-Down-Count Mode ............................................................. 417
Figure 6.8-17 PWM One-shot Mode Output Waveform............................................................... 418
Figure 6.8-18 PWM Pulse Generation......................................................................................... 419
Figure 6.8-19 PWM 0% to 100% Pulse Generation..................................................................... 419
Figure 6.8-20 PWM Independent Mode Waveform ..................................................................... 421
Figure 6.8-21 PWM Complementary Mode Waveform................................................................ 421
Figure 6.8-22 PWM Group Function Waveform........................................................................... 422
Figure 6.8-23 PWM SYNC_IN Noise Filter Block Diagram ......................................................... 423
Figure 6.8-24 PWM Counter Synchronous Function Block Diagram........................................... 424
Figure 6.8-25 PWM Synchronous Function with Synchronize source from SYNC_IN Signal..... 425
Figure 6.8-26 PWM0_CH0 Output Control in Independent Mode............................................... 425
Figure 6.8-27 PWM0_CH0 and PWM0_CH1 Output Control in Complementary Mode.............. 426